阅读说明：本技术 用于雷达芯片同步的设备和方法 (Apparatus and method for radar chip synchronization ) 是由 P·C·达托 于 2019-08-13 设计创作，主要内容包括：本公开涉及用于雷达芯片同步的设备和方法。在某些实施方式中,参考时钟信号被分配给两个或更多个半导体芯片,每个半导体芯片包括至少一个数据转换器。两个或更多个芯片包括产生数据转换器同步信号的主芯片,以及处理数据转换器同步信号以对准芯片上的数据转换操作的定时例如以获得高度数字采样的定时相干性的的至少一个从芯片。在某些实施方式中,芯片对应于雷达系统的雷达芯片,而数据转换器同步信号对应于模数转换器(ADC)同步信号。芯片对应于雷达系统的雷达芯片,而数据转换器同步信号对应于模数转换器(ADC)同步信号。另外,主雷达芯片产生斜坡同步信号,以同步雷达芯片的传输顺序和/或提供ADC时钟信号的相位对准。(The present disclosure relates to an apparatus and method for radar chip synchronization. In some embodiments, the reference clock signal is distributed to two or more semiconductor chips, each semiconductor chip including at least one data converter. The two or more chips include a master chip that generates data converter synchronization signals, and at least one slave chip that processes the data converter synchronization signals to align the timing of data conversion operations on the chips, e.g., to obtain a high degree of timing coherence of the digital samples. In some embodiments, the chip corresponds to a radar chip of a radar system and the data converter synchronization signal corresponds to an analog-to-digital converter (ADC) synchronization signal. The chip corresponds to a radar chip of the radar system and the data converter synchronization signal corresponds to an analog-to-digital converter (ADC) synchronization signal. In addition, the master radar chip generates ramp synchronization signals to synchronize the transmission sequence of the radar chips and/or provide phase alignment of the ADC clock signals.)

1. A radar system with synchronized timing, the radar system comprising:

a first radar chip comprising a first analog-to-digital converter (ADC) circuit and a first phase-locked loop (PLL) configured to process a reference clock signal to generate a first ADC clock signal that controls timing of the first ADC circuit, wherein the first radar chip is further configured to generate an ADC synchronization signal based on the timing of the first ADC clock signal; and

a second radar chip comprising a second ADC circuit and a second PLL configured to process the reference clock signal to generate a second ADC clock signal that controls timing of the second ADC circuit, wherein the second radar chip is further configured to align sampling operations of the second ADC circuit with sampling operations of the first ADC circuit based on the ADC synchronization signal.

2. The radar system of claim 1, wherein the first radar chip is further configured to generate a ramp synchronization signal based on a timing of the reference clock signal, wherein the second radar chip is configured to align a transmission sequencing operation of the second radar chip with a transmission sequencing operation of the first radar chip based on the ramp synchronization signal.

3. The radar system of claim 2, wherein the second radar chip is configured to process the ramp synchronization signal to synchronize a reset of the second PLL with a reset of the first PLL.

4. The radar system of claim 2, wherein the first radar chip further comprises a frequency ramp generator, wherein the first radar chip is configured to activate the ramp synchronization signal and then control the frequency ramp generator to provide a transmission sequencing operation after one or more cycles of the reference clock signal.

5. The radar system of claim 1, wherein the first radar chip further comprises a first time-to-digital converter (TDC) configured to provide a phase adjustment to the first ADC clock signal based on measuring a time delay between the reference clock signal and the first ADC clock signal.

6. The radar system of claim 5, wherein the second radar chip further comprises a second TDC configured to provide a phase adjustment to the second ADC clock signal based on measuring a time delay between the reference clock signal and the second ADC clock signal, wherein the first TDC and the second TDC operate to compensate for a difference in clock path delay between the first radar chip and the second radar chip.

7. The radar system of claim 1, further comprising a third radar chip including a third ADC circuit and a third PLL configured to process the reference clock signal to generate a third ADC clock signal that controls timing of the third ADC circuit, wherein the third radar chip is configured to control timing of sampling operations of the third ADC circuit based on the ADC synchronization signal.

8. A semiconductor chip for controlling synchronization of a multichip radar system, the semiconductor chip comprising:

a Phase Locked Loop (PLL) configured to generate an analog-to-digital converter (ADC) clock signal based on a timing of a reference clock signal;

an ADC circuit controlled by the ADC clock signal;

an ADC synchronization signal generation circuit configured to generate an ADC synchronization signal based on a timing of the ADC clock signal; and

a first pin configured to output an ADC synchronization signal to coordinate synchronization of the multichip radar system.

9. The semiconductor chip of claim 8, further comprising: a ramp synchronization signal generation circuit configured to generate a ramp synchronization signal based on a timing of the reference clock signal; and a second pin configured to output the ramp synchronization signal.

10. The semiconductor chip of claim 9, wherein the ADC synchronization signal and the ramp synchronization signal are generated in different time domains.

11. The semiconductor chip of claim 9, further comprising a frequency ramp generator configured to initiate a frequency ramp of one or more cycles of the reference clock signal after activating the ramp synchronization signal.

12. The semiconductor chip of claim 9, wherein the ramp synchronization signal generation circuit is further configured to control the ramp synchronization signal to indicate a phase alignment operation, wherein the PLL is configured to reset in response to the phase alignment operation.

13. The semiconductor chip of claim 8, further comprising a time-to-digital converter (TDC) configured to provide a phase adjustment to the ADC clock signal based on measuring a time delay between the reference clock signal and the ADC clock signal.

14. The semiconductor chip of claim 13, wherein the ADC PLL comprises an output divider configured to output an ADC clock signal, wherein the TDC provides phase adjustment based at least in part on controlling a reset delay of the output divider.

15. The semiconductor chip of claim 8, further comprising a frequency divider configured to divide the ADC clock signal to generate an Analog Front End (AFE) clock signal, wherein the ADC synchronization signal and the AFE clock signal are synchronized.

16. The semiconductor chip of claim 15, further comprising a filter circuit clocked by the AFE clock signal and configured to process a digital output signal of the ADC circuit.

17. A method of synchronizing radar chips, the method comprising:

synthesizing a first analog-to-digital converter (ADC) clock signal in a first radar chip based on a timing of a reference clock signal;

controlling an analog-to-digital conversion operation in a first radar chip using the first ADC clock signal;

generating an ADC synchronization signal in the first radar chip based on the timing of the first ADC clock signal;

providing an ADC synchronization signal from the first radar chip to a second radar chip; and

processing an ADC synchronization signal in the second radar chip to synchronize analog-to-digital conversion operations in the second radar chip with analog-to-digital conversion operations in the first radar chip.

18. The method of claim 17, further comprising generating a ramp synchronization signal in the first radar chip based on timing of the reference clock signal, providing a ramp synchronization signal from the first radar chip to the second radar chip, and synchronizing a transmission sequencing operation of the second radar chip with a transmission sequencing operation of the first radar chip using the ramp synchronization signal.

19. The method of claim 18, further comprising synthesizing a second ADC clock signal in the second radar chip based on the timing of the reference clock signal and aligning the first ADC clock signal with the second ADC clock signal using the ramp synchronization signal.

20. The method of claim 19, wherein aligning the first ADC clock signal with the second ADC clock signal further comprises adjusting a first clock path delay from the reference clock signal to the first ADC clock signal using a first time-to-digital converter (TDC), and adjusting a second clock path delay from the reference clock signal to the second ADC clock signal using a second TDC.

Technical Field

Embodiments of the present invention relate to electronic systems, and more particularly, to synchronization of one or more semiconductor chips.

Background

An electronic system may include a plurality of semiconductor chips for processing data based on timing of a reference clock signal. For example, a radar system, a telecommunication system, a parallel data processing system, and/or a chip-to-chip communication system may include several chips for processing data in multiple channels or channels. Including multiple chips for processing data may provide many advantages, such as wider bandwidth, greater flexibility, reduced cost, and/or expanded application scope.

Disclosure of Invention

Apparatus and methods for synchronizing radar chips are provided herein. In some embodiments, the reference clock signal is distributed to two or more radar chips, each radar chip including at least one analog-to-digital converter (ADC). The two or more radar chips include a master chip that generates ADC synchronization signals, and at least one slave chip that processes the ADC synchronization signals to align the timing of data conversion operations on the chips, e.g., to obtain a high degree of timing coherence for digital sampling. In some embodiments, the master chip generates ramp synchronization signals to synchronize the transmission sequence of the radar chip and/or provide phase alignment of the ADC clock signals.

In one aspect, a radar system with synchronized timing is provided. The radar system includes: a first radar chip including a first analog-to-digital converter (ADC) circuit and a first phase-locked loop (PLL) configured to process a reference clock signal to generate a first ADC clock signal that controls timing of the first ADC circuit. The first radar chip is further configured to generate an ADC synchronization signal based on timing of the first ADC clock signal. The radar system also includes a second radar chip including a second ADC circuit and a second PLL configured to process the reference clock signal to generate a second ADC clock signal that controls timing of the second ADC circuit. The second radar chip is further configured to align a sampling operation of the second ADC circuit with a sampling operation of the first ADC circuit based on the ADC synchronization signal.

In another aspect, a semiconductor chip for controlling synchronization of a multichip radar system is provided. The semiconductor chip includes: a Phase Locked Loop (PLL) configured to generate an analog-to-digital converter (ADC) clock signal based on a timing of a reference clock signal; an ADC circuit controlled by the ADC clock signal; an ADC synchronization signal generation circuit configured to generate an ADC synchronization signal based on a timing of the ADC clock signal; and a first pin configured to output an ADC synchronization signal to coordinate synchronization of the multichip radar system.

In another aspect, a method of synchronizing radar chips is provided. The method comprises the following steps: synthesizing a first analog-to-digital converter (ADC) clock signal in a first radar chip based on a timing of a reference clock signal; controlling an analog-to-digital conversion operation in a first radar chip using the first ADC clock signal; generating an ADC synchronization signal in the first radar chip based on the timing of the first ADC clock signal; providing an ADC synchronization signal from the first radar chip to a second radar chip; and processing an ADC synchronization signal in the second radar chip to synchronize an analog-to-digital conversion operation in the second radar chip with an analog-to-digital conversion operation in the first radar chip.

In another aspect, a semiconductor chip is provided that compensates for variations in clock path delay. The semiconductor chip includes: a Phase Locked Loop (PLL) configured to generate a synthesized clock signal based on a timing of a reference clock signal, the PLL including a controllable phase shifter configured to control a phase of the synthesized clock signal. The semiconductor chip further includes: a time-to-digital converter (TDC) configured to generate a first digital timestamp indicative of a transition time of a reference clock signal and a second digital timestamp indicative of a transition time of a synthesized clock signal, and to generate a clock delay detection signal based on the first digital timestamp and the second digital timestamp. The TDC is configured to control an amount of phase shift provided by the controllable phase shifter based on the clock delay detection signal. In some embodiments, the amount of phase shift provided by the TDC provides a coarse phase shift, and the PLL is further controlled by a fine phase shift. In some embodiments, the fine phase shift is generated based on one or more TDC measurements.

In another aspect, a semiconductor chip for controlling multi-chip synchronization is provided. The semiconductor chip includes: a Phase Locked Loop (PLL) configured to generate a synthesized clock signal based on a timing of a reference clock signal; a data converter circuit controlled by the synthesized clock signal; a first synchronization circuit configured to generate a data converter synchronization signal in a time domain of the synthesized clock signal; and a second synchronization circuit configured to generate a PLL clock alignment signal in a time domain of the reference clock signal. The semiconductor chip is configured to output a data converter synchronization signal and a PLL clock alignment signal to coordinate multi-chip synchronization.

In another aspect, an electronic system with timing synchronization is provided. The electronic system includes: a first semiconductor chip including a first Phase Locked Loop (PLL) configured to generate a first data converter clock signal based on a timing of a reference clock signal; a first data converter circuit controlled by a first data converter clock signal; and a first synchronization circuit configured to generate a data converter synchronization signal based on a timing of the first data converter clock signal. The electronic system further includes a second semiconductor chip comprising: a second PLL configured to generate a second data converter clock signal based on a timing of the reference clock signal; a second data converter circuit controlled by a second data converter clock signal; and a second semiconductor chip synchronization circuit configured to process the data converter synchronization signal to align the second data converter clock signal with the first data converter clock signal.

Drawings

Fig. 1A is a schematic diagram of one embodiment of a printed circuit board including a plurality of semiconductor chips.

Fig. 1B is a schematic diagram of a multichip system 20 with data transition synchronization, according to one embodiment.

FIG. 2A is a schematic diagram of a multi-chip radar system with synchronization, according to one embodiment.

FIG. 2B is a schematic diagram of a multi-chip radar system with a delay verification circuit, according to one embodiment.

Fig. 3A is a schematic diagram of a multi-chip radar system with synchronization according to another embodiment.

Fig. 3B is an example of a timing diagram for ADC sampling for the multi-chip radar system of fig. 3A.

Fig. 3C is an example of a timing diagram of the ramp synchronization signal.

Fig. 4 is an example of a timing diagram for ramp generation for the multi-chip radar system of fig. 3A.

Fig. 5 is an example of a timing diagram for ADC synchronization for the multi-chip radar system of fig. 3A.

Fig. 6A is a schematic diagram of a multi-chip radar system with phase alignment according to one embodiment.

Fig. 6B is an example of a timing diagram for phase alignment of the multichip radar system of fig. 6A.

Figure 7A is a schematic diagram of an IC including TDC calibration for clock delay according to one embodiment.

Figure 7B is a schematic diagram of an IC including TDC calibration for clock delay according to another embodiment.

Fig. 7C is one example of a timing diagram depicting the resetting of the ADC clock signal.

Fig. 8 is a schematic diagram of an IC with phase alignment according to another embodiment.

Fig. 9 is an example of a timing diagram for phase alignment of a multi-chip radar system implemented in accordance with fig. 8.

Fig. 10 is a schematic diagram of a slave IC having a reset circuit according to one embodiment.

Detailed Description

The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways as defined and covered by the claims. In the description, reference is made to the drawings wherein like reference numbers may indicate identical or functionally similar elements. It should be understood that certain embodiments may include more elements than shown and/or a subset of the elements shown in the figures. Furthermore, some embodiments may incorporate any suitable combination of features from two or more of the figures.

Some electronic systems may include multiple semiconductor chips for processing data. For example, each semiconductor chip may include one or more data converters, such as a digital-to-analog converter (DAC) and/or an analog-to-digital converter (ADC) for providing data conversion between the analog and digital domains. In some embodiments, the data converters operate based on the timing of the common reference clock signal. For example, a beamforming communication system may include multiple receive channels for processing Radio Frequency (RF) signals received from an antenna array, and each receive channel may include a downconverter for downconverting the RF signal to baseband and an ADC for digitizing the baseband signal based on a common timing reference.

In such electronic systems, it may be important that the data converters operate in a synchronized timing relationship. For example, in a beamforming communication system, such as a Frequency Modulated Continuous Wave (FMCW) radar system, the accuracy of beamforming is limited by the phase difference between the clock signals that control the data converters. In addition, large differences in phase may cause the transmit or receive beams of a beamformed communication system to be corrupted. For example, beamforming of receive beams in radar systems depends on high sampling consistency across the ADC, and thus the accuracy of the angular position of a detected object depends on sampling consistency.

Without a mechanism for channel synchronization, such electronic systems may have reduced phase alignment and/or a limit on the maximum number of channels that can operate reliably.

This uniformity of channels can be achieved quite easily when all data converters are located on the same semiconductor chip. However, when the data converter is located on multiple chips (e.g., multiple radar chips), it is difficult to maintain timing coherence across channels.

For example, several ADCs may be distributed over two or more chips, and a common reference clock signal may be provided to each chip to help synchronize the operation of the ADCs. However, many factors may cause the ADC to operate with a phase difference, which may vary between chips and with temperature and/or other operating conditions. For example, each chip may include a Phase Locked Loop (PLL) that uses a reference clock signal to synthesize an ADC clock signal for controlling ADC timing, and the phase difference may come from any initial phase of the PLL, such as a non-deterministic start-up value of a frequency divider, charge pump, and/or battery. In addition, the phase difference may come from other sources, such as differences in path delay of the reference clock signal to each chip and/or manufacturing variations.

The phase difference between the sampling clocks of the data converters causes performance degradation. For example, in a radar system, the phase error is proportional to the frequency of the signal and the phase difference between the clocks of the data converters. Furthermore, in radar applications, it is also desirable to synchronize transmissions across chips.

An apparatus and method for synchronizing a plurality of semiconductor chips is provided herein. In some embodiments, the reference clock signal is distributed to two or more semiconductor chips, each semiconductor chip including at least one data converter. The two or more chips include a master chip that generates data converter synchronization signals, and at least one slave chip that processes the data converter synchronization signals to align timing of data conversion operations on the chips. For example, in some embodiments, the data converter includes an ADC and the master chip generates an ADC synchronization signal for obtaining a high degree of timing coherence for the digital samples.

In some embodiments, the chip corresponds to a radar chip of a radar system. In addition, the master chip also generates ramp synchronization signals to synchronize the transmission sequence on the radar chip (e.g., activation and deactivation of transmissions, alternation of transmissions, simultaneous transmissions, etc.). In addition, the main chip generates an ADC synchronization signal based on the timing of the ADC clock signal of the main chip, and generates a ramp synchronization signal based on the timing of the reference clock signal of the main chip.

Thus, in some embodiments, synchronization of ramp sequencing and ADC sampling is achieved using a pair of synchronization signals, including a ramp synchronization signal and an ADC synchronization signal. Further, the ramp synchronization signal and the ADC synchronization signal have timings associated with different clock domains.

The ramp sync signal is also used to provide phase alignment in some embodiments. For example, different shapes of the ramp synchronization signal (e.g., different bit sequences) may be used to indicate frequency ramp generation or phase alignment. Phase alignment may be provided in various ways. In some embodiments, each semiconductor chip includes a PLL for generating an ADC clock signal based on a reference clock signal, and phase alignment (e.g., reset of an output divider) is provided by controlling timing of reset of the PLL using a ramp synchronization signal. By providing phase alignment, a known phase relationship between the ADC clock signals of the master and slave chips may be achieved.

In some embodiments, each chip includes a time-to-digital converter (TDC) for measuring an internal time delay between a reference clock signal and the ADC clock signal of the chip. By using a TDC in this manner, a reduction in phase difference, including phase differences caused by manufacturing variations and/or operating conditions such as temperature, may be achieved by providing compensation for clock delay errors caused by mismatch. In some embodiments, the phase of a particular ADC clock signal may be controlled by coarse and fine phase adjustments provided to the PLL.

The TDC calibration may be performed at any desired time, for example, at regular or irregular intervals every 100 or more cycles. Thus, the TDC performs measurement of timing error when needed. Moreover, the TDC of the chip need not provide calibration at the same time. Instead, the TDC can operate independently if desired. In some embodiments, the calibration is offline when the channel is not being used to process data, for example.

Thus, the TDC is used to measure the phase of the ADC clock signal of each chip relative to the reference clock signal. In addition, the measurement of each TDC is used to adjust the phase of the ADC clock signal to a desired value. By providing phase adjustment in this manner, the chip can operate with matched clock delays to achieve phase alignment. For example, the TDC selects an amount of phase modification or adjustment based on the measured delay to reduce or eliminate phase differences between the ADC clock signals.

In some embodiments, the TDC performs a measurement after resetting the state of the PLL to a known state, e.g., after a reset of the output divider. For example, the TDC may measure a delay between a clock edge of the reference clock signal and a corresponding clock edge output from the divider after reset.

Although various embodiments herein are described in the context of radar systems, the teachings herein are applicable to a variety of electronic systems, including multiple semiconductor chips operating based on the timing of a common reference clock signal. For example, the synchronization scheme herein may be used in a multichip system where each chip includes at least one data converter that operates in a synchronized timing relationship with respect to a common reference clock signal.

The multi-chip synchronization scheme described herein may be used for a wide range of applications including, but not limited to, radar, cellular, microwave, Very Small Aperture Terminal (VSAT), test equipment, and/or sensor applications. Furthermore, synchronization may be provided for electronic systems operating over a wide frequency range, including not only electronic systems associated with decimetric waves (about 300MHz to 3GHz) and centimeter waves (about 3GHz to 30GHz), but also electronic systems associated with higher frequencies, such as K_aFrequencies in a frequency band (about 27GHz to 40GHz), a V-band (about 40GHz to 75GHz), and/or a W-band (about 75GHz to 110 GHz). Accordingly, the teachings herein are applicable to a variety of electronic systems, including RF and microwave communication systems.

Fig. 1A is a schematic diagram of one embodiment of a Printed Circuit Board (PCB)1 including a plurality of ICs. As shown in FIG. 1A, PCB1 includes a first semiconductor chip or Integrated Circuit (IC)2a, a second IC 2b, a third IC 2c, and a fourth IC 2d, each of which receives a reference clock signal (CLK)_REF). Although an example with four ICs is depicted, PCB1 may include more or less CLK-based_REFThe timing of the operation of IC.

PCB1 of fig. 1A illustrates one example of an electronic system that includes multiple ICs operating using a common timing reference. While PCB1 illustrates one example of an electronic system that may benefit from the chip synchronization scheme herein, the teachings herein are applicable to electronic systems implemented in a variety of ways.

Although in this embodiment ICs 1a-2d are included on PCB1, other configurations are possible, such as an embodiment in which two or more ICs are attached to a module or package substrate.

As shown in FIG. 1A, ICs 2a-2d each receive CLK_REF，CLK_REFFor controlling oneOr the timing of multiple data processing operations. In one example, each IC includes at least one ADC for generating a digital representation of an analog signal, and CLK_REFFor controlling the timing of the data conversion operation of the ADC. In another example, each IC includes at least one digital-to-analog converter (DAC), and CLK_REFFor controlling the timing of the data conversion operation of the DAC.

In the illustrated embodiment, ICs 2a-2d are also connected to a digital interface 3, which digital interface 3 may be, for example, a general purpose input/output (GPIO) bus, an inter-integrated circuit (I)²C) A bus, a Serial Peripheral Interface (SPI) bus, or other suitable interface. The digital interface 3 may be used for various purposes including, but not limited to, programming the IC with digital data to control operation and/or provide calibration. In some embodiments, digital interface 3 is used to provide data indicating whether a particular IC will function as a master or slave device that achieves synchronization in accordance with the teachings herein.

As shown in fig. 1A, CLK_REFIs assigned to each IC 2a-2 d. In some embodiments, CLK_REFAre provided to the ICs 2a-2d through a clock distribution network with substantially matched delays, such as a balanced clock tree. For example, CLK_REFMay be routed along substantially symmetrical conductors of substantially the same length so that CLK may be routed_REFSubstantially simultaneously to each chip.

Fig. 1B is a schematic diagram of a multichip system 20 with data transition synchronization, according to one embodiment. The multichip system 20 includes a master IC 21a, a first slave IC 21b, and a second slave IC 21c, which are connected through the digital interface 3. Although an example with three chips is shown, the teachings herein are applicable to electronic systems that include more or fewer chips.

As shown in fig. 1B, the main IC 21a includes a data converter 22a, a PLL 23a, a converter synchronization circuit 25a, and a PLL synchronization circuit 26 a. PLL 23a uses CLK_REFA resultant clock signal is generated for controlling the timing of the data conversion operation of the data converter 22 a. The synthesized clock signal is also used by converter synchronization circuit 25a to generate a data converter synchronization signal (data _ converter _ SYNC). Thus, the data _ converter _ SYNC is newly generatedTimed to operate in the time domain of the synthesized clock signal of the master IC 21 a. In addition, the PLL synchronization circuit 26a is based on CLK_REFGenerates a PLL phase alignment signal (alignment). Thus, the data _ translator _ SYNC and alignment have timing associated with different clock domains.

The first slave IC 21b includes a data converter 22b, a PLL 23b, a converter synchronization circuit 25b, and a PLL synchronization circuit 26 b. PLL 23b uses CLK_REFA resultant clock signal is generated for controlling the timing of the data conversion operation of the data converter 22 b. Converter synchronization circuit 25b processes data _ converter _ SYNC to synchronize the sampling of data converter 22b with the sampling of data converter 22 a. In addition, the PLL synchronization circuit 26b handles alignment to reset the PLL 23b, thereby reducing or eliminating a phase difference between the synthesized clock signals used to clock the data converter 22a and the data converter 22 b.

Similarly, the second slave IC 21c includes a data converter 22c, a PLL 23c, a converter synchronization circuit 25c, and a PLL synchronization circuit 26 c. Converter synchronization circuit 25c processes data _ converter _ SYNC to synchronize the sampling of data converter 22c with the sampling of data converter 22 a. In addition, the PLL synchronization circuit 26c handles alignment to reset the PLL 23c, thereby reducing or eliminating a phase difference between the synthesized clock signals used to time the data converter 22a and the data converter 22 c. The data converters 22a-22c may include ADCs and/or DACs.

In some embodiments, ICs 21a-21c are of the same type or design (e.g., the same part number), and designation of a particular IC as a master or slave is based on data programmed through digital interface 3.

Fig. 2A is a schematic diagram of a multichip radar system 30 with synchronization, according to one embodiment. The multi-chip radar system 30 includes a master IC 21 and a slave IC 22, which are based on CLK_REFThe timing of (2) processes the data. The main IC 21 includes a frequency ramp generation circuit 23 and an ADC circuit 24. Likewise, the slave IC 22 includes a frequency ramp generation circuit 25 and an ADC circuit 26. Although an example with one slave IC is shown, additional slave ICs may be included.

In the illustrated embodiment, master IC 21 receives a ramp trigger signal (ramp _ flip-flop) for initiating frequency ramp generation of master IC 21 and slave IC 22. The main IC 21 controls the frequency ramp generating circuit 23 in response to activation of the ramp _ flip-flop, thereby controlling transmission of the radar wave.

As shown in fig. 2A, the master IC 21 generates a ramp synchronization signal (ramp _ SYNC), which is provided to the slave IC 22. The ramp _ SYNC is processed by the slave IC 22 to synchronize the transmission sequence between the master IC 21 and the slave IC 22. Accordingly, the slave IC 22 controls the frequency ramp generation circuit 25 in response to the activation of the ramp _ SYNC such that the frequency ramps of the master IC 21 and the slave IC 22 occur substantially simultaneously. Additionally or alternatively, ramp _ SYNC is used to provide phase alignment of the ADC clock signal, which controls the timing of ADC circuit 24 and ADC circuit 26 (e.g., by resetting the PLL used to generate the ADC clock signal), as will be discussed in further detail below.

Thus, in the illustrated embodiment, the master IC 21 processes the ramp _ flip-flop to generate ramp _ SYNC, which is used to synchronize ramp transmissions across two or more ICs and/or provide phase alignment.

As shown in fig. 2A, the master IC 21 also generates an ADC synchronization signal (ADC _ SYNC) for synchronizing the sampling timing of the ADC circuit 24 of the master IC 21 with the sampling of the ADC circuit 26 of the slave IC 22. The ADCs of the master and slave ICs 21, 22 are used to generate digital representations of the RF signals received in response to the transmitted radar waves.

In some embodiments, master IC 21 uses CLK_REFTo synthesize an ADC clock signal to control the timing of the ADC circuit 24. In addition, the main IC 21 generates ADC _ SYNC in the time domain of the ADC clock signal and at CLK_REFGenerates a ramp _ SYNC in the time domain. Thus, ADC _ SYNC and ramp _ SYNC have timings associated with different clock domains. For example, the transition of ADC _ SYNC may occur in response to a clock edge of the ADC clock signal of main IC 21, while the transition of ramp _ SYNC may occur in response to CLK_REFClock edges of.

Thus, main IC 21 generates ramp _ SYNC and ADC _ SYNC to synchronize ramp transmission and analog-to-digital conversion operations across multiple chips. By implementing the multichip radar system 30 in this manner, a high degree of sampling consistency across ADCs may be achieved, thereby improving the detection of objectsThe accuracy of the angular position of (a). In one application, when CLK_REFThe multi-chip radar system 30 may provide synchronization when operating at frequencies up to about 100MHz with a clock uncertainty of less than about 1 ns.

Fig. 2B is a schematic diagram of a multi-chip radar system 40 with a delay verification circuit, according to one embodiment. The multichip radar system 40 includes a master IC31 and a slave IC 32, which are configured similarly to the multichip radar system 30 of fig. 2A. For clarity, certain circuits of the IC, such as the ADC circuit and the frequency ramp generation circuit, are not shown in this figure.

It has been depicted that master IC31 and slave IC 32 have circuitry for verifying the delay between master IC31 and slave IC 32 for ramp _ SYNC and ADC _ SYNC. For example, the main IC31 includes a synchronization signal generation circuit 33, a multiplexer 34, and a comparison circuit 35. In addition, the slave IC 32 includes a multiplexer 36.

The synchronization signal generation circuit 33 generates ramp _ SYNC and ADC _ SYNC as described above with reference to fig. 2A. In addition, the multiplexer 34 is used to select either the ramp _ SYNC or the ADC _ SYNC to be provided to the comparison circuit 35, and the comparison circuit 35 may be, for example, an exclusive or (XOR) gate and a counter. The slave IC 32 further comprises a multiplexer 36 for selecting either the ramp _ SYNC or the ADC _ SYNC to provide a MONITOR signal (MONITOR) in a feedback loop to the comparison circuit 35 of the master IC 31.

In some embodiments, the master IC31 activates ramp _ SYNC and then waits for a delay (e.g., a programmable number of cycles) before initiating a frequency ramp. The delay may be selected based on the propagation delay of the ramp _ SYNC from the master IC31 to the slave IC 32. In some embodiments, the delay is controllable (e.g., user programmable via a digital interface) to provide a delay appropriate for a particular implementation or deployment scenario. Likewise, the main IC31 activates ADC _ SYNC and then waits for a delay (e.g., a programmable number of cycles) before initiating ADC sampling.

The delay verification circuit depicted in fig. 2B may be used to verify the delay between master IC31 and slave ICIC 32 for ramp _ SYNC and/or ADC _ SYNC, thereby determining that the ICs are operating simultaneously. For example, the feedback loop shown may be used to cause the master IC31 to detect the propagation delay by driving ramp _ SYNC and ADC _ SYNC from IC 32.

In some embodiments herein, a multichip system is implemented to include not only a circuit for implementing chip synchronization, but also a delay verification circuit for detecting whether a master IC and one or more slave ICs are synchronized. Although one example of a delay verification circuit is shown in fig. 2B, delay verification may be implemented in various ways.

Fig. 3A is a schematic diagram of a multichip radar system 70 with synchronization according to another embodiment. The multi-chip radar system 70 includes a master IC41 and a slave IC42, which are based on CLK_REFThe timing of (2) processes the data.

The main IC41 includes a main timing control circuit 43, an ADC circuit 44, a filter circuit 45, a data port 46, an ADC PLL47, a clock divider 48, a ramp _ SYNC generation circuit 49, an ADC _ SYNC generation circuit 50, and a frequency ramp generator 61. Slave IC42 includes ramp _ SYNC processing circuit 51, ADC _ SYNC processing circuit 52, slave timing control circuit 53, ADC circuit 54, filter circuit 55, data port 56, ADC PLL 57, clock divider 58, and frequency ramp generator 62.

In some embodiments, the master IC41 and the slave IC42 correspond to the same type or design of semiconductor chip. In addition, the ICs may be configured in either master or slave mode, thereby enhancing flexibility and allowing two chips of the same type to be serviced in a master-slave timing relationship. In some embodiments, the IC is configured in either a master mode or a slave mode based on data received over an interface (e.g., digital interface 3 of fig. 1A-1B).

As shown in fig. 3A, CLK_REFIs provided to the master IC41 and the slave IC 42. In some embodiments, CLK_REFProvided by a matched clock distribution network to help match the CLK_REFTime to master IC41 and slave IC 42.

However, even when matched clock distribution networks are used, CLK in master IC41 and slave IC42_REFMay also have a phase difference that may vary with process and operating conditions such as temperature and/or supply voltage. Thus, the master IC41 is shown with a master reference clock signal (CLK)_REFM) Operation ofAnd slave IC42 is shown with a slave reference clock signal (CLK)_REFS) And (5) operating.

As shown in FIG. 3A, the master timing control circuit 43 receives CLK_REFMAnd a ramp _ flip-flop. In addition, the main timing control circuit 43 generates various control signals for controlling the operation of the main IC 41. For example, the main timing control circuit 43 generates a main ramp start signal (ramp _ start _ M) for the frequency ramp generator 61 and a main sampling enable signal (sample _ EN _ M) for the filter circuit 45. The main timing control circuit 43 also supplies data for controlling the state of ramp _ SYNC to the ramp _ SYNC generation circuit 49, and supplies data for controlling the state of ADC _ SYNC to the ADC _ SYNC generation circuit 50. In addition, the main timing control circuit 43 also supplies a main PLL enable signal (enable _ M) and a main PLL reset signal (reset _ M) to the ADC PLL47, and supplies a main AFE reset signal (AFE _ reset _ M) to the frequency divider 48.

ADC PLL47 based on CLK_REFMGenerates the main ADC clock signal (ADC _ CLK _ M). In some embodiments, the ADC PLL47 generates ADC _ CLK _ M based on a frequency synthesis operation. For example, the ADC PLL47 may be implemented as an integer or fractional NPLL that controls the frequency of ADC _ CLK _ M to have a relative to CLK_REFMThe desired frequency relationship. In the illustrated embodiment, ADC _ CLK _ M is divided in frequency by clock divider 48 to produce a main Analog Front End (AFE) clock signal (AFE _ CLK _ M) that is used to control the timing of filter circuit 45, data port 46, and ADC _ SYNC generation circuit 50.

The main IC41 includes an ADC circuit 44, a filter circuit 45, and a data port 46, which are connected in cascade to process an analog Signal (SIG). Although not depicted in fig. 3A, SIG may be received on a pin of the master IC 41. Although one example of a signal processing circuit is shown, the teachings herein may be used to synchronize various types of signal processing circuits.

The ADC circuit 44 includes one or more ADCs that operate to digitize SIG based on the timing of ADC CLK M. In some embodiments, the SIG corresponds to a set of analog signals, such as analog signals generated by processing RF signals received on several antenna elements of an antenna array in response to transmitted radar waves. The ADC circuit 44 generates a digital output signal (OUT _ M) that is processed by one or more filters of the filter circuit 45. As shown in fig. 3A, the timing of the data conversion operation of the ADC circuit 44 is controlled by the ADC _ CLK _ M.

Filter circuit 45 also receives sample _ EN _ M, which indicates whether SIG is being sampled. Implementing the master timing control circuit 43 to generate the sample _ EN _ M may help coordinate the timing of the digital samples. As shown in fig. 3A, filter circuit 45 operates based on the timing of AFE _ CLK _ M, which in some embodiments has a lower frequency than ADC _ CLK _ M, e.g., is decimated by a factor of ten or more. Although an example is depicted in which the filter frequency is less than the ADC frequency, other implementations are possible. For example, in another example, the filter circuit 45 operates at about the same frequency as the ADC circuit 44.

The data port 46 receives filtered data from the filter circuit 45 and operates to send the filtered data to downstream circuitry (e.g., a downstream chip) for further processing. In some embodiments, the data port 46 includes high speed interface circuitry, such as Low Voltage Differential Signaling (LVDS) drivers. As shown in fig. 3A, the data port 46 operates based on the timing of AFE _ CLK _ M.

With continued reference to fig. 3A, slave IC42 includes a slave timing control circuit 53 that generates various control signals for controlling the operation of slave IC 42. For example, the slave timing control circuit 53 generates a slave ramp start signal (ramp _ start _ S) of the frequency ramp generator 62 to control the sequence of transmitters, and a slave sampling enable signal (sample _ EN _ S) of the filter circuit 55. The slave timing control circuit 53 also supplies a slave PLL enable signal (enable _ S) and a slave PLL reset signal (reset _ S) to the ADC PLL 57, and supplies a slave AFE reset signal (AFE _ reset _ S) to the frequency divider 58.

ADC PLL 57 based on CLK_REFSGenerates the slave ADC clock signal (ADC _ CLK _ S). As shown in fig. 3A, ADC _ CLK _ S controls the timing of the ADC circuit 54 generating the digital output signal (OUT _ S) by digitizing SIG, which may be the same or different analog signal processed by the host IC 41. Clock divider 58 divides down ADC _ CLK _ S to generate a slave AFE clock signal (AFE _ CLK _ S), which is provided to filter circuit 55, data port 56, and ADC _ SYNC processing circuit 52.

As shown in fig. 3A, master IC41 provides ramp _ SYNC and ADC _ SYNC to slave IC 42. In addition, the ramp _ SYNC generation circuit 49 re-clocks data from the main timing control circuit 43 to CLK_REFMTo generate ramp _ SYNC. In addition, the ADC _ SYNC generation circuit 50 generates ADC _ SYNC, which corresponds to a decimated version of ADC _ CLK _ M, by retiming data from the main timing control circuit 43 to the AFE _ CLK _ M. Thus, in this embodiment, ADC _ SYNC and AFE _ CLK _ M are synchronized.

With continued reference to FIG. 3A, ramp _ SYNC processing circuit 51 is based on CLK_REFSThe ramp _ SYNC is retimed and the retimed ramp SYNC signal is provided to the slave timing control circuit 53 for timing control of frequency ramp generation and/or for providing phase alignment. In addition, the ADC _ SYNC processing circuit 52 retimes the ADC _ SYNC based on the AFE _ CLK _ S and supplies the retimed ADC synchronization signal to the slave timing control circuit 53 for timing control of ADC sampling.

In the illustrated embodiment, the multi-chip radar system 70 includes a master IC41 and a slave IC42, each master IC including at least one ADC controlled by a common timing reference. Although an example with two chips is shown, the teachings herein are also applicable to electronic systems with three or more chips. For example, a master IC may provide synchronization signals to two or more slave ICs.

When processing received data, it is desirable to operate the ADC circuit 44 and the ADC circuit 54 in a synchronized timing relationship. For example, in some embodiments, the phase error is proportional to the phase difference between the frequency of the signal being sampled and the clock signal used to sample the signal. By using ramp _ SYNC and ADC _ SYNC, the IC operates in synchronous operation to enhance the performance of the multichip radar system 70, e.g., with greater accuracy in determining the angular position of a detected object.

Fig. 3B is an example of a timing diagram for ADC sampling for the multichip radar system 70 of fig. 3A. As shown in FIG. 3B, the voltage and time waveforms of SIG, ADC _ CLK _ M, ADC _ CLK _ S, OUT _ M, and OUT _ S are shown. In this example, SIG is sinusoidal. However, the multichip radar system 70 of FIG. 3A may sample a wide variety of signal waveforms and/or a set of analog signals. For example, in some embodiments, the ADC circuitry 44 of the master IC41 and the ADC circuitry 54 of the slave IC42 sample different versions of SIG, e.g., analog signals produced by different antenna elements of an antenna array.

In the example shown, ADC _ CLK _ M and ADC _ CLK _ S are at a phase difference of t_{Phase position}This is undesirable for operation.

As shown in fig. 3B, the phase difference t_{Phase position}Resulting in sampling errors. In certain embodiments, the sampling error is related to SIG and t_{Phase position}Is proportional to the frequency of (c). The synchronization scheme here is used to reduce or eliminate the t-phase.

Fig. 3C is an example of a timing diagram of the ramp synchronization signal. The timing diagram includes CLK_REFAnd the voltage versus time curve of ramp _ SYNC.

As described above, the main IC may be implemented to include a pin or pad that outputs ramp _ SYNC. In some embodiments, the pins are used not only to synchronize transmission sequencing across multiple chips, but also to indicate phase alignment of the slave devices. Using pins for multiple functions may reduce the pin count of the IC. In another embodiment, a master IC includes: a first pin for generating a ramp synchronization signal for coordinating frequency ramp generation across a plurality of chips; and a second pin for generating a phase alignment signal for coordinating phase alignment of the plurality of chips.

Phase alignment may be provided in various ways. In some embodiments, phase alignment is provided by resetting the ADC PLL47 and the adpll 57 (e.g., by resetting the output divider). For example, the slave timing control circuit 53 may reset the ADC PLL 57 in response to the ramp _ SYNC indicating phase alignment. Additional details of phase alignment will be discussed further below.

Thus, in certain embodiments, ramp _ SYNC is used not only for synchronization of ramp generation across two or more devices, but also for phase alignment.

In some embodiments, the bit pattern of ramp _ SYNC is used to indicate whether ramp _ SYNC is used to synchronize transmitter sequencing or to coordinate phase alignment. For example, in the example of fig. 3C, bit sequence "11" represents issuing a frequency ramp generation instruction to the slave IC, and bit sequence "101" represents issuing an instruction for phase alignment to the slave IC. Thus, the shape of ramp _ SYNC is different for command frequency ramp generation relative to command phase alignment.

Thus, a common pin of the main IC may be used for synchronous ramp generation and provide phase alignment of the ADC clock signal across the chip.

Although a specific example of a bit sequence is shown, any suitable bit sequence may be used to initiate ramp generation and/or phase alignment. Thus, other implementations are possible.

Referring to fig. 3A and 3C, in one embodiment, the master IC41 first uses ramp _ SYNC to indicate phase alignment. Thereafter, the main IC41 starts frequency ramp generation using the ramp _ SYNC. Both the master IC41 and the slave IC42 operate with a low phase difference and a synchronous frequency ramping operation, which results in transmitting a radar wave. Thereafter, the main IC41 uses ADC _ SYNC to synchronize ADC sampling, thereby coordinating digital sampling of signals received in response to radar waves.

Fig. 4 is an example of a timing diagram for ramp generation for the multichip radar system 70 of fig. 3A. The timing diagram includes a voltage-time plot of ramp _ flip-flops, a ramp of the frequency ramp generator 61 of the master IC (CLKREFM, ramp _ SYNC, ramp _ start _ M), and a ramp of the frequency ramp generator 62 of the slave IC (CLKREFS and ramp _ start _ S). In this example, the activated signal has a logic high value and the deactivated signal has a logic low value. However, as the skilled person will appreciate, any signal may be implemented using an inverted polarity such that activation is indicated by a logic low value and deactivation is indicated by a logic high value.

In addition, in response to the ramp _ flip-flop being activated, the main IC41 activates ramp _ SYNC at a second time ② and ramp _ Start _ M at a third time 3 ○ in this example, the main IC41 activates ramp _ SYNC one CLK after activating ramp _ flip-flop_REFMPeriod, and ramp _ start _ M two CLKs are activated after ramp _ SYNC is activated_REFMHowever, other implementations are possible, such as configurations using programmable delays (e.g., calibration delays and/or user-controlled delays).

By using ramp _ SYNC, the timing of ramp generation in master IC41 and slave IC42 is synchronized.

By using ramp _ SYNC, the timing of ramp generation in master IC41 and slave IC42 is synchronized.

Fig. 5 is an example of a timing diagram for ADC synchronization of the multichip radar system 70 of fig. 3A. The timing diagram includes a voltage-time plot of the ramp _ flip-flop, the ramp (CLK) of the frequency ramp generator 61 of the main IC_REFMRamp _ SYNC, ADC _ CLK _ M, AFE _ CLK _ M, ADC _ SYNC, sample _ EN _ M), ramp (CLK) from the frequency ramp generator 62 of the IC_REFSADC _ CLK _ S, AFE _ CLK _ S, and sample _ EN _ S). The timing diagram has also been annotated to indicate whether the signal is internal to the chip (INT) or on the chip PIN (PIN).

As shown in FIG. 5, at a first time ①, a ramp _ flip-flop is activated at an input pin of the main IC41, thereby enabling ramp generation. additionally, in response to activation of the ramp _ flip-flop, the main IC41 activates ramp _ SYNC at a second time ②. thereafter, the main IC41 activates ADC _ SYNC at a third time 3 ○ and activates sample _ EN _ M at a fourth time ④. in this example, the main IC41 activates ramp _ SYNC _ CLK one CLK after activation of the ramp _ flip-flop_REFMHowever, other implementations are possible, such as configurations using programmable delays (e.g., calibration delays and/or user-controlled delays). slave IC42 processes ADC _ SYNC to activate sample _ EN _ S at fourth time ④.

By using ADC _ SYNC, the timing of the ADC sampling in the master IC41 and the slave IC42 is synchronized.

Fig. 6A is a schematic diagram of a multichip radar system 150 with phase alignment according to one embodiment. Multi-chip radar system 150 includes receiving CLK_REF A master IC 101 and a slave IC 102.

In the illustrated embodiment, the main IC 101 includes a main timing control circuit 110, an ADC PLL 111, a frequency divider 114, and a ramp _ SYNC generation circuit 116. In addition, the ADC PLL 111 comprises a controllable oscillator 121, an enable circuit 122 and an output frequency divider 123, which may be programmable. In addition, the main timing control circuit 110 includes a TDC 125. Some circuits of the main IC 101 are omitted for clarity.

ADC PLL 111 based on CLK_REFMGenerates ADC _ CLK _ M. In addition, the divider 114 divides the ADC _ CLK _ M to generate the AFE _ CLK _ M. In some embodiments, divider 114 is programmable. The ramp _ SYNC generation circuit 116 generates a ramp _ SYNC based on the data and clock signal timing from the main timing control circuit 110. The master timing control circuit 110 also receives a phase alignment signal (phase _ aligned) and generates a master PLL enable signal (enable _ M), a master PLL reset signal (reset _ M), and an AFE reset signal (AFE _ reset _ M).

As shown in fig. 6A, the slave IC 102 includes a slave timing control circuit 130, an ADC PLL 131, a frequency divider 134, and a ramp _ SYNC processing circuit 136. In addition, the ADC PLL 131 includes a controllable oscillator 141, an enable circuit 142, and an output frequency divider 143. Further, the slave timing control circuit 130 includes a TDC 145. Some circuits of the slave IC 102 are omitted for clarity.

ADC PLL 131 based on CLK_REFSGenerates ADC _ CLK _ S. In addition, the divider 134 divides the ADC _ CLK _ S to generate the AFE _ CLK _ S. In some embodiments, frequency divider 134 and/or output frequency divider 143 are programmable. The ramp _ SYNC processing circuit 136 retimes the ramp _ SYNC based on the clock signal timing and provides a retimed ramp synchronization signal to the slave timing control circuit 130. The slave timing control circuit 130 generates a slave PLL enable signal (enable _ S), a slave PLL reset signal (reset _ S), and a slave AFE reset signal (AFE _ reset _ S).

The multi-chip radar system 150 of fig. 6A illustrates an implementation in which ramp _ SYNC is used to provide phase alignment to coordinate synchronization of AFE _ CLK _ M and AFE _ CLK _ S. For example, as described above with reference to fig. 3C, ramp _ SYNC may serve a variety of functions, including providing phase alignment.

Without phase alignment, the ADC _ CLK _ M and ADC _ CLK _ S may have unknown phase differences, e.g., caused by non-deterministic startup values of the frequency dividers, charge pumps, and/or accumulators. Also, without phase alignment, the AFE _ CLK _ M and AFE _ CLK _ S may have unknown phase differences. By providing phase alignment using reset, a controlled phase relationship (e.g., a known and constant phase offset) can be achieved. In particular, ADC _ CLK _ M may have a relative CLK to CLK when ADC PLL 111 is reset synchronously from the reference clock domain_REFControlled phase alignment. Likewise, when the ADC PLL 131 is synchronously reset from the reference clock domain using ramp _ SYNC, ADC _ CLK _ S may have a relative CLK to CLK_REFControlled phase alignment. In addition, phase alignment may help reduce or eliminate the phase difference between AFE _ CLK _ M and AFE _ CLK _ S.

Fig. 6B is an example of a timing diagram for phase alignment of the multichip radar system of fig. 6A. The timing diagram includes CLK_REFMPhase _ alignment, ramp _ SYNC, AFE _ reset _ M, ADC _ CLK _ M, AFE _ CLK _ M, CLK_REFSAFE _ reset _ S, ADC _ CLK _ S and AFE _ CLK _ S.

Before reset, ADC _ CLK _ M and ADC _ CLK _ S are depicted as having an initial phase difference (Δ Θ) as shown in fig. 6B, at a first time ①, phase _ alignment is activated in the master IC 101 to initiate phase alignment, in some embodiments, phase _ alignment is activated by register writing of the master IC 101, e.g., using a digital interface, in response to activation of phase _ alignment, the master IC 101 activates a phase alignment command at a second time ② via a ramp SYNC _ and disables ADC _ CLK _ M at a third time ③, the slave IC 102 processes the ramp _ SYNC to deactivate ADC _ CLK _ S at a third time 3 ○, the ADC _ CLK _ M and ADC _ CLK _ S may be disabled by various means, e.g., using enable _ M and enable _ S, respectively, further, at a fourth time ④, the master IC 101 activates AFE _ reset _ M to reset the frequency divider 114, likewise, the slave IC 102 processes the ramp _ SYNC to activate reset at time ④, thereby resetting the ADC _ CLK _ M, thereby resetting the frequency divider 101, and the slave IC 102 generates the frequency divider reset at a fifth time 39143, and enables the ADC IC 111, and generates the frequency divider at a fifth time 39111.

With continued reference to fig. 6B, after phase alignment, there may still be a residual phase difference between ADC _ CLK _ M and ADC _ CLK _ S

Clock delay errors that may be caused by mismatches include phase differences caused by manufacturing variations and/or operating conditions (e.g., temperature).

As will be discussed below, the TDC of the master and slave ICs (e.g., TDC 125 and TDC 145 of FIG. 6A) may be used to reduce or eliminate

In particular, each TDC may measure an internal time delay between a reference clock signal and the ADC clock signal of the chip and provide a phase adjustment to set the internal time delay to a desired delay value. Providing pairs by controlling the internal clock delay of each chip to substantially the same delay value

Compensation of (2).

Figure 7A is a schematic diagram of an IC150 including TDC calibration for clock delay, according to one embodiment. IC150 includes input/output (I/O) interface pad 141, input clock path 142, PLL circuit 143, output clock path 144, controllable phase shifter 145, and TDC 146. For clarity, the circuitry of the IC150 is described in relation to TDC calibration for clock delay, but other circuitry of the IC150 is omitted. The TDC calibration circuit of figure 7A may be incorporated into any of the chips disclosed herein.

The IC150 receives CLK at pad 141_REF. In addition, CLK_REFIs provided to a first input of the TDC 146. CLK_REFProcessed by input clock path 141 to generate a timing reference for PLL circuit 143. In addition, the synthesized clock signal from the PLL circuit 143 is processed by an output clock path 144 and phase shifted by a controllable phase shifter 145 to generate an ADC clock signal (ADC _ CLK). The ADC _ CLK is provided to a second input of the TDC 146.

As shown in fig. 7A, CLK_REFAnd ADC _ CLK may include various components including, for example, the delay (τ) of pad 141_IO) Delay (τ) of input clock path 142_{Route 1}) Delay PLL circuit 143(τ)_PLL) Delay (τ) of output clock path 144_{Route 2}) And the delay of controllable phase shifter 145.

TDC 146 is used to generate a clock signal corresponding to CLK_REFA first digital timestamp of the digital representation of the transition time (e.g., rising edge or falling edge) and a second digital timestamp of the digital representation (e.g., rising edge or falling edge) corresponding to the transition time of ADC _ CLK. In addition, TDC 146 compares the digital time stamps to generate CLK_REFAnd a digital representation of the time delay between the transition of ADC CLK and the corresponding transition of ADC CLK. As shown in fig. 7A, the digital time delay measured by TDC 146 is used to control the delay of the controllable phase shifter 145.

In some embodiments, TDC 146 controls the delay of the controllable phase shifter 145 such that CLK_REFAnd the internal time delay between ADC CLK is substantially equal to the desired time delay. In one example, the TDC 146 controls the delay of the controllable phase shifter 145 to a known reference time delay, e.g., a fraction (e.g., half) of the period of the ADC CLK.

In a multi-chip electronic system, each chip may include a TDC arranged in a configuration similar to that of FIG. 7A. After each chip is calibrated to achieve a common clock path delay, CLK_REFAnd ADC CLK is substantially constant on the chip. Thus, phase differences between ADC clock signals of different chips (e.g., of fig. 6B) may be reduced or eliminated

)。

Figure 7B is a schematic diagram of an IC230 including TDC calibration for clock delay according to another embodiment. IC230 includes pads 201, input clock buffer 202, reference clock multiplier 203 (in this example, multiplied by or 2 times), Signal Jitter (SJ) suppression circuit 204, All Digital Phase Locked Loop (ADPLL)205, output clock buffer 206, output divider 207, divider reset generator 208, reference clock level shifter 211, reference clock multiplexer 213, ADC clock multiplexer 214, TDC215, first flip-flop 217, and second flip-flop 218. The ADPLL205 includes a controllable oscillator 221 and a phase detector 222.

The TDC calibration circuit of figure 7B may be incorporated into any of the chips disclosed herein.

As shown in fig. 7B, CLK_REFAnd ADC _ CLK may include various components including, for example, the delay (τ) of pad 201_IO) Delay (τ) of input clock buffer 202_BUF) Delay (τ) of reference clock multiplier 203_X2) And a delay (tau) of the signal jitter suppression circuit 204_SJ) Delay (τ) of ADPLL205_PLL) The delay of the output clock buffer 206 and the delay of the divider 207.

As shown in fig. 7B, the reference clock level shifter 211 includes a first capacitor 212a and a second capacitor 212B connected in series with the pad 201 and ground. Reference clock level shifter 211 vs CLK_REFLevel shifting is performed. The use of capacitive level shifters provides level shifting with relatively low delay, thereby reducing chip-to-chip variations.

TDC215 is used to measure CLK_REFAnd a delay difference between the level shifted version of ADC CLK. The measured delays are used to generate a FINE phase adjustment signal (FINE) for the ADPLL205 and a COARSE phase adjustment signal (COARSE) for the reset generator 208. Multiplexers 213 and 214 and flip-flops 217 and 218 are also included to use the TDC for other functions. For example, the TDC215 may also measure a time delay associated with the input reference signal (IN) and/or the split version of ADC _ CLK based on the state of the select Signal (SEL). In other implementations, multiplexing is omittedMultiplexer 213-214 and flip-flop 217-218.

In some embodiments, COARSE provides phase adjustment in a full or half cycle of the oscillation period of the controllable oscillator 221, while FINE provides phase adjustment in steps that are less than half of the full or oscillation period. However, other implementations are possible.

In the illustrated embodiment, COARSE is provided to divider reset generator 208. The divider reset generator 208 also receives a reset signal reset from the timing control circuitry of the chip (see, e.g., fig. 6A). COARSE controls the delay of the divider reset generator 208 to reset the output divider 207 in response to activation of the reset. Although one example of coarse tuning is shown, adjustment of the clock path delay may be provided in various ways.

With continued reference to fig. 7B, FINE is provided to ADPLL 205. The ADPLL205 also receives an enable signal (enable) from the timing control circuit of the chip (see, e.g., fig. 6A). The FINE may provide phase adjustment in various ways, such as controlling the output phase of the controllable oscillator 221 and/or the phase offset of the phase detector 222.

Although FINE is depicted as being provided from TDC215 to ADPLL205, in some embodiments, FINE is set offline based on measurement of TDC 215. For example, the IC230 may include one or more registers that are programmed on the interface by a user based on measurements from the TDC 215. Thus, in some embodiments, FINE represents TDC measurement data output by a register of IC 230.

Fig. 7C is one example of a timing diagram depicting the resetting of the ADC clock signal. In this example, the voltage and time waveforms of CLKREF, ADC _ CLK _ M, and ADC _ CLK _ S are shown. Both ADC _ CLK _ M and ADC _ CLK _ S have been calibrated using TDC to control the clock path delay of each chip to the desired delay. As shown in fig. 7C, ADC _ CLK _ M and ADC _ CLK _ S have an initial phase difference at power-up. The phase difference may come from any initial phase of each PLL, such as a non-deterministic start-up value of a frequency divider, charge pump, and/or accumulator. After providing phase alignment using ramp _ SYNC, the PLL is reset and ADC _ CLK _ M and ADC _ CLK _ S are substantially aligned.

Fig. 8 is a schematic diagram of an IC 310 with phase alignment according to another embodiment. IC 310 includes timing control circuit 300, ADC PLL 301, TDC 303, and frequency divider 305. In this example, the ADC PLL 301 includes an ADPLL311, an output frequency divider 312, a frequency divider reset generator 313, and a clock gate circuit 314. For clarity, only certain circuits of the IC are depicted. The circuit depicted in fig. 8 may be incorporated into any of the master or slave ICs disclosed herein.

As shown in FIG. 8, ADC PLL 301 is based on CLK_REFThe ADC clock signal (ADC _ CLK) is synthesized. In addition, divider 305 divides ADC _ CLK to generate AFE _ CLK. TDC 303 for comparing CLK_REFAnd ADC CLK and provides the measured delay through a digital Interface (INTF). The ADC PLL 301 is also coupled to INTF, and may receive clock delay adjustment data through INTF.

In the illustrated implementation, the timing control circuit 300 generates an ADC PLL enable signal (enable), an ADC reset signal (reset), and an AFE reset signal (AFE _ reset). Thus, in this embodiment, timing control circuit 300 also resets the divider that generates AFE _ CLK.

Fig. 9 is an example of a timing diagram for phase alignment of a multi-chip radar system implemented in accordance with fig. 8. The timing diagram corresponds to a case where both the master IC and the slave IC are implemented with the phase alignment circuit shown in fig. 8. The clock diagram including the CLK of the master IC_REF(CLK_REFM) Voltage-time waveform of (d), ramp _ SYNC generated by the master IC, AFE _ reset (AFE _ reset _ M) of the master IC, enable (enable _ M) of the master IC, reset (reset _ M) of the master IC, PLL _ CLK (PLL _ CLK _ M) of the master IC, ADC _ CLK (ADC _ CLK _ M) of the master IC, CLK of the slave IC_REF(CLK_REFS) The slave IC includes an AFE _ reset (AFE _ reset _ S), an enable (enable _ S), a reset (reset _ S), a PLL _ CLK (PLL _ CLK _ S), and an ADC _ CLK (ADC _ CLK _ S).

In response to activation of ramp _ SYNC, the slave IC also resets the divider that generates AFE _ CLK _ S at second time 2 ○ and turns off ADC _ CLK _ S at third time 3 2. in this embodiment, ADC _ CLK _ S and ADC _ CLK _ M are gate controlled for two reference clock cycles.

With continued reference to fig. 9, enable _ M, enable _ S, reset _ M, and reset _ S are activated at a fourth time 4 ○.

Fig. 10 is a schematic diagram of a slave IC 340 with a reset circuit according to one embodiment. The slave IC 340 includes an ADC PLL 319 and a ramp _ SYNC processing circuit 320. The ADC PLL 319 includes a controllable oscillator 321, an output divider 322, a first divider reset generator 323, a second divider reset generator 324, a multiplexer 325, and a retiming flip-flop 326.

The controllable oscillator 321 generates a clock signal (CLK) and an early clock signal (CLK') having an earlier phase than the time of CLK. In this embodiment, ramp _ SYNC processing circuit 320 processes ramp _ SYNC to detect an instruction to perform phase alignment and activates reset _ S in response to detecting the onset of phase alignment.

As shown in fig. 10, the first frequency divider reset generator 323 operates based on the timing of CLK ', and the second frequency divider reset generator 324 operates based on the timing of the inverted version of CLK'. Both divider reset generators 323, 324 also receive COARSE, which may be used to provide phase adjustment to the clock path, as described above with reference to fig. 7B.

The control signal (CTRL) is used to select the output of the first or second frequency divider reset generator 323, 324. CTRL may be generated in a variety of ways, for example using a timing control circuit, such as a microcontroller and/or a state machine. The selection of CTRL may be based on whether the phase adjustment is greater or less than 180 degrees. For example, in some embodiments, the first divider reset generator 323 is used for phase adjustments less than 180 degrees, while the second divider reset generator 324 is used for phase adjustments higher than 180 degrees.

The use of a bi-phase reset generator helps to satisfy timing constraints over a wide range of phase adjustment values, providing enhanced flexibility and/or superior performance.

Applications of

The device adopting the scheme can be realized into various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, components of consumer electronics, electronic test equipment, and the like. Examples of the electronic device may also include circuitry of an optical network or other communication network. Consumer electronics products may include, but are not limited to, automobiles, camcorders, cameras, digital cameras, portable memory chips, washing machines, dryers, washer/dryers, copiers, facsimile machines, scanners, multifunction peripherals, and the like. Further, the electronic device may include unfinished products, including products for industrial, medical, and automotive applications.

The foregoing description and claims may refer to elements or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematic diagrams shown in the figures depict exemplary arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual implementation (assuming that the functionality of the depicted circuits is not adversely affected).

While the present invention has been described in terms of certain embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages described herein, are also within the scope of the present invention. Furthermore, the various embodiments described above can be combined to provide further embodiments. In addition, certain features that are shown in the context of one embodiment can also be incorporated in other embodiments. Accordingly, the scope of the invention is to be defined only by reference to the following claims.