阅读说明：本技术 读、部分写数据方法以及相关装置 (Method for reading and partially writing data and related device ) 是由 罗日新 李渊 袁泉 于 2017-07-14 设计创作，主要内容包括：一种部分写数据方法，包括：缓存控制器(20，30，40，150，160)接收部分写请求(S61)；所述部分写请求携带的数据的大小小于缓存行(211，212，213，311，312，313，411，412，413)可缓存数据的大小；将部分写请求携带的数据写入请求地址在缓存行(211，212，213，311，312，313，411，412，413)中对应的位置，更新缓存行(211，212，213，311，312，313，411，412，413)的写掩码(S65)，以及更新缓存行(211，212，213，311，312，313，411，412，413)的状态(S69，S145)。一种读数据方法，以及相关装置。通过在缓存行(211，212，213，311，312，313，411，412，413)的状态中增加部分写状态，以及通过写掩码来表示该缓存行(211，212，213，311，312，313，411，412，413)中已被写入的数据的位置，使得缓存控制器(20，30，40，150，160)在部分写或读数据过程中，减少内存与高速缓冲存储器(172)的数据交换，提高高速缓冲存储器(172)的数据处理效率。(A method of partially writing data, comprising: the cache controller (20, 30, 40, 150, 160) receiving a partial write request (S61); the size of the data carried by the partial write request is smaller than the size of the cacheable data of the cache line (211, 212, 213, 311, 312, 313, 411, 412, 413); the method includes the steps of writing data carried by the partial write request to a corresponding location in the cache line (211, 212, 213, 311, 312, 313, 411, 412, 413), updating a write mask (S65) of the cache line (211, 212, 213, 311, 312, 313, 411, 412, 413), and updating a state (S69, S145) of the cache line (211, 212, 213, 311, 312, 313, 411, 412, 413). A method of reading data, and an associated apparatus. By adding a partial write state in the state of the cache line (211, 212, 213, 311, 312, 313, 411, 412, 413) and representing the position of the data which is written in the cache line (211, 212, 213, 311, 312, 313, 411, 412, 413) by a write mask, the cache controller (20, 30, 40, 150, 160) reduces data exchange between a memory and the cache memory (172) in the partial write or read process of the data, and improves the data processing efficiency of the cache memory (172).)

A method for partially writing data, comprising:

receiving a partial write request, wherein the size of data carried by the partial write request is smaller than the size of cacheable data of a cache line;

writing data carried by the partial write request into a corresponding position of a request address in the cache line;

updating a write mask of the cache line;

updating the state of the cache line;

wherein the state of the cache line comprises a partial write state; the partial write state is to indicate that a data portion of the cache line is valid; the write mask is used to indicate the location of data in the cache line that has been written.

The method of claim 1, wherein the corresponding location of the address of the data write request carried by the partial write request in the cache line comprises:

when the partial write request is subjected to cache hit, writing data carried by the partial write request into a corresponding position of the request address in a hit cache line; or the like, or, alternatively,

and when the partial write request is not hit, allocating a cache line for the partial write request, and writing the data carried by the partial write request into a corresponding position of the request address in the allocated cache line.

The method of claim 1 or 2,

the updating the write mask of the cache line comprises: and updating the write mask of the cache line according to the request address.

The method of any of claims 1-3, wherein when the updated write mask of the cache line is all 1, the method further comprises: writing the data of the cache line into a memory or a next-level cache memory, and initializing a write mask of the cache line;

the updating the state of the cache line comprises: and updating the state of the cache line into an invalid state.

The method of any of claims 1-3, wherein when the write mask of the cache line after the update is all 1, the method further comprises: initializing a write mask for the cache line;

the updating the state of the cache line comprises: and updating the state of the cache line into a modified state.

A method of reading data, comprising:

receiving a first read request; the first read request is used for requesting to read data corresponding to a first request address in a cache line;

when the first read request is subjected to cache hit and part or all of data corresponding to the first request address in a hit cache line does not exist, merging the data read from the memory corresponding to the first request address or the corresponding next-level cache memory into the hit cache line according to a write mask of the hit cache line, and updating the state and the write mask of the merged cache line;

reading data corresponding to the first request address in the merged cache line;

wherein the state of the cache line comprises a partial write state; the partial write state is to indicate that a data portion of the cache line is valid; the write mask is used to indicate the location of data in the cache line that has been written.

The method of claim 6, wherein the method further comprises:

receiving a second read request; the second read request is used for requesting to read data corresponding to a second request address in a cache line;

when a cache hit occurs for the second read request and the status of the hit cache line is not a partial write status; or, when the second read request has a cache hit, the state of the hit cache line is a partial write state, and the write masks corresponding to the second request address in the hit cache line are all 1, reading data corresponding to the second request address in the hit cache line.

The method of claim 6, wherein the absence of a portion or all of the data corresponding to the first request address in the hit cache line comprises: the state of the hit cache line is a partial write state, and the write masks corresponding to the first request address in the hit cache line are not all 1;

the merging the data read from the memory corresponding to the request address or the corresponding next-level cache memory into the hit cache line includes:

writing data in a memory corresponding to a first position or a next-level cache memory into the first position in the hit cache line; the first location comprises a location in the hit cache line where a writemask is 0;

the data at the first position and the data at the second position in the written cache line form a merged cache line; the second location comprises a location in the cache line of the hit where the writemask is 1.

A cache memory, comprising: a cache controller and a cache line region; the cache line region comprises a plurality of cache lines, and each cache line comprises a data field, an address field, a state field and a write mask field; wherein the content of the first and second substances,

the data field is used for storing data;

the address field is used for indicating address information of data stored in the cache line;

the status field is to indicate a status of the cache line; the state comprises a partial write state; the partial write state is to indicate that a data portion of the cache line is valid;

the writemask field is used to store a writemask, which is used to indicate the location of data that has been written in the cache line;

the cache controller is configured to receive a request and to update a state of a cache line and a write mask in response to the request.

The cache memory of claim 9, wherein the writemask field is n/8 bytes in size, where n is a maximum number of bytes of data that the cache line may store.

The cache memory according to claim 9 or 10, wherein the request comprises a partial write request, the cache controller being specifically configured to perform:

receiving the partial write request; the size of the data carried by the partial write request is smaller than the size of the cacheable data of the cache line;

writing data carried by the partial write request into a corresponding position of a request address in the cache line;

updating a write mask of the cache line;

and updating the state of the cache line.

The cache memory of claim 11, wherein the cache controller to perform the writing of the data carried by the partial write request to the corresponding location of the address of the request in the cache line comprises:

when the partial write request is subjected to cache hit, writing data carried by the partial write request into a corresponding position of the request address in the hit cache line; or the like, or, alternatively,

and when the partial write request is not hit, writing the data carried by the partial write request into the corresponding position of the request address in the allocated cache line for the cache line allocated to the partial write request.

The cache memory of claim 11 or 12, wherein the cache controller to perform the updating the write mask of the cache line comprises: and the cache controller updates the write mask of the cache line according to the request address.

The cache memory of any one of claims 11-13, wherein when the updated write mask is all 1, the cache controller is further to perform: writing the data of the cache line into a memory or a next-level cache memory, and initializing a write mask of the cache line;

the updating, by the cache controller, the state of the cache line comprises: the cache controller updates the state of the cache line to an invalid state.

The cache memory of any one of claims 11-13, wherein when the write mask of the cache line after the update is all 1, the cache controller is further to perform: initializing a write mask for the cache line;

the updating, by the cache controller, the state of the cache line comprises: the cache controller updates the state of the cache line to a modified state.

The cache memory according to claim 9 or 10, wherein the request comprises a first read request, the cache controller being in particular configured to perform:

receiving the first read request; the first read request is used for requesting to read data corresponding to a first request address in the cache line;

when the first read request is subjected to cache hit and part or all of data corresponding to the first request address in a hit cache line does not exist, merging the data read from the memory corresponding to the first request address or the corresponding next-level cache memory into the hit cache line according to a write mask of the hit cache line, and updating the state and the write mask of the merged cache line;

and reading data corresponding to the first request address in the merged cache line.

The cache memory of claim 16, wherein the control buffer is further configured to perform:

receiving a second read request; the second read request is used for requesting to read data corresponding to a second request address in a cache line;

when a cache hit occurs for the second read request and the status of the hit cache line is not a partial write status; or, when the second read request has a cache hit, the state of the hit cache line is a partial write state, and the write masks corresponding to the second request address in the hit cache line are all 1, reading data corresponding to the second request address in the hit cache line.

The cache memory of claim 16, wherein the partial or complete absence of data corresponding to the request address in the hit cache line comprises: the state of the hit cache line is a partial write state, and the write masks corresponding to the request addresses in the hit cache line are not all 1;

the cache controller executes the merging of the data read from the memory corresponding to the request address or the corresponding next-level cache memory into the hit cache line, including:

writing data in a memory corresponding to a first position or a next-level cache memory into the first position in the hit cache line; the first location comprises a location in the hit cache line where a writemask is 0;

the data at the first position and the data at the second position in the written cache line form a merged cache line; the second location comprises a location in the cache line of the hit where the writemask is 1.

A cache memory, comprising: the cache comprises a cache controller, a cache line area and a mask area, wherein the cache line area comprises a plurality of cache lines; the cache line comprises a data field, a first address field, a state field and a mask index field; the mask region includes a mask line corresponding to the cache line, the mask line including a writemask field; wherein the content of the first and second substances,

the cache line comprises a data field for storing data;

the first address field is used for indicating address information of data stored in the cache line;

the status field is to indicate a status of the cache line; the state comprises a partial write state; the partial write state is to indicate that a data portion of the cache line is valid;

the mask index field is used for indicating address information of a write mask field of the cache line;

the write mask field is used for storing a write mask, and the write mask is used for indicating the position of the written data in the cache line corresponding to the mask line;

the cache controller is configured to receive a request and to update a state of a cache line and a write mask in response to the request.

The cache memory of claim 19, wherein the mask index field stores address information of the mask region; the mask row further comprises a second address field, and the second address field is used for indicating the cache line corresponding to the mask row.

The cache memory of claim 19 or 20, wherein the size of the writemask field is n/8 bytes, where n is the maximum number of bytes of data that can be stored by the cache line.

A cache controller, comprising:

a receiving unit, configured to receive a partial write request, where a size of data carried in the partial write request is smaller than a size of cacheable data of the cache line;

the writing unit is used for writing the data carried by the partial writing request into a corresponding position of a request address in the cache line;

an update unit for updating a write mask of the cache line; and updating the state of the cache line;

wherein the state of the cache line comprises a partial write state; the partial write state is to indicate that a data portion of the cache line is valid; the write mask is used to indicate the location of data in the cache line that has been written.

The cache controller of claim 22, wherein the write unit is specifically configured to:

when the partial write request is subjected to cache hit, the cache line is the hit cache line, and data carried by the partial write request is written into a corresponding position of the request address in the hit cache line; or the like, or, alternatively,

and when the partial write request is not hit, allocating a cache line for the partial write request, and writing data carried by the partial write request into a corresponding position of the request address in the allocated cache line.

The cache controller of claim 22 or 23,

the update unit is specifically configured to, when updating the write mask of the cache line: and updating the write mask of the cache line according to the request address.

The cache controller of any of claims 22-24, wherein when the updated write mask for the cache line is all 1's,

the write unit is further to: writing the data of the cache line into a memory or a next-level cache memory;

the update unit is further configured to: initializing a write mask for the cache line;

the update unit is specifically configured to, when updating the state of the cache line: and updating the state of the cache line into an invalid state.

The cache controller of any of claims 22-24, wherein when the write mask of the cache line is all 1's after the update,

the update unit is further configured to: initializing a write mask for the cache line;

the update unit is specifically configured to, when updating the state of the cache line: and updating the state of the cache line into a modified state.

A cache controller, comprising:

a receiving unit configured to receive a first read request; the first read request is used for requesting to read data corresponding to a first request address in a cache line;

a merging unit, configured to, when a cache hit occurs in the first read request and a part or all of data corresponding to the first request address does not exist in a hit cache line, merge, according to a write mask of the hit cache line, data read from a memory corresponding to the first request address or a corresponding next-level cache memory into the hit cache line;

the updating unit is used for updating the state of the merged cache line and the write mask;

a reading unit, configured to read data corresponding to the first request address in the merged cache line;

wherein the state of the cache line comprises a partial write state; the partial write state is to indicate that a data portion of the cache line is valid; the write mask is used to indicate the location of data in the cache line that has been written.

The cache controller of claim 27,

the receiving unit is further configured to: receiving a second read request; the second read request is used for requesting to read data corresponding to a second request address in a cache line;

the reading unit is further configured to: when a cache hit occurs for the second read request and the status of the hit cache line is not a partial write status; or, when the second read request has a cache hit, the state of the hit cache line is a partial write state, and the write masks corresponding to the second request address in the hit cache line are all 1, reading data corresponding to the second request address in the hit cache line.

The cache controller of claim 27, wherein the absence of a portion or all of the data corresponding to the first request address in the hit cache line comprises: the state of the hit cache line is a partial write state, and the write masks corresponding to the first request address in the hit cache line are not all 1; the merging unit is specifically configured to:

writing data in a memory corresponding to a first position or a next-level cache memory into the first position in the hit cache line; the first location comprises a location in the hit cache line where a writemask is 0;

the data at the first position and the data at the second position in the written cache line form a merged cache line; the second location comprises a location in the cache line of the hit where the writemask is 1.

A processor comprising at least one core and at least one cache memory; the cache memory includes: a cache controller and a cache line region; the cache line region comprises a plurality of cache lines, and each cache line comprises a data field, an address field, a state field and a write mask field; wherein the content of the first and second substances,

the data field is used for storing data;

the address field is used for indicating address information of data stored in the cache line;

the status field is to indicate a status of the cache line; the state comprises a partial write state; the partial write state is to indicate that a data portion of the cache line is valid;

the writemask field is used to store a writemask, which is used to indicate the location of data that has been written in the cache line;

the cache controller is used for receiving the request sent by the kernel, responding to the request, and updating the state of the cache line responding to the request and the write mask.

A processor comprising at least one core and at least one cache memory; the cache memory includes: the cache comprises a cache controller, a cache line area and a mask area, wherein the cache line area comprises a plurality of cache lines; the cache line comprises a data field, a first address field, a state field and a write mask field; the mask region includes a mask line corresponding to the cache line, the mask line including a writemask field; wherein the content of the first and second substances,

the cache line comprises a data field for storing data;

the first address field is used for indicating address information of data stored in the cache line;

the status field is to indicate a status of the cache line; the state comprises a partial write state; the partial write state is to indicate that a data portion of the cache line is valid;

the mask index field is used for indicating the address information of a write mask field corresponding to the cache line;

the write mask field is used for storing a write mask, and the write mask is used for indicating the position of the written data in the cache line corresponding to the mask line;

the cache controller is used for receiving the request sent by the kernel, responding to the request, and updating the state of the cache line responding to the request and the write mask.