阅读说明：本技术 摄像装置及电子设备 (Imaging device and electronic apparatus ) 是由 山本朗央 福留贵浩 于 2018-07-02 设计创作，主要内容包括：降低使用晶体管的乘法运算中的偏置成分。一种摄像装置，包括像素区域、第一电路、第二电路、第三电路及第四电路。像素区域包括多个像素，像素包括第一晶体管。对由第一电路和第二电路选择的像素供应偏置电位及权重电位。像素通过对光进行光电转换取得第一信号，第一晶体管对第一信号和权重电位进行乘法运算。第一晶体管使用第一信号和权重电位的乘法项以及偏置电位生成第一偏置项及第二偏置项。第三电路减去第一偏置项，第四电路减去第二偏置项。第四电路判定乘法项，并且通过第四电路所包括的神经网络接口输出判定结果。(A bias component in a multiplication operation using a transistor is reduced. An image pickup device includes a pixel region, a first circuit, a second circuit, a third circuit, and a fourth circuit. The pixel region includes a plurality of pixels including a first transistor. A bias potential and a weight potential are supplied to a pixel selected by the first circuit and the second circuit. The pixel obtains a first signal by photoelectrically converting light, and the first transistor multiplies the first signal by a weight potential. The first transistor generates a first bias term and a second bias term using a multiplication term of the first signal and the weight potential and the bias potential. The third circuit subtracts the first offset term and the fourth circuit subtracts the second offset term. The fourth circuit determines the multiplication term, and outputs the determination result through a neural network interface included in the fourth circuit.)

1. A camera device includes a neural network interface,

the image pickup device includes a pixel region, a first circuit, a second circuit, a third circuit, a fourth circuit, and a first signal line Wx,

wherein the pixel region includes a plurality of pixels,

the pixel includes a first transistor that is coupled to a first transistor,

the fourth circuit includes the neural network interface,

the pixel is electrically connected to the third circuit through the first signal line Wx,

the third circuit is electrically connected to the fourth circuit,

the first circuit has a function of supplying a scan signal to the pixel,

the second circuit has a function of supplying a weight potential to the pixel selected by the scan signal,

the pixel has a function of acquiring a first signal by photoelectrically converting light,

the pixel has a function of multiplying the first signal and the weight potential by the first transistor,

the first transistor has a function of generating a multiplication term of the first signal and the weight potential, a first bias term, and a second bias term,

the third circuit has the function of subtracting the first bias term,

the fourth circuit has the function of subtracting the second bias term,

the fourth circuit has a function of deciding the multiplication term,

and the fourth circuit outputs the determination result through the neural network interface.

2. The image pickup apparatus according to claim 1,

wherein the second circuit further has a function of supplying a bias potential to the pixel selected by the scan signal,

the pixel has a function of generating a second signal by adding the bias potential to the first signal,

the pixel has a function of generating a third signal by adding the weight potential to the bias potential,

the pixel has a function of generating a fourth signal by adding the bias potential and the weight potential to the first signal,

the first transistor has a function of multiplying the second signal by an arbitrary magnification to generate a fifth signal,

the first transistor has a function of multiplying the third signal by an arbitrary magnification to generate a sixth signal,

the first transistor has a function of generating a seventh signal by multiplying the fourth signal by an arbitrary magnification,

the third circuit has a function of storing the second signal,

the third circuit has a function of generating an eighth signal by operating the seventh signal and the fifth signal,

the fourth circuit has a function of storing the eighth signal,

the fourth circuit has a function of generating a ninth signal by operating the eighth signal and the sixth signal,

the ninth signal is outputted as a multiplication term of the first signal and the weight potential,

the fourth circuit has a function of deciding the ninth signal,

and the fourth circuit outputs the determination result through the neural network interface.

3. The image pickup apparatus according to claim 1 or 2, further comprising:

an analog-digital conversion circuit, a signal line Pio and a wiring VRS,

wherein the pixel has a function of outputting the first data to the analog-digital conversion circuit through the signal line Pio,

the pixel has a function of being inputted with the first potential supplied to the wiring VRS through the signal line Pio,

and the pixel is used as a neuron element of a neural network when a first potential supplied to the wiring VRS is input through the signal line Pio.

4. The image pickup apparatus according to claim 1 or 2, further comprising:

a wiring VPD, a wiring VDM, a signal line G1, a signal line G2, a signal line G3, a signal line Tx, a signal line Res, a signal line S1, and a signal line S2,

wherein the pixel includes a photoelectric conversion element, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor,

the first circuit is electrically connected to the pixel through the signal line G1,

the first circuit is electrically connected to the pixel through the signal line G2,

the first circuit is electrically connected to the pixel through the signal line G3,

the second circuit is electrically connected to the pixel through the signal line S1,

the second circuit is electrically connected to the pixel through the signal line S2,

one of the electrodes of the photoelectric conversion element is electrically connected to the wiring VPD,

the other of the electrodes of the photoelectric conversion element is electrically connected to one of a source and a drain of the second transistor,

a gate electrode of the second transistor is electrically connected to the signal line Tx,

the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the third transistor, the gate of the fourth transistor, and one of the electrodes of the first capacitor,

the other of the source and the drain of the third transistor is electrically connected to the wiring VRS,

a gate of the third transistor is electrically connected to the signal line Res,

one of a source and a drain of the fourth transistor is electrically connected to the wiring VDM,

the other of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor and one of the electrodes of the second capacitor,

the other of the source and the drain of the fifth transistor is electrically connected to the wiring Pio,

the gate of the fifth transistor is electrically connected to the signal line G3,

the other electrode of the second capacitor is electrically connected to the gate of the first transistor, one of the source and the drain of the sixth transistor, and one of the electrodes of the third capacitor,

one of a source and a drain of the first transistor is electrically connected to the first signal line Wx,

the other of the source and the drain of the sixth transistor is electrically connected to the signal line S1,

the gate of the sixth transistor is electrically connected to the signal line G1,

the other electrode of the third capacitor is electrically connected to one of a source and a drain of the seventh transistor,

the other of the source and the drain of the seventh transistor is electrically connected to the signal line S2, and the gate of the seventh transistor is electrically connected to the signal line G2.

5. The image pickup apparatus according to claim 4, further comprising:

a signal line Csw, a signal line Cswb, a signal line Eabs, a signal line Osp, a signal line Ewx, a signal line Mac, and a wiring VIV,

wherein the third circuit comprises a current mirror circuit, a storage circuit and an output circuit,

the current mirror circuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor,

the memory circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a fourth capacitor,

the output circuit includes a sixteenth transistor and a resistor R1,

the wiring VDM is electrically connected to one of a source and a drain of the eighth transistor and one of a source and a drain of the ninth transistor,

a gate of the eighth transistor is electrically connected to a gate of the ninth transistor, one of a source and a drain of the tenth transistor, and one of a source and a drain of the eleventh transistor,

the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the tenth transistor and one of the source and the drain of the twelfth transistor,

a gate of the tenth transistor is electrically connected to the wiring Cswb,

a gate of the eleventh transistor is electrically connected to the signal line Csw,

a gate of the twelfth transistor is electrically connected to the signal line Eabs,

the other of the source and the drain of the twelfth transistor is electrically connected to one of the first signal line Wx and the source and the drain of the fifteenth transistor,

the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the eleventh transistor, one of the source and the drain of the thirteenth transistor, and one of the source and the drain of the fourteenth transistor,

a gate of the fourteenth transistor is electrically connected to the signal line Osp,

the other of the source and the drain of the fourteenth transistor is electrically connected to one of the source and the drain of the fifteenth transistor, one of the electrodes of the fourth capacitor, and the gate of the thirteenth transistor,

a gate of the fifteenth transistor is electrically connected to the signal line Res,

the other of the source and the drain of the sixteenth transistor is electrically connected to one of the electrodes of the resistor R1 and the signal line Mac,

the gate of the sixteenth transistor is electrically connected to the signal line Ewx,

and the other of the electrodes of the resistor R1 is electrically connected to the wiring VIV.

6. The image pickup apparatus according to claim 1 or 2, further comprising:

a signal line Sh, a signal line CL, a signal line Out, a wiring VCDS, and a wiring JD,

wherein the fourth circuit comprises a CDS circuit and a decision circuit,

the CDS circuit includes a fifth capacitor, a sixth capacitor, an operational amplifier OP1, and a seventeenth transistor,

the determination circuit includes a seventh capacitor, an operational amplifier OP2 and an eighteenth transistor,

the signal line Mac is electrically connected to one of the electrodes of the fifth capacitor,

a first input terminal of the operational amplifier OP1 is electrically connected to the other of the electrodes of the fifth capacitor, one of the electrodes of the sixth capacitor, and one of the source and the drain of the seventeenth transistor,

a gate of the seventeenth transistor is electrically connected to the signal line CL,

a second input terminal of the operational amplifier OP1 is electrically connected to the wiring VCDS,

an output terminal of the operational amplifier OP1 is electrically connected to the other of the electrodes of the sixth capacitor, the other of the source and the drain of the seventeenth transistor, and the one of the source and the drain of the eighteenth transistor,

a gate of the eighteenth transistor is electrically connected to the signal line Sh,

the other of the source and the drain of the eighteenth transistor is electrically connected to the first input terminal of the operational amplifier OP2 and one of the electrodes of the seventh capacitor,

a second input terminal of the operational amplifier OP2 is electrically connected to the wiring JD,

an output terminal of the operational amplifier OP2 is electrically connected to the signal line Out,

and the signal line Out is connected to the neural network.

7. The image pickup apparatus according to claim 1 or 2, further comprising:

the second signal line Wx, the signal line Bsel1 and the switch Bsw,

wherein the switch Bsw has a function of electrically connecting the first signal line Wx and the second signal line Wx according to a signal supplied to the wiring Bsel,

the third circuit has a function of being supplied with a plurality of the fifth signals, a plurality of the sixth signals, and a plurality of the seventh signals from a plurality of the pixels connected to the first signal line Wx and a plurality of the pixels connected to the second signal line Wx,

the third circuit has a function of adding together the fifth signal, the sixth signal, and the seventh signal supplied from each pixel, and then subtracting the first bias term,

the image pickup device has a function of selecting a selection range of a plurality of the pixels in accordance with a signal supplied to the switch Bsw,

and the image pickup device performs pooling processing corresponding to the selection range of the pixels.

8. The image pickup apparatus according to claim 4,

wherein the photoelectric conversion element includes selenium or a compound containing selenium.

9. The image pickup apparatus according to claim 4,

wherein one or more of the first transistor, the second transistor, the fourth transistor, the sixth transistor, and the seventh transistor comprises a metal oxide in a channel formation region.

10. The image pickup apparatus according to claim 4,

wherein the thirteenth transistor has the same channel length and channel width as the fifth transistor.

11. The image pickup apparatus according to claim 5,

wherein the second potential supplied to the wiring VIV is smaller than the third potential supplied to the wiring VDM.

12. The image pickup apparatus according to claim 10,

wherein the metal oxide comprises In, Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf).

13. An electronic apparatus comprising the image pickup device and the display device according to claim 1 or 2.

Technical Field

One embodiment of the present invention relates to an imaging device and an electronic apparatus.

Note that one embodiment of the present invention is not limited to the above-described technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a method for driving the same, or a method for manufacturing the same.

In this specification and the like, a semiconductor device refers to an element, a circuit, a device, or the like which can operate by utilizing semiconductor characteristics. As an example, a semiconductor element such as a transistor or a diode is a semiconductor device. As another example, a circuit including a semiconductor element is a semiconductor device. As another example, a device including a circuit including a semiconductor element is a semiconductor device.

Background

With the development of information technologies such as IoT (Internet of things) and AI (Artificial Intelligence), the amount of data to be processed tends to increase. In order to utilize information technologies such as IoT and AI in electronic devices, it is necessary to manage a large amount of data in a decentralized manner.

As the display devices have become higher in definition and higher in gray scale, the amount of image data has increased, and therefore, an efficient management method has been required. In addition, the increase in the amount of data increases the amount of computation for processing image data, and thus power consumption and computation processing time increase.

In an imaging system of an in-vehicle electronic apparatus, an imaging system for monitoring a moving object, and the like, improvement of accuracy of image recognition using AI has been receiving attention. For example, patent document 1 discloses a technique for providing an imaging device with an arithmetic function.

[ Prior Art document ]

[ patent document ]

[ patent document 1] Japanese patent application laid-open No. 2016-123087

Disclosure of Invention

Technical problem to be solved by the invention

With the development of technology, in an image pickup apparatus including a solid-state image pickup element such as a CMOS image sensor, it is possible to easily pick up a high-quality image. It is required to install more intelligent functions also in the next-generation image pickup apparatus.

In order to recognize an object from image data, high-level image processing is required. In the height image processing, various analysis processes for analyzing an image, such as a filter process and a comparison operation process, are used. In the analysis processing for performing image processing, the larger the number of pixels processed, the larger the amount of computation, and the larger the amount of computation, the longer the processing time. For example, in an in-vehicle image system, there is a problem that an increase in processing time affects safety. Further, in the image system, there is a problem that the power consumption increases as the amount of computation increases.

In view of the above, it is an object of one embodiment of the present invention to provide an imaging apparatus having a novel structure. Another object of one embodiment of the present invention is to provide an imaging apparatus having a neural network pooling layer. Another object of one embodiment of the present invention is to provide an imaging apparatus having a novel configuration, which can reduce the amount of computation and shorten the processing time. It is another object of an embodiment of the present invention to provide an image pickup apparatus having a novel configuration that can reduce power consumption.

Note that the description of these objects does not hinder the existence of other objects. In addition, one embodiment of the present invention does not necessarily achieve all of the above-described objects. Objects other than the above objects will be apparent from the description of the specification, drawings, claims, and the like, and objects other than the above objects may be extracted from the description of the specification, drawings, claims, and the like.

Note that the object of one embodiment of the present invention is not limited to the above object. The above object does not hinder the existence of the other objects. Further, the other objects are objects which are not mentioned above and will be described in the following description. A person skilled in the art can derive and appropriately extract the above-mentioned object from the description of the specification, the drawings, and the like. One embodiment of the present invention achieves at least one of the above-described and/or other objects.

Means for solving the problems

One embodiment of the present invention is an imaging device including a neural network interface, the imaging device including a pixel region (10), a first circuit (11), a second circuit (12), a third circuit (13), a fourth circuit (14), and a first signal line Wx, the pixel region including a plurality of pixels (P), the pixels including first transistors (25), and the fourth circuit including the neural network interface. The pixel is electrically connected to a third circuit through a first signal line Wx, the third circuit is electrically connected to a fourth circuit, the first circuit has a function of supplying a scanning signal to the pixel, and the second circuit has a function of supplying a weighted potential to the pixel selected by the scanning signal. The pixel has a function of photoelectrically converting light to obtain a first signal, the pixel has a function of multiplying the first signal by a weight potential via a first transistor, and the first transistor has a function of generating a multiplication term of the first signal by the weight potential, a first bias term (C4), and a second bias term (C6). The third circuit has the function of subtracting the first offset term and the fourth circuit has the function of subtracting the second offset term. The fourth circuit has a function of judging the multiplication term, and outputs a judgment result through the neural network interface.

In the imaging device having each of the above configurations, it is preferable that the second circuit further has a function of supplying a bias potential to a pixel selected by the scanning signal, the pixel has a function of generating a second signal by adding the bias potential to the first signal, the pixel has a function of generating a third signal by adding the weight potential to the bias potential, and the pixel has a function of generating a fourth signal by adding the bias potential and the weight potential to the first signal. The first transistor has a function of multiplying the second signal by an arbitrary magnification to generate a fifth signal, the first transistor has a function of multiplying the third signal by an arbitrary magnification to generate a sixth signal, and the first transistor has a function of multiplying the fourth signal by an arbitrary magnification to generate a seventh signal. The third circuit has a function of storing the second signal, and the third circuit has a function of generating an eighth signal by operating the seventh signal and the fifth signal. The fourth circuit has a function of storing the eighth signal, the fourth circuit has a function of generating a ninth signal by operating the eighth signal and the sixth signal, the ninth signal is outputted as a multiplication term of the first signal and the weight potential, the fourth circuit has a function of determining the ninth signal, and the fourth circuit outputs a determination result through the neural network interface.

In the imaging device having each of the above configurations, it is preferable that the imaging device further includes an analog-digital conversion circuit (15), a signal line Pio, and a wiring VRS, the pixel has a function of outputting first data to the analog-digital conversion circuit through the signal line Pio, the pixel has a function of being inputted with a first potential supplied to the wiring VRS through the signal line Pio, and the pixel is used as a neuron of a neural network when the first potential supplied to the wiring VRS is inputted through the signal line Pio.

In the imaging device having each of the above configurations, the imaging device preferably further includes a wiring VPD, a wiring VDM, a signal line G1, a signal line G2, a signal line G3, a signal line Tx, a signal line Res, a signal line S1, and a signal line S2, and the pixel preferably includes a photoelectric conversion element (50), a first transistor (21), a second transistor (22), a third transistor (23), a fourth transistor (24), a fifth transistor (25), a sixth transistor (26), a seventh transistor (27), a first capacitor (C1), a second capacitor (C2), and a third capacitor (C3). The first circuit (11) is electrically connected to the pixel through a signal line G1, the first circuit is electrically connected to the pixel through a signal line G2, the first circuit is electrically connected to the pixel through a signal line G3, the second circuit (12) is electrically connected to the pixel through a signal line S1, and the second circuit is electrically connected to the pixel through a signal line S2. One of electrodes of the photoelectric conversion element is electrically connected to a wiring VPD, the other of the electrodes of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor, a gate of the first transistor is electrically connected to a signal line Tx, the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, a gate of the third transistor, and an electrode of the first capacitor, the other of the source and the drain of the second transistor is electrically connected to a wiring VRS, a gate of the second transistor is electrically connected to a signal line Res, one of a source and a drain of the third transistor is electrically connected to a wiring VDM, the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and one of an electrode of the second capacitor, the other of the source and the drain of the fourth transistor is electrically connected to a wiring Pio, a gate of the fourth transistor is electrically connected to the signal line G3, the other electrode of the second capacitor is electrically connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of electrodes of the third capacitor, one of the source and the drain of the fifth transistor is electrically connected to the first signal line Wx, the other of the source and the drain of the sixth transistor is electrically connected to the signal line S1, the gate of the sixth transistor is electrically connected to the signal line G1, the other electrode of the third capacitor is electrically connected to one of a source and a drain of the seventh transistor, the other of the source and the drain of the seventh transistor is electrically connected to the signal line S2, and the gate of the seventh transistor is electrically connected to the signal line G2.

In the imaging device having each of the above configurations, it is preferable that the imaging device further includes a signal line Csw, a signal line Cswb, a signal line Eabs, a signal line Osp, a signal line Ewx, a signal line Mac, and a wiring VIV, the third circuit includes a current mirror circuit including an eighth transistor (31), a ninth transistor (32), a tenth transistor (33), an eleventh transistor (34), and a twelfth transistor (35), the memory circuit includes a thirteenth transistor (36), a fourteenth transistor (37), a fifteenth transistor (38), and a fourth capacitor (C4), and the output circuit includes a sixteenth transistor (39) and a resistor R1. The wiring VDM is electrically connected to one of a source and a drain of the eighth transistor (31) and one of a source and a drain of the ninth transistor (32), a gate of the eighth transistor (31) is electrically connected to one of a gate of the ninth transistor (32), one of a source and a drain of the tenth transistor (33), and one of a source and a drain of the eleventh transistor (34), the other of the source and the drain of the eighth transistor (31) is electrically connected to the other of the source and the drain of the tenth transistor (33) and one of the source and the drain of the twelfth transistor (35), a gate of the tenth transistor (33) is electrically connected to the signal line Cswb, a gate of the eleventh transistor (34) is electrically connected to the signal line Csw, a gate of the twelfth transistor (35) is electrically connected to the signal line Eabs, the other of the source and the drain of the twelfth transistor (35) is electrically connected to one of the first signal line Wx and the source and the drain of the sixteenth transistor (36), the other of the source and the drain of the ninth transistor (32) is electrically connected to the other of the source and the drain of the eleventh transistor (34), the one of the source and the drain of the thirteenth transistor (36), and the one of the source and the drain of the fourteenth transistor (37), the gate of the fourteenth transistor (37) is electrically connected to the signal line Osp, the other of the source and the drain of the fourteenth transistor (37) is electrically connected to the one of the source and the drain of the fifteenth transistor (38), the one of the electrodes of the fourth capacitor (C4), and the gate of the thirteenth transistor (36), the gate of the fifteenth transistor (38) is electrically connected to the signal line Res, the other of the source and the drain of the sixteenth transistor (39) is electrically connected to the one of the electrodes of the resistor R1 and the signal line Mac, and the gate of the sixteenth transistor (39) is electrically connected to the signal line Ewx, the other of the electrodes of the resistor R1 is electrically connected to the wiring VIV.

In the imaging device having each of the above configurations, it is preferable that the imaging device further includes a signal line Sh, a signal line CL, a signal line Out, a wiring VCDS, and a wiring JD, the fourth circuit includes a CDS circuit including a fifth capacitor (C5), a sixth capacitor (C6), an operational amplifier OP1, and a seventeenth transistor (41), and the determination circuit includes a seventh capacitor (C7), an operational amplifier OP2, and an eighteenth transistor (41). The signal line Mac is electrically connected to one of the electrodes of the fifth capacitor (C5), the first input terminal of the operational amplifier OP1 is electrically connected to the other of the electrodes of the fifth capacitor (C5), one of the electrodes of the sixth capacitor (C6), and one of the source and the drain of the seventeenth transistor (41), the gate of the seventeenth transistor (41) is electrically connected to the signal line CL, the second input terminal of the operational amplifier OP1 is electrically connected to the wiring VCDS, the output terminal of the operational amplifier OP1 is electrically connected to the other of the electrodes of the sixth capacitor (C6), the other of the source and the drain of the seventeenth transistor (41), and one of the source and the drain of the eighteenth transistor (42), the gate of the eighteenth transistor is electrically connected to the signal line Sh, the other of the source and the drain of the eighteenth transistor is electrically connected to the first input terminal of the operational amplifier OP2, and one of the electrodes of the seventh capacitor (C7), a second input terminal of the operational amplifier OP2 is electrically connected to the wiring JD, an output terminal of the operational amplifier OP2 is electrically connected to the signal line Out, and the signal line Out is connected to the neural network.

In the imaging device having each of the above configurations, the imaging device preferably further includes a second signal line Wx, a signal line Bsel1, and a switch Bsw. The switch Bsw has a function of electrically connecting the first signal line Wx and the second signal line Wx in accordance with a signal supplied to the wiring Bsel, the third circuit has a function of being supplied with a plurality of fifth signals, a plurality of sixth signals, and a plurality of seventh signals from a plurality of pixels connected to the first signal line Wx and a plurality of pixels connected to the second signal line Wx, and the third circuit has a function of adding together the fifth signals, the sixth signals, and the seventh signals supplied from the respective pixels and then subtracting the first offset term. The image pickup device has a function of selecting a selection range of a plurality of pixels in accordance with a signal supplied to the switch Bsw, and performs pooling processing corresponding to the selection range of the pixels.

In the imaging devices having the above-described configurations, the photoelectric conversion element preferably includes selenium or a compound containing selenium.

In the imaging device having each of the above configurations, it is preferable that one or more of the first transistor (21), the second transistor (22), the fourth transistor (24), the sixth transistor (26), and the seventh transistor (27) include a metal oxide in a channel formation region.

In the imaging devices having the above-described configurations, the thirteenth transistor (36) preferably has the same channel length and channel width as those of the fifth transistor (25).

In the imaging devices having the above-described configurations, it is preferable that the second voltage supplied to the wiring VIV be smaller than the third voltage supplied to the wiring VDM.

In the imaging devices having the above-described configurations, the metal oxide preferably contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

An electronic apparatus including the imaging device and the display device described in any one of the above is preferable.

Effects of the invention

In view of the above, one embodiment of the present invention can provide an image pickup apparatus having a novel structure. Further, an embodiment of the present invention can provide an imaging apparatus having a pooling layer of a neural network. Further, an embodiment of the present invention can provide an imaging apparatus having a novel configuration capable of reducing a processing time by suppressing an amount of computation. It is another object of an embodiment of the present invention to provide an image pickup apparatus having a novel configuration that can reduce power consumption.

Note that the effect of one embodiment of the present invention is not limited to the above-described effect. The above effects do not hinder the existence of other effects. The other effects are those not mentioned above and will be described in the following description. A person skilled in the art can derive and appropriately extract the effects not mentioned above from the description of the specification, the drawings, and the like. One embodiment of the present invention achieves at least one of the above-described effects and/or other effects. Thus, one embodiment of the present invention may not have the above-mentioned effects in some cases.