阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 下条亮平 于 2019-01-10 设计创作，主要内容包括：半导体装置具备：第1导电型第1半导体层；第2导电型第2半导体层,选择性地设置在第1半导体层上；第1导电型第3半导体层,选择性地设置在第2半导体层上；第1绝缘膜,覆盖第1半导体层与第3半导体层之间的一部分第2半导体层；控制电极,隔着第1绝缘膜与一部分第2半导体层相对；第2导电型第4半导体层,设置在第1半导体层的下表面侧；第1导电型第5半导体层,在沿第1半导体层下表面的第1方向上与第4半导体层并列；第6半导体层,设置在第1半导体层与第5半导体层之间,与第4半导体层相连,连接部分,为在第1半导体层与第5半导体层之间不存在第6半导体层的部分。第6半导体层与第4半导体层相比第2导电型杂质的有效浓度低。(The semiconductor device includes: a 1 st semiconductor layer of a 1 st conductivity type; a 2 nd semiconductor layer of a 2 nd conductivity type selectively provided on the 1 st semiconductor layer; a 1 st conductive type 3 rd semiconductor layer selectively disposed on the 2 nd semiconductor layer; a 1 st insulating film covering a part of the 2 nd semiconductor layer between the 1 st semiconductor layer and the 3 rd semiconductor layer; a control electrode facing a part of the 2 nd semiconductor layer with the 1 st insulating film interposed therebetween; a 4 th semiconductor layer of the 2 nd conductivity type provided on the lower surface side of the 1 st semiconductor layer; a 1 st conductive type 5 th semiconductor layer juxtaposed with the 4 th semiconductor layer in a 1 st direction along a lower surface of the 1 st semiconductor layer; and a 6 th semiconductor layer disposed between the 1 st semiconductor layer and the 5 th semiconductor layer and connected to the 4 th semiconductor layer, wherein the connection portion is a portion where the 6 th semiconductor layer is not present between the 1 st semiconductor layer and the 5 th semiconductor layer. The 6 th semiconductor layer has a lower effective concentration of impurities of the 2 nd conductivity type than the 4 th semiconductor layer.)

1. A semiconductor device, comprising:

a 1 st semiconductor layer of a 1 st conductivity type;

a 2 nd semiconductor layer of a 2 nd conductivity type selectively provided on the 1 st semiconductor layer;

a 3 rd semiconductor layer of a 1 st conductivity type selectively provided on the 2 nd semiconductor layer;

a 1 st insulating film covering a part of the 2 nd semiconductor layer between the 1 st semiconductor layer and the 3 rd semiconductor layer;

a control electrode facing a part of the 2 nd semiconductor layer with the 1 st insulating film interposed therebetween;

a 4 th semiconductor layer of a 2 nd conductivity type provided on a lower surface side of the 1 st semiconductor layer;

a 5 th semiconductor layer of a 1 st conductivity type, which is arranged in parallel with the 4 th semiconductor layer in a 1 st direction along a lower surface of the 1 st semiconductor layer;

the 6 th semiconductor layer is arranged between the 1 st semiconductor layer and the 5 th semiconductor layer and is connected with the 4 th semiconductor layer; and

a connecting portion, which is a portion located between the 1 st semiconductor layer and the 5 th semiconductor layer without the 6 th semiconductor layer, for electrically connecting the 5 th semiconductor layer and the 1 st semiconductor layer,

the 6 th semiconductor layer has a compensated concentration of the 2 nd conductive type impurity obtained by subtracting a concentration of the 1 st conductive type impurity from a concentration of the 2 nd conductive type impurity, and the compensated concentration of the 2 nd conductive type impurity in the 6 th semiconductor layer is lower than the compensated concentration of the 2 nd conductive type impurity in the 4 th semiconductor layer.

2. The semiconductor device according to claim 1,

the semiconductor device further includes:

a 1 st electrode electrically connected to the 3 rd semiconductor layer and covering the control electrode;

a 2 nd insulating film electrically insulating the control electrode from the 1 st electrode; and

and a 2 nd electrode electrically connected to the 4 th semiconductor layer and the 5 th semiconductor layer.

3. The semiconductor device according to claim 2,

the control electrode is provided so as to extend in a 2 nd direction from the 1 st electrode toward the 2 nd electrode, and is opposed to the 1 st semiconductor layer, the 2 nd semiconductor layer, and the 3 rd semiconductor layer with the 1 st insulating film interposed therebetween.

4. The semiconductor device according to claim 1,

the 5 th semiconductor layer is electrically connected to the 1 st semiconductor layer via the connection portion.

5. The semiconductor device according to claim 1,

the 4 th semiconductor layer and the 5 th semiconductor layer are alternately arranged in the 1 st direction along a lower surface of the 1 st semiconductor layer.

6. The semiconductor device according to claim 1,

the connection portion is provided at a position separated from the 4 th semiconductor layer in the 1 st direction along a lower surface of the 1 st semiconductor layer.

7. The semiconductor device according to claim 5,

a plurality of the connection portions are arranged in parallel along a 3 rd direction intersecting the 1 st direction along a lower surface of the 1 st semiconductor layer,

the 4 th semiconductor layer extends in the 3 rd direction along a lower surface of the 1 st semiconductor layer,

the connection portion is located between 4 th semiconductor layers adjacent in the 1 st direction.

8. The semiconductor device according to claim 1,

the semiconductor device further includes:

a 7 th semiconductor layer which is provided between the 1 st semiconductor layer and the 4 th semiconductor layer and between the 1 st semiconductor layer and the 6 th semiconductor layer, and contains a 1 st conductivity type impurity at a higher concentration than a 1 st conductivity type impurity of the 1 st semiconductor layer,

the 5 th semiconductor layer is connected to the 7 th semiconductor layer via the connection portion.

9. The semiconductor device according to claim 8,

the 5 th semiconductor layer includes a 1 st conductive type impurity at a higher concentration than the 1 st conductive type impurity of the 7 th semiconductor layer.

10. The semiconductor device according to claim 1,

the 4 th semiconductor layer includes a 2 nd conductive type impurity at a higher concentration than the 2 nd conductive type impurity of the 2 nd semiconductor layer.

11. The semiconductor device according to claim 2,

the semiconductor device further includes:

an 8 th semiconductor layer selectively provided between the 2 nd semiconductor layer and the 1 st electrode, containing a 2 nd conductive type impurity at a higher concentration than the 2 nd conductive type impurity of the 2 nd semiconductor layer,

the 8 th semiconductor layer is in contact with the 2 nd semiconductor layer and is electrically connected with the 1 st electrode.

12. The semiconductor device according to claim 1,

the 6 th semiconductor layer includes a 1 st portion, a 2 nd portion, and a 3 rd portion juxtaposed in the 1 st direction,

the 1 st portion is connected to the 4 th semiconductor layer, the 2 nd portion is located between the 1 st portion and the 3 rd portion,

a 1 st thickness of the 1 st portion in a 2 nd direction from the 1 st semiconductor layer toward the 5 th semiconductor layer is thicker than a 2 nd thickness of the 2 nd portion in the 2 nd direction, and the 2 nd thickness is thicker than a 3 rd thickness of the 3 rd portion in the 2 nd direction.

13. The semiconductor device according to claim 12,

the offset concentration of the impurity of the 2 nd conductivity type in the 1 st portion is higher than the offset concentration of the impurity of the 2 nd conductivity type in the 2 nd portion, and the offset concentration of the impurity of the 2 nd conductivity type in the 2 nd portion is higher than the offset concentration of the impurity of the 2 nd conductivity type in the 3 rd portion.

14. The semiconductor device according to claim 1,

the 6 th semiconductor layer includes a 1 st portion, a 2 nd portion, and a 3 rd portion juxtaposed in the 1 st direction,

the 1 st portion is connected to the 4 th semiconductor layer, the 2 nd portion is located between the 1 st portion and the 3 rd portion,

the offset concentration of the impurity of the 2 nd conductivity type in the 1 st portion is higher than the offset concentration of the impurity of the 2 nd conductivity type in the 2 nd portion, and the offset concentration of the impurity of the 2 nd conductivity type in the 2 nd portion is higher than the offset concentration of the impurity of the 2 nd conductivity type in the 3 rd portion.

15. The semiconductor device according to claim 14,

the 3 rd portion of the 6 th semiconductor layer is adjacent to the connection portion.

Technical Field

Background

A power converter for controlling a high withstand voltage and a large current is configured using a switching element such as an IGBT (Insulated Gate bipolar transistor) and a diode element. For example, by using a semiconductor device in which a switching element and a diode element are integrated into one chip, the configuration of the power converter can be simplified and reduced in size. However, in such a semiconductor device, it is required to reduce switching loss and conduction loss.

Disclosure of Invention

Drawings

Fig. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment.

Fig. 2A to 2C are schematic views showing a semiconductor device according to an embodiment.

Fig. 3A and 3B are schematic diagrams showing characteristics of the semiconductor device according to the embodiment.

Fig. 4A to 4D are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment.

Fig. 5A and 5B are schematic views showing a semiconductor device according to modification 1 of the embodiment.

Fig. 6 is a schematic cross-sectional view showing a semiconductor device according to modification 2 of the embodiment.

Fig. 7 is a schematic cross-sectional view showing a semiconductor device according to modification 3 of the embodiment.

Embodiments relate to a semiconductor device.