Packaging method and related packaging structure
阅读说明：本技术 封装方法及相关的封装结构 (Packaging method and related packaging structure ) 是由 陈志明 谢元智 喻中一 于 2016-11-02 设计创作，主要内容包括：本发明的实施例提供封装方法及相关的封装结构。所述方法包括提供第一半导体衬底；在所述第一半导体衬底上形成接合区,其中所述第一半导体衬底的所述接合区包括第一接合金属层与第二接合金属层；提供具有接合区的第二半导体衬底,其中所述第二半导体衬底的所述接合区包括第三接合金属层；以及通过使所述第一半导体衬底的所述接合区接触所述第二半导体衬底的所述接合区,将所述第一半导体衬底接合到所述第二半导体衬底；其中所述第一与第三接合金属层包括铜(Cu),且所述第二接合金属层包括锡(Sn)。(The embodiment of the invention provides a packaging method and a related packaging structure. The method includes providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate comprises a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate comprises a third bonding metal layer; and bonding the first semiconductor substrate to the second semiconductor substrate by contacting the bonding region of the first semiconductor substrate to the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers comprise copper (Cu) and the second bonding metal layer comprises tin (Sn).)
1. A method of packaging, comprising:
providing a first semiconductor substrate;
providing an induction substrate on the first semiconductor substrate;
depositing a first copper (Cu) bonding layer and a tin (Sn) bonding layer on the induction substrate;
patterning and etching the first copper bonding layer and the tin bonding layer, wherein the inductive substrate is etched to a first depth to form a bonding protrusion;
etching the sensing substrate to a second depth to form a microelectromechanical systems (MEMS) structure of the sensing substrate, wherein the second depth is greater than the first depth;
providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate comprises a second copper bonding layer;
bonding the first semiconductor substrate to the second semiconductor substrate by bringing the tin bonding layer of the bonding protrusion of the first semiconductor substrate into contact with the second copper bonding layer of the bonding region of the second semiconductor substrate; and
providing a bonding temperature and a bonding pressure when the tin bonding layer of the first semiconductor substrate contacts the second copper bonding layer of the second semiconductor substrate to form an alloy Cu by reaction of tin and copper of the tin bonding layer of the first semiconductor substrate3Sn, wherein the copper is provided by the first copper bonding layer and the second copper bonding layer.
2. The method of claim 1, wherein a reaction of the tin and the copper of the tin bonding layer of the first semiconductor substrate forms an alloy Cu3Sn until the tin is completely consumed.
3. The method of claim 1, further comprising:
removing a portion of the first semiconductor substrate so that a bonding pad of the second semiconductor substrate is not covered by the first semiconductor substrate, wherein the bonding pad of the second semiconductor substrate is used for receiving external bonding or wire bonding.
4. A method of packaging, comprising:
providing a first semiconductor substrate;
forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate comprises a first copper (Cu) bonding layer and a tin (Sn) bonding layer;
providing a second semiconductor substrate having a dielectric layer and a bonding region, the dielectric layer forming an opening to expose the bonding region of the second semiconductor substrate, wherein the bonding region of the second semiconductor substrate comprises a second copper bonding layer;
bonding the bonding region of the first semiconductor substrate and the bonding region of the second semiconductor substrate by using auxiliary bonding tin; and
applying a pressing force of about 1MPa to about 2MPa or less per unit area to press the first and second semiconductor substrates against each other.
5. The method of claim 4, further comprising:
reacting the auxiliary bonding tin with the first copper bonding layer and the second copper bonding layer to form Cu3Sn until the auxiliary bonding tin is completely consumed.
6. The method of claim 4, wherein bonding the bonding region of the first semiconductor substrate and the bonding region of the second semiconductor substrate by the using auxiliary bonding tin comprises:
applying the auxiliary bonding tin on the first copper bonding layer prior to the bonding.
7. The method of claim 4, wherein bonding the bonding region of the first semiconductor substrate and the bonding region of the second semiconductor substrate by the using auxiliary bonding tin comprises:
applying the auxiliary bonding tin on the second copper bonding layer prior to the bonding.
8. The method of claim 4, wherein forming the junction region on the first semiconductor substrate comprises:
depositing the first copper bonding layer on the first semiconductor substrate; and
etching a portion of the first copper bonding layer to form the bonding region of the first semiconductor substrate.
9. A package structure, comprising:
a first semiconductor substrate having a first bonding region thereon, the first bonding region having a first copper (Cu) bonding layer; and
a second semiconductor substrate having a dielectric layer and a second bonding region thereon, the dielectric layer forming an opening to expose the second bonding region, the second bonding region including a second copper bonding layer;
wherein the first bonding region bonds the second bonding region, and a bonding interface between the first bonding region and the second bonding region comprises Cu3Sn。
10. The package structure of claim 9, wherein the first semiconductor substrate has a bonding protrusion, the bonding protrusion being located below the first bonding region.
Technical Field
The embodiment of the invention relates to a packaging method and a related packaging structure.
Background
In the field of micro-electro-mechanical systems (MEMS) and microelectronics, it is often necessary to bond wafers together to encapsulate structures in vacuum cavities or cavities having controlled gas pressures. This structure may have to be operable for very long periods of time, most often for decades. It may also be desirable to provide electrical connections between the wafers via the seal.
Of course, the absolute need to handle/bond the wafers together and provide a virtually coherent joint (join) of the cavity will provide a good enough seal that will not degrade over time. However, as modern semiconductor structures become more sophisticated, the overall thermal budget shrinks and the bonding temperature of existing eutectic bonding materials becomes unacceptable. In particular, the processing forces applied during the eutectic bonding process also decrease as advanced processes, such as MEMD structures, evolve.
Therefore, new bonding mechanisms are urgently needed by the semiconductor manufacturing industry to meet the above problems.
Disclosure of Invention
Some embodiments of the present invention provide a packaging method, comprising providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate comprises a first bonding metal layer and a second bonding metal layer; providing a semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate comprises a third bonding metal layer; and bonding the first semiconductor substrate to the second semiconductor substrate by contacting the bonding region of the first semiconductor substrate to the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers comprise copper (Cu) and the second bonding metal layer comprises tin (Sn).
Some embodiments of the present invention provide a packaging method, comprising providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate comprises a first bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate comprises a second bonding metal layer; bonding the bonding region of the first semiconductor substrate and the bonding region of the second semiconductor substrate by using an auxiliary bonding metal; and applying a pressing force of about 1MPa to about 2MPa or less per unit area to press the first and second semiconductor substrates against each other.
Some embodiments of the present invention provide a package structure comprising a first semiconductor substrate having a first bonding region thereon; and a second semiconductor substrate having a second bonding region thereon; wherein the first bonding region bonds the second bonding region and a bonding interface between the first and second bonding regions comprises Cu3Sn。
Drawings
To assist the reader in achieving the best understanding, it is suggested that the present invention be read with reference to the accompanying drawings and detailed written description thereof. Please note that the drawings in this patent specification are not necessarily drawn to scale in order to comply with industry standards. In some drawings, the dimensions may be exaggerated or minimized intentionally to assist the reader in understanding the discussion herein.
Fig. 1-11 are a series of cross-sectional views illustrating processing steps for fabricating a CMOS-MEMS device structure.
Detailed Description
The present invention provides several different embodiments or examples, which may be used to implement different features of the present invention. For simplicity of illustration, examples of specific components and arrangements are also described. It should be noted that these specific examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of how a first feature may be formed over or on a second feature may include certain embodiments in which the first feature is in direct contact with the second feature, and may also include other embodiments in which the second feature is intermediate to the first feature such that the first feature is not in direct contact with the second feature. Moreover, various examples of the invention may use repeated reference numerals and/or written labels to simplify and clarify the file, such repeated reference numerals and labels do not represent an association between different embodiments and configurations.
Furthermore, where the invention is described using spatially relative terms such as "below," "lower," "above," "below," "top," "bottom," and the like, for ease of description, the usage of the invention is to describe one element or feature's relationship to another element(s) or feature(s) in the figures. These spatially relative terms are intended to describe possible angles and orientations of the device in use and operation in addition to the angular orientation shown in the figures. The angular orientation of the device may vary (rotated 90 degrees or at other orientations) and these spatially relative descriptors used in the present invention are interpreted in the same manner.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Further, as used herein, the word "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the word "about" refers to the acceptable standard error of the mean, as considered by one of ordinary skill in the art. Except in the operating/working examples, or where otherwise indicated, such as amounts of materials, time periods, temperatures, operating conditions, proportions of amounts, and the like, disclosed herein, all numerical ranges, amounts, values, and percentages are to be understood as modified by the word "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges are expressed herein as from one end point to another end point or between two end points. All ranges disclosed herein are inclusive of the endpoints unless specifically stated otherwise.
The present invention relates generally to bonding, and more particularly to eutectic bonding. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
In the described embodiments, microelectromechanical systems (MEMS) refer to a class of structures or devices fabricated using semiconductor-based processes and having mechanical properties, such as the ability to move or deform. MEMS typically, but not always, interact with electronic signals. MEMS devices include, but are not limited to, gyroscopes, accelerometers, magnetometers, pressure sensors, and radio frequency components. In some embodiments, a MEMS device structure may comprise a plurality of the above MEMS devices. Silicon wafers containing MEMS devices or MEMS device structures are referred to as MEMS wafers.
In the described embodiments, a MEMS device may refer to a semiconductor device implemented as a microelectromechanical system. A MEMS device structure may refer to any feature associated with a combination of multiple MEMS devices. Engineered silicon-on-insulator (ESOI) may refer to SOI wafers having cavities (voids) beneath a silicon device layer or substrate. A cap or handle wafer typically refers to a thicker substrate that acts as a carrier for the thinner silicon sense substrate in a silicon-on-insulator wafer. The cover or handle substrate and the cover or handle wafer may be interchanged. In the described embodiments, a cavity may refer to an opening or recess in a substrate wafer, and an enclosed space (enclosure) may refer to a fully enclosed space.
To describe the features of the present invention in more detail, apparatus and methods of manufacture are disclosed, resulting in a MEMS device having features including improved bonding temperature and processing forces applied during bonding.
FIGS. 1-11 are cross-sectional views illustrating process steps for fabricating a MEMS device assembly or MEMS device, according to embodiments of the invention. In fig. 1, an induction substrate 104 and a cover substrate 101 are bonded together with a thin dielectric film 103 interposed therebetween, forming an ESOI substrate 102. Note that in an exemplary embodiment of the present invention, the sensing substrate 104 and the cover substrate 101 are bonded together by fusion bonding at relatively high processing temperatures such that the chemical species are further completely removed from the dielectric material prior to sealing the cavity of the MEMS structure. During bonding, the two substrates are annealed, which reduces the emission of chemicals during the cavity formation process. MEMS structures bonded by fusion bonding have greater mechanical strength than metal bonding due to the higher bonding ratio. Furthermore, fusion bonding allows Through Substrate Vias (TSVs) to be formed in MEMS structures without reducing yield. However, the concept of the present invention is not limited thereto. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. The concepts of the present invention may also be applied to other forms of MEMS device combinations in some embodiments.
The thin dielectric film 103 comprises a material such as silicon oxide or other insulating layer. Along the surface of the cover substrate 101, a plurality of cavities 112 of desired dimensions are defined and patterned, for example, by etching, but this is not a limitation of the present invention. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. A plurality of cavities 112 are used to accommodate adjacent movable masses of the MEMS device to be fabricated. The dimensions of each cavity 112 are determined based on the movable mass of the MEMS device and/or the desired performance. In some embodiments, each cavity 112 may be different depths or sizes from the other cavities.
The inductive substrate 104 is then thinned using grinding and/or other thinning processes to a desired thickness, as shown in FIG. 2. Existing thinning techniques, such as Chemical Mechanical Polishing (CMP) and/or Reactive Ion Etching (RIE), may be used to achieve the desired thickness. Suitable grinding and polishing equipment may be used for the thinning process. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. In some embodiments, an etch stop layer is integrated in the inductive substrate 104 to facilitate precise control of the thinning process. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
Referring to fig. 3, a metal layer 302 is then deposited on the inductive substrate 104. In this embodiment, metal layer 302 includes a copper (Cu) layer. In particular, metal layer 302 includes a thin titanium (Ti) layer below the Cu layer. In some embodiments, the metal layer 302 is deposited using electroplating, Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD). One of ordinary skill in the art would recognize many variations, modifications, and alternatives. Referring to fig. 4, then, another metal layer 304, different from the metal layer 302, is deposited on the metal layer 302. In this embodiment, the metal layer 304 includes a tin (Sn) layer. In some embodiments, metal layer 304 is deposited using electroplating, Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD). One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
The next step shown in fig. 5 is to pattern and etch the metal layers 302 and 304, depending on the structure of the MEMS to be produced. As a result of the patterning and etching operations, a plurality of bonding regions 402 'and 404' are formed for bonding in the following steps, such as eutectic bonding as used in the exemplary embodiment. In particular, each bonding region 402' includes metal layers 402 and 406; and each bonding region 404' includes metal layers 404 and 408, where metal layers 406 and 408 are considered as auxiliary bonding metal layers during the bonding operation to form a eutectic bond.
For clarity, the process flow does not show a photolithography etching process, in which a photoresist layer is deposited on the metal layer 304And patterned to form an etch mask. The dimensions of the etch mask may be tightly controlled during the photolithographic etching process and may be formed of any suitable material that is resistant to the etching process used to etch the metal layer. In some embodiments, silicon nitride (Si) is used3N4) The etching mask of (1). In some embodiments, the photoresist layer may serve as an etch mask. One of ordinary skill in the art would recognize many variations, modifications, and alternatives. Although fig. 5 illustrates a one-dimensional cross-sectional view, it will be apparent to those skilled in the art that a two-dimensional pattern of the desired geometry is formed in metal layers 302 and 304. In some embodiments, the bonding regions 402 'and 404' may further comprise nickel (Ni), germanium (Ge), aluminum (Al). In other embodiments, other materials may be used for the bonding regions, such as gold (Au), indium (In), or other solders with good adhesion under layers and improved wetting ability.
A first shallow cavity etch is performed selective to the sense substrate 104. During the first shallow cavity etch, a shallow cavity is formed to a depth measured from the surface of the sensing substrate 104 of fig. 5. After the first shallow cavity etch, a plurality of first step bonding protrusions 502 and 504 are left protruding from the etched surface of the sensing substrate 104, as shown in fig. 6. More specifically, a plurality of first step engagement protrusions 502 and 504 are located below the engagement regions 402 'and 404'. A plurality of first step bond bumps 502 and 504 carry conductive bond regions 402 'and 404' to form a stacked structure. In the illustrated embodiment, the width of the first step bonding protrusions 502 and 504 may be substantially equal to the bonding regions 402 'and 404' or wider than the bonding regions 402 'and 404'. The sidewalls of the plurality of first step engagement protrusions 502 and 504 may be vertical or tapered. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
The sensing substrate 104 is then patterned and etched to form the sensing substrate shown in fig. 7. The sensing substrate comprises a proof-mass, balanced or unbalanced, suspended by at least one spring or elastic device, and free to move in one of the x-, y-and z-directions, with at least one electrode embedded in said at least one spring or elastic device. The at least one spring or resilient device is attached to a support structure, which is attached to the sensing substrate 104. The mass block, the support structure and the at least one electrode are fabricated in the same semiconductor layer to form a driving/sensing circuit. In some embodiments, the at least one spring or resilient device forms a support network with the support structure. The mass suspended by the support network is free to move in any direction. MEMS capacitance induces or produces movement of a mass in any direction. In some embodiments, the direction may include a direction along at least one of the x-, y-, and z-directions.
In some embodiments, the patterning and etching techniques used to form the sensing substrate may vary depending on the form of the MEMS device. For example, the patterning and etching of a MEMS accelerometer is different from the patterning and etching of a MEMS gyroscope. Conventional etching techniques such as anisotropic etching, RIE or the like may be used. In some embodiments, the thickness of the sensing substrate 104 can vary as a function of position along a length of the sensing substrate, where the length is defined along a direction orthogonal to the thickness of the substrate. For example, the sensing substrate 104 may have a first thickness at one end, a second thickness at the center, and a third thickness at the other end.
Next, as shown in fig. 8A, the ESOI substrate 102 and Complementary Metal Oxide Semiconductor (CMOS) wafer 106 are pre-cleaned and then aligned between eutectic bonds. In the present invention, the CMOS wafer may be referred to as a CMOS substrate. The CMOS wafer 106 may include a substrate 812. The substrate 812 may comprise a semiconductor material, such as silicon, however, other semiconductor materials may be used. On the surface of substrate 812, a plurality of CMOS devices 814 (e.g., transistors) are formed. Further, an interconnect structure 816 is formed to electrically couple to the CMOS device 814. The interconnect structure 816 may include dielectric layers that further include low-k dielectric layers, non-low-k dielectric layers, such as passivation layers, and the like. Metal lines and vias, which may be formed of copper, aluminum, and combinations thereof, are formed in the dielectric layer.
The top dielectric layer 810 of the interconnect structure 816 is patterned, and a plurality of openings, including openings 802 and 804 corresponding to the bonding regions 402 'and 404', are formed in the top dielectric layer 810. Thus, bonding regions 806 and 808 are exposed. The dielectric layer 810 has a different melting characteristic than the bonding material of the plurality of bonding regions 806 and 808 of the CMOS substrate 106. In the illustrated embodiment, the bonding regions 806 and 808 comprise a Cu layer. In particular, the bonding regions 806 and 808 further include a thin Ti layer below the Cu layer. However, this is not a limitation of the present invention.
In some other embodiments, another metal layer of a bonding material different from the bonding materials of the bonding regions 806 and 808 is further formed on the bonding regions 806 and 808 for eutectic bonding. The metal layers formed on bonding regions 806 and 808 comprise the same metal as metal layers 406 and 408. An embodiment is shown in fig. 8B, where metal layers 406 'and 408' are electroplated onto bonding regions 806 and 808, respectively. In still other embodiments, another metal layer of bonding material different from bonding material of bonding regions 806 and 808 is further formed on bonding regions 806 and 808 for eutectic bonding, but metal layers 406 and 408 of fig. 8B are omitted, the same as or similar to fig. 8B. An embodiment is shown in fig. 8C, where Sn layers 406 'and 408' are electroplated onto bonding areas 806 and 808, respectively, and the bonding areas of the sensing substrate 104 include only metal layers 402 and 404.
Thereafter, bonding regions 402 'and 404' (or metal layers 402 and 404 of fig. 8C) of ESOI substrate 102 contact bonding regions 806 and 808 through openings 802 and 804 of CMOS wafer 106. During the bonding process, the ESOI substrate 102 and CMOS wafer 106 are heated, and as the temperature increases, a process force is applied to press the ESOI substrate 102 and CMOS wafer 106 toward each other. In other words, the bonding interface between the ESOI substrate 102 and the CMOS wafer 106 is heated and pressed to reflow the metals contained in the bonding regions 402 'and 404' (or metal layers 402 and 404 of fig. 8C) and the corresponding bonding regions 806 and 808 (metal layers 406 'and 408' of fig. 8B and 8C) of the CMOS wafer 106. The pressing force is applied on the ESOI substrate 102 against the CMOS wafer 106 and/or on the CMOS wafer 106 against the ESOI substrate 102, thus creating a seal.
Reflow of the metal results in a fused bond structure that provides an ohmic contact between the ESOI substrate 102 and the CMOS wafer 106. In the illustrated embodiment, the bond between the ESOI substrate and the CMOS wafer 106 comprises a Cu-Sn eutectic bond. This eliminates the need to provide separate electrical paths for signals between the sensing substrate and the CMOS wafer 106. Eutectic reactions are at the triple point in the figure, where the solid alloy mixture transforms directly into the liquid phase. The eutectic melting temperature of Cu-Sn bonding is about 231 degrees celsius, and the bonding temperature provided during the eutectic bonding process may be higher than the eutectic temperature in order to ensure proper or sufficient eutectic reaction of Cu-Sn. In this embodiment, the bonding temperature provided during the eutectic bonding process may range from about 240 degrees celsius to about 300 degrees celsius with a pressing force per unit area of about 1MPa to about 2MP or less. However, this is not a limitation of the present invention.
The disclosed Cu-Sn eutectic bonding has a lower bonding temperature and a lower bonding pressure by using Cu-Sn eutectic bonding, compared to existing eutectic bonding. In particular, some existing eutectic bonds include Au-In bonds, Au-Sn bonds, Au-Ge bonds, Au-Si bonds, and Al-Ge bonds, which all require high bonding temperatures. Au-Sn bonding has a eutectic melting temperature of about 280 degrees celsius, and the required bonding temperature ranges from about 280 degrees celsius to about 310 degrees celsius. The Au-Ge bond has a eutectic melting temperature of about 361 degrees celsius and the required bonding temperature range is about 380 degrees celsius to about 400 degrees celsius. The Au-Si bonding has a eutectic melting temperature of about 363 degrees celsius and the required bonding temperature range is about 390 degrees celsius to about 415 degrees celsius. The Al-Ge bond has a eutectic melting temperature of about 419 degrees celsius and the desired bonding temperature range is about 430 degrees celsius to about 450 degrees celsius.
Although the eutectic melting temperature of the Au-In bond is about 156 degrees celsius and the required bonding temperature range is about 180 degrees celsius to about 210 degrees celsius, it is no higher than the disclosed Cu-Sn bond. However, Au-In bonding is considered incompatible with standard CMOS processes. Further, Au-In bonding, Au-Sn bonding, Au-Ge bonding, Au-Si bonding, and Al-Ge bonding all have a pressing force higher than about 10MPa per unit area, which becomes inapplicable when the technology shrinks.
After cooling, a microstructure is formed, which is robust and hermetic, as shown in fig. 9. Eutectic metal compositions have several benefits as sealing materials, including the ability to properly deposit and define the metal in the desired pattern, resistance to surface deviations, roughness and particles, plus the inherent hermeticity and conductivity of the metal. Since the mechanical and electrical functions of the devices within the package typically rely on critical environmental controls, hermeticity, i.e., the degree of hermeticity of the container or package, is useful for MEMS packaging. Variations in air pressure inside the package can cause performance drift or even overall failure of the device.
With respect to the embodiment of the architecture of fig. 8A, alloy 1006 of fig. 9 is formed by metal layer 406 and at least a portion of metal layers 402 and 806; and similarly, an alloy 1008 is formed by metal layer 408 and at least a portion of metal layers 404 and 808. With respect to the embodiment of the architecture of fig. 8B, the alloy 1006 of fig. 9 is formed by at least a portion of the metal layers 406, 406' and the metal layers 402 and 806; and similarly, an alloy 1008 is formed by at least a portion of metal layers 408, 408' and metal layers 404 and 808. For the embodiment of the architecture of fig. 8C, alloy 1006 of fig. 9 is formed by metal layer 406' and at least a portion of metal layers 402 and 806; and similarly, an alloy 1008 is formed by metal layer 408' and at least a portion of metal layers 404 and 808. In particular, the metal layers 406, 408, 406', and 408' are substantially fully reactive with the upper or lower metal layers 402, 404, 802, and 804.
In the illustrated embodiment, alloys 1006 and 1008 comprise Cu3Sn. It is acceptable that some unreacted Cu remains after bonding. However, it is undesirable to leave any unreacted Sn after bonding because Sn is more noble than Cu and Cu3Sn is less stable. To completely consume Sn in the metal layers 406, 408, 406', and 408', the thickness of the metal layers 406, 408, 406', and 408' may be predetermined according to the thickness of the metal layers 402, 404, 802, and 804 above or below the metal layers 406, 408, 406', and 408'.
In the subsequent step, a pad opening step (pad opening step) is performed. For example, in an etching step or a grinding step, portions 902 and 904 of the cover substrate 101 are removed, as shown in fig. 10. The resulting structure is shown in fig. 11. Thus, the pads 1002 and 1004 in the CMOS substrate 106 are no longer covered by the ESOI substrate 102. The pads 1002 and 1004 are exposed from the CMOS substrate 106 to receive external bonding or wire bonding. In some embodiments, the etch is an anisotropic etch, such that the edge of the cover substrate 101 of fig. 11 is substantially straight. Alternatively, portions 902 and 904 may be removed by a grinding step, wherein portions 902 and 904 are cleaned away using a grinding wheel or knife. In some embodiments, prior to completion of forming the MEMS device including the package, grinding and/or other thinning processes may be used to thin the sensing substrate 104 to a desired thickness.
The present invention provides improved bonding methods for producing Wafer Level Packages (WLPs) that have been widely used in three-dimensional (3D) ICs, Chip Scale Packages (CSPs), and MEMS device combinations. However, the disclosed bonding and related methods are not limited to WLP or 3D ICs, CSP, and MEMS devices. The disclosed bonding process can be integrated into a standard CMOS process, thus resulting in a simplified, low cost solution. Compared with the existing eutectic bonding, the disclosed Cu-Sn eutectic bonding has lower bonding temperature and lower bonding pressing force by using the Cu-Sn eutectic bonding.
Some embodiments of the invention provide packaging methods. The packaging method comprises providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate comprises a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate comprises a third bonding metal layer; and bonding the first semiconductor substrate to the second semiconductor substrate by contacting the bonding region of the first semiconductor substrate to the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers comprise copper (Cu) and the second bonding metal layer comprises tin (Sn).
Some embodiments of the invention provide a packaging method. The packaging method comprises providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate comprises a first bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate comprises a second bonding layer; bonding the bonding region of the first semiconductor substrate and the bonding region of the second semiconductor substrate by using an auxiliary bonding metal; and applying a pressing force of about 1MPa to about 2MPa or less per unit area so that the first and second semiconductor substrates are pressed toward each other.
Some embodiments of the invention provide a package structure. The package structure includes a first semiconductor substrate having a first bonding region thereon; and a second semiconductor substrate having a second bonding region thereon; wherein the first bonding region is bonded to the second bonding region, and a bonding interface between the first and second bonding regions comprises Cu3Sn。
The foregoing outlines some features of embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Description of the symbols
101 cover substrate
102 ESOI substrate
103 thin dielectric film
104 inductive substrate
106 CMOS wafer
112 cavity
302 metal layer
304 metal layer
402 metal layer
402' junction region
404 metal layer
404' junction region
406 metal layer
406' Metal layer
408 metal layer
408' Metal layer
502 engaging protrusion
504 engaging protrusion
802 opening
804 opening
806 bonding region
808 zone of joinder
810 top dielectric layer
812 substrate
814 CMOS device
816 interconnect structures
902 cover a portion of the substrate
904 cover portions of the substrate
1006 alloy
1008 alloy.