External RC frequency adjustable oscillator
阅读说明：本技术 一种外部rc频率可调振荡器 (External RC frequency adjustable oscillator ) 是由 吴益民 熊辉涛 王鹏飞 于 2019-11-05 设计创作，主要内容包括：本发明涉及振荡器中的一种外部RC频率可调振荡器,包括参考电压产生电路1、充电电路；2、放电电路；3、时钟处理电路；4、参考电压产生电路1用于生成并输出参考电压信号,放电电路3用于把电容C2上的电荷泄放掉；放电电路3包含有比较器,充电电路2包含有电容C2,电容C2上的电压直接反馈给比较器的正向输入端；时钟处理电路4用于增强输出的驱动与整形。该振荡器输出频率范围宽、结构简单、面积小、使用方便灵活,广泛应用于MCU等需要时钟的电子产品中。(The invention relates to an external RC frequency adjustable oscillator in oscillators, which comprises a reference voltage generating circuit 1 and a charging circuit; 2. a discharge circuit; 3. a clock processing circuit; 4. the reference voltage generating circuit 1 is used for generating and outputting a reference voltage signal, and the discharging circuit 3 is used for discharging the charge on the capacitor C2; the discharging circuit 3 comprises a comparator, the charging circuit 2 comprises a capacitor C2, and the voltage on the capacitor C2 is directly fed back to the positive input end of the comparator; clock processing circuit 4 is used to enhance the driving and shaping of the output. The oscillator has the advantages of wide output frequency range, simple structure, small area, convenient and flexible use, and is widely applied to electronic products such as MCU (microprogrammed control Unit) and the like which need clocks.)
1. An external RC frequency tunable oscillator, comprising: the device comprises a reference voltage generating circuit 1, a charging circuit 2, a discharging circuit 3 and a clock processing circuit 4, wherein the output end of the charging circuit 2 is connected with the input end of the discharging circuit 3, and the output end of the discharging circuit 3 is connected with the input end of the clock processing circuit 4; wherein the content of the first and second substances,
the reference voltage generating circuit 1 is connected with the discharging circuit 3 and is used for generating and outputting a reference voltage signal;
the discharge circuit 3 is used for discharging the charge on the capacitor C2; the discharge circuit 3 comprises a comparator I1, a schmitt trigger I2, a fifth inverter I3, a sixth inverter I10, and a second MOS transistor M2;
the charging circuit 2 comprises a resistor R4 and a capacitor C2, and the voltage on the capacitor C2 is directly fed back to the positive input end of the comparator;
the clock processing circuit 4 is used for enhancing the driving capability and waveform shaping of the output, and the clock processing circuit 4 comprises a D flip-flop I5 and a plurality of inverters; the D port and the QB port of the D trigger I5 are electrically connected, the first inverter I6 is sequentially connected with the second inverter I7, the third inverter I8 and the fourth inverter I9 in series, and the input end of the first inverter I6 is connected with the signal output end of the D trigger I5.
2. An external RC frequency tunable oscillator as claimed in claim 1, wherein: the reference voltage generating circuit 1 comprises a first MOS tube, one end of the first MOS tube is connected with an external power supply VDD5, the other end of the first MOS tube is connected with a resistor R1, the resistor R1 is connected with a resistor R3 through a resistor R2, the other end of the resistor R3 is grounded, and a capacitor C1 is connected to two ends of the resistor R3 in parallel; when the first MOS tube is conducted, the resistor divides voltage to obtain a voltage which is about one third of the power supply voltage and is used as the reference voltage VREF of the comparator, and the capacitor C1 is a voltage stabilizing capacitor of the reference voltage and is mainly used for filtering noise interference on the power supply voltage.
3. An external RC frequency tunable oscillator as claimed in claim 1, wherein: the charging circuit 2 is composed of an off-chip resistor R4 and a capacitor C2, one end of the resistor R4 is connected with a power supply, the other end of the resistor R4 is connected with the capacitor C2, the other end of the capacitor C2 is connected with the ground, and the connection position of the resistor and the capacitor is connected to the positive input end F of the comparator.
4. An external RC frequency tunable oscillator as claimed in claim 1, wherein: the discharge circuit 3 comprises a second MOS tube, a comparator I1, a Schmitt trigger I2 and a plurality of phase inverters; the source electrode of the second MOS tube is connected with the ground, the drain electrode of the second MOS tube is connected with the positive input end F of a comparator, the output end of the comparator I1 is connected with the input end of a Schmitt trigger I2, the output end of the Schmitt trigger I2 is connected with the input end of a fifth inverter I3, the output end of the fifth inverter I3 is connected with the input end of a sixth inverter I10, and the output end of the sixth inverter I10 is connected with the gate electrode of the second MOS tube; when the comparator outputs a low level, the second MOS transistor is turned off, and when the comparator outputs a high level, the second MOS transistor is turned on, and the charge on the capacitor C2 is discharged through the turned-on second MOS transistor.
5. An external RC frequency tunable oscillator as claimed in any one of claims 1 to 5, wherein: when the enable signal EN is high, the oscillator starts to operate.
Technical Field
The invention relates to the field of oscillators, in particular to an oscillator with adjustable external RC frequency.
Background
In conventional applications, the oscillator circuit is implemented by an internal RC circuit and a crystal oscillator circuit. The internal RC circuit generally overcomes the consistency problem among different chips through a correction circuit, and utilizes temperature compensation to solve the temperature drift problem, and also corrects the clock through a precise clock such as a crystal oscillator circuit to detect the clock in real time to improve the accuracy of the chip.
Through retrieval, the patent application number 201821763559.X patent name is a frequency-adjustable RC oscillator, which comprises a code system conversion module, a bias module, a switching current control module, a comparator and an output control module. According to the invention, the frequency selection signal is converted into a binary current control bit code through the code system conversion module, the charging and discharging current is changed through the switch current control module, and finally, the charging and discharging voltage is compared with the reference voltage provided by the bias module, so that the periodic square wave given by the product number selection signal is obtained.
However, the RC circuit inside the oscillator often has a large temperature drift, which causes a decrease in accuracy, and the frequency is not stable enough, resulting in poor consistency.
In the existing scheme, the problem of consistency among different chips is solved through a correction circuit, and the temperature drift problem is solved by using temperature compensation, but the structures of the correction circuits are often complex, and the matching performance of the temperature compensation circuit is poor.
Although the crystal oscillator has the advantages of small clock jitter, small temperature drift, stable frequency and the like, the frequency of the crystal oscillator is relatively single, and the production cost is high.
Disclosure of Invention
In order to solve the problems, the invention provides an external RC frequency adjustable oscillator which has a simple structure, a small area and a wide frequency range.
In order to achieve the purpose, the invention adopts the technical scheme that:
an external RC frequency tunable oscillator, comprising: the device comprises a reference
the reference
the discharge circuit 3 is used for discharging the charge on the capacitor C2; the discharge circuit 3 comprises a comparator I1, a schmitt trigger I2, a fifth inverter I3, a sixth inverter I10, and a second MOS transistor M2;
the
the clock processing circuit 4 is used for enhancing the driving capability and waveform shaping of the output, and the clock processing circuit 4 comprises a D flip-flop I5 and a plurality of inverters; the D port and the QB port of the D trigger I5 are electrically connected, the first inverter I6 is sequentially connected with the second inverter I7, the third inverter I8 and the fourth inverter I9 in series, and the input end of the first inverter I6 is connected with the signal output end of the D trigger I5.
As a further elaboration of the above technical solution:
in the above technical solution, the reference
In the above technical solution, the
In the above technical solution, the discharge circuit 3 includes a second MOS transistor, a comparator I1, a schmitt trigger I2, and a plurality of inverters; the source electrode of the second MOS tube is connected with the ground, the drain electrode of the second MOS tube is connected with the positive input end F of a comparator, the output end of the comparator I1 is connected with the input end of a Schmitt trigger I2, the output end of the Schmitt trigger I2 is connected with the input end of a fifth inverter I3, the output end of the fifth inverter I3 is connected with the input end of a sixth inverter I10, and the output end of the sixth inverter I10 is connected with the gate electrode of the second MOS tube; when the comparator outputs a low level, the second MOS transistor is turned off, and when the comparator outputs a high level, the second MOS transistor is turned on, and the charge on the capacitor C2 is discharged through the turned-on second MOS transistor.
The invention has the beneficial effects that: the invention comprises a reference voltage generating circuit, a charging circuit, a discharging circuit and a clock shaping circuit. Wherein: the reference voltage is obtained by dividing voltage through resistors, the charging circuit is connected with corresponding resistors and capacitors outside the chip according to actual needs, one end of each resistor is connected with a power supply, and the other end of each resistor is connected with the corresponding capacitor. One end of the capacitor is connected with the resistor, and the other end of the capacitor is connected with the ground. The junction of the resistor and the capacitor is connected to the positive input F of the comparator. When the enable signal EN is high, the oscillator starts to operate. The 1 st MOS tube is conducted, and the resistance voltage division obtains a voltage which is about one third of the power supply voltage and is used as the reference voltage VREF of the comparator. The external power supply VDD5 charges an external capacitor through a resistor, and when the voltage on the capacitor, i.e., the voltage at the positive-phase input end of the comparator, is less than the reference input voltage of the comparator, i.e., the voltage at the negative-phase input end, the comparator inputs a low level, and at this time, the gate terminal of the second MOS transistor is at a low level, and the MOS transistor is in an off state. Along with the increase of the charging time, the electric charge on the capacitor is more and more, the voltage is higher and higher, when the voltage on the capacitor, namely the voltage of the positive phase input end of the comparator is greater than the reference input voltage of the comparator, the output of the comparator is high level, at the moment, the grid end of the second MOS tube is high level, the second MOS tube is in a conducting state, and the electric charge on the capacitor is discharged through the conducting second MOS tube. Because the on-resistance of the second MOS tube is very small, the discharging current is far greater than the charging current, the charge on the capacitor is rapidly discharged, and the voltage on the capacitor can rapidly drop. At the moment, the voltage on the external capacitor is smaller than the reference voltage of the comparator, the comparator outputs a low level, the grid end of the second MOS tube becomes a low level and is in a turn-off state, the power supply charges the capacitor through the external resistor, the voltage on the capacitor gradually rises along with the lapse of charging time, when the voltage on the capacitor is larger than the reference input voltage of the comparator, the comparator outputs a high level, and in this way, the comparator continuously outputs high and low levels, and a square wave with a duty ratio of 50% can be obtained after shaping.
Therefore, the charging time of the charging circuit can be changed by connecting resistors with different resistance values and capacitors with different capacitance values outside the chip, and the frequency of the clock can be further changed, wherein the frequency range of the clock is from 100HZ to 10 MHZ. The oscillator has the advantages of wide output frequency range, simple structure, small area, convenient and flexible use, and is widely applied to electronic products such as MCU (microprogrammed control Unit) and the like which need clocks.
Drawings
Fig. 1 is a circuit configuration diagram of the present invention.
Fig. 2 is a circuit schematic of the present invention.
Fig. 3 is a graph of the variation of the output 5M clock with power supply of the present invention.
Fig. 4 is a graph of the output 5M clock of the present invention as a function of temperature.
The reference numbers illustrate: 1. a reference voltage generating circuit; 2. a charging circuit; 3. a discharge circuit; 4. a clock processing circuit.
Detailed Description
Fig. 1 to 4 are specific embodiments of an external RC frequency tunable oscillator according to the present invention, and referring to fig. 1 to 4, an external RC frequency tunable oscillator includes a reference
the reference
the discharge circuit 3 is used for discharging the charge on the capacitor C2; the discharge circuit 3 comprises a comparator I1, a schmitt trigger I2, a fifth inverter I3, a sixth inverter I10, and a second MOS transistor M2;
the
the clock processing circuit 4 is used for enhancing the driving capability and waveform shaping of the output, and the clock processing circuit 4 comprises a D flip-flop I5 and a plurality of inverters; the D port and the QB port of the D trigger I5 are electrically connected, the first inverter I6 is sequentially connected with the second inverter I7, the third inverter I8 and the fourth inverter I9 in series, and the input end of the first inverter I6 is connected with the signal output end of the D trigger I5.
As a further elaboration of the above technical solution:
in this embodiment, the reference
In this embodiment, the
In this embodiment, the discharge circuit 3 includes a second MOS transistor, a comparator I1, a schmitt trigger I2, and several inverters; the source electrode of the second MOS tube is connected with the ground, the drain electrode of the second MOS tube is connected with the positive input end F of a comparator, the output end of the comparator I1 is connected with the input end of a Schmitt trigger I2, the output end of the Schmitt trigger I2 is connected with the input end of a fifth inverter I3, the output end of the fifth inverter I3 is connected with the input end of a sixth inverter I10, and the output end of the sixth inverter I10 is connected with the gate electrode of the second MOS tube; when the comparator outputs a low level, the second MOS transistor is turned off, and when the comparator outputs a high level, the second MOS transistor is turned on, and the charge on the capacitor C2 is discharged through the turned-on second MOS transistor.
Specifically, when En is at a high level, ENB is at a low level, the first MOS transistor in the reference voltage generation circuit is turned on, the first MOS transistor is used as a control switch, the designed on-resistance value is small, and the power supply obtains a voltage after resistance voltage division as a reference voltage of the comparator, which is about 1/3 of the power supply. The capacitor C1 is a voltage stabilizing capacitor for the reference voltage, and mainly filters noise interference on the power supply voltage.
The power supply VDD5 charges an external capacitor through a chip external resistor, the voltage on the external capacitor is smaller than the reference voltage of the comparator when the external capacitor starts to charge, the output of the comparator is at a low level, the grid end of the second MOS tube is at the low level, and the second MOS tube is closed. The voltage on the external capacitor is higher and higher along with the charging time, when the voltage on the capacitor is larger than the reference voltage of the comparator, the output state of the comparator is changed to be changed from low level to high level, once the output of the comparator is changed to be high level, the gate voltage of the second MOS tube is changed to be high level, the second MOS tube is conducted, and the charges on the capacitor are discharged to the ground through the conducted second MOS tube.
Because the on-resistance of the second MOS tube is very small, the discharge current is far larger than the charge current, and the electric quantity on the capacitor is rapidly reduced to a value close to 0. The voltage drop on the external capacitor enables the voltage of the positive phase input end of the comparator to be smaller than that of the negative phase input end, the output state of the comparator changes from high level output to low level output, the grid end voltage of the second MOS tube changes from high level to low level, and the second MOS tube is cut off. At the moment, the external capacitor only has charging current and does not have discharging current, the voltage on the capacitor is gradually increased and the charging is restarted, so that the external capacitor is periodically charged and discharged, the periodically output high and low levels of the comparator are square waves, and the square waves are shaped by the D trigger to generate square waves with the duty ratio of 50%.
Further, the oscillator output CLK is also a 50% square wave with a duty cycle. The clock cycle of charging and discharging is composed of three parts of charging time T1, discharging time T2 and response time T3 of the comparator, wherein T is T1+ T2+ T3. The response time t2 of the comparator is much shorter than the charging time t1, and the discharging time t3 is much shorter than the charging time t1, so the clock frequency is mainly determined by the
From the expression of the clock frequency, the output frequency of the oscillator is only related to the resistance value of the resistor and the capacitance value of the capacitor, i.e. the accuracy of the clock is mainly determined by the accuracy of the resistor and the capacitor. The oscillator can select resistors and capacitors with different accuracies according to different requirements in practical application.
In the present embodiment, fig. 3 shows that the clock frequency decreases as the power supply VDD5 increases when the oscillator outputs 5M; fig. 4 shows that the clock frequency increases with increasing temperature when the oscillator outputs 5M.
The above embodiments are merely illustrative of the preferred embodiments of the present invention, and not restrictive, and various changes and modifications to the technical solutions of the present invention may be made by those skilled in the art without departing from the spirit of the present invention, and the technical solutions of the present invention are intended to fall within the scope of the present invention defined by the appended claims.