阅读说明：本技术 用于高效互补金属氧化物半导体(cmos)功率放大器的偏置电路 (Bias circuit for high efficiency Complementary Metal Oxide Semiconductor (CMOS) power amplifier ) 是由 M·M·R·艾斯梅尔 M·A·Y·阿布达拉 于 2019-07-23 设计创作，主要内容包括：本公开的各方面涉及用于功率放大器的自适应偏置电路。自适应偏置电路可包括分流电阻器布置和/或浮栅线性化器布置。(Aspects of the present disclosure relate to an adaptive bias circuit for a power amplifier. The adaptive bias circuit may include a shunt resistor arrangement and/or a floating gate linearizer arrangement.)

1. A bias circuit for a power amplifier to enhance linearization of a bias ramp of the power amplifier, the bias circuit comprising:

a Field Effect Transistor (FET);

a linearizer arrangement configured to float a gate terminal of the FET to generate a bias signal having a quadratic slope; and

a resistor arrangement electrically connected in parallel with the linearizer arrangement, the resistor arrangement configured to add a linear term to the bias signal, wherein the linearizer arrangement and the resistor arrangement are configured to provide a bias signal at an input of the power amplifier.

2. The biasing circuit of claim 1, wherein the resistor arrangement is a shunt resistor arrangement including a first resistor, wherein a first end of the first resistor is electrically connected to a first node, the first node being electrically connected to the input of the power amplifier.

3. The bias circuit of claim 2, wherein the second end of the first resistor is electrically connected to a first voltage source.

4. The biasing circuit of claim 2, wherein the first node is further electrically connected to an alternating current power source.

5. The biasing circuit of claim 4, wherein the biasing circuit increases the amplitude of the bias signal of the power amplifier during negative half cycles of the AC power source, and wherein the biasing circuit increases or approximately maintains the amplitude of the bias signal of the power amplifier during positive half cycles of the AC power source.

6. The bias circuit of claim 2, wherein the linearizer arrangement is a floating gate linearizer arrangement comprising a FET, wherein the FET comprises a first terminal, a second terminal, and a gate terminal, wherein the gate terminal is electrically connected to the first end of the second resistor, and wherein the first node is also electrically connected to the first terminal of the FET.

7. The biasing circuit of claim 6, wherein the second node is electrically connected to the second terminal of the FET, the first end of the capacitor, and the first end of the third resistor.

8. The bias circuit of claim 7, wherein the second end of the first resistor is electrically connected to a first voltage source, a second voltage source is electrically connected to the second end of the second resistor, and a third voltage source is electrically connected to the second end of the third resistor, and wherein the first voltage source, the second voltage source, and the third voltage source are different.

9. The bias circuit of claim 8, wherein values of the first voltage source, the second voltage source, and the third voltage source are based on a selected power amplifier class.

10. The bias circuit of claim 9, wherein a value of at least one of the first resistor, the second resistor, the third resistor, the capacitor, or the FET is based on the selected power amplifier class.

11. The bias circuit of claim 7, wherein the second end of the first resistor is electrically connected to a first voltage source, a second voltage source is electrically connected to the second end of the second resistor, and a third voltage source is electrically connected to the second end of the third resistor, and wherein at least two of the first voltage source, the second voltage source, and the third voltage source are connected.

12. The biasing circuit of claim 7, wherein the second end of the capacitor is electrically connected to ground.

13. The bias circuit of claim 1, wherein the power amplifier is a CMOS power amplifier.

14. A bias circuit for a power amplifier to control a bias ramp of the power amplifier, wherein the bias circuit comprises a linearizer arrangement electrically connected to an input of the power amplifier in parallel with a MOSFET, the linearizer arrangement being configured to enhance the linearity of the bias ramp of the power amplifier.

15. The bias circuit of claim 14, wherein the linearizer arrangement is a floating gate linearizer comprising a first FET, wherein the first FET comprises a first terminal, a second terminal, and a gate terminal, wherein the gate terminal is electrically connected to a first end of a second resistor, and wherein the first node is electrically connected to the input of the power amplifier, the first terminal of the first FET, and the alternating current power supply.

16. The biasing circuit of claim 15, wherein current propagates from the second terminal to the first terminal of the first FET during negative half-cycles of the ac power source, and current propagates from the first terminal to the second terminal of the first FET during positive half-cycles of the ac power source.

17. The biasing circuit of claim 15, wherein the linearizer arrangement further comprises a second FET connected in parallel with the first FET.

18. The biasing circuit of claim 14, wherein the biasing circuit decreases the amplitude of the input of the power amplifier during negative half cycles of the ac power source, and wherein the biasing circuit increases the amplitude of the input of the power amplifier during positive half cycles of the ac power source.

19. A bias circuit for a power amplifier to control a bias ramp of the power amplifier, wherein the bias circuit comprises a resistor arrangement configured to enhance linearity of the bias ramp of the power amplifier.

20. The biasing circuit of claim 19, wherein the resistor arrangement is a shunt resistor arrangement including a first resistor, wherein a first end of the first resistor is electrically connected to a first node, the first node being electrically connected to the input of the power amplifier.

Technical Field

The present disclosure relates to electronic devices, and more particularly to bias circuits for power amplifiers.

Background

Wireless technology continues to emerge as transistors scale, digital signal processing, and transceiver architectures suitable for silicon integration advance. Wireless transceivers have become ubiquitous, integrating into cell phones, notebook computers, game consoles, global positioning systems, medical devices, satellite communications, radio and television transmitters, radio frequency power heating, and a wide variety of consumer electronics. This success is largely attributed to advances in semiconductor technology, particularly CMOS technology.

Disclosure of Invention

The innovations described in the claims each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims, some of the salient features of the disclosure will now be briefly described.

In some embodiments, a bias circuit is provided, disclosing: a Field Effect Transistor (FET); a linearizer arrangement configured to float a gate terminal of the FET to generate a bias signal having a quadratic slope; and a resistor arrangement electrically connected in parallel with the linearizer arrangement, wherein the resistor arrangement is configured to add a linear term to a bias circuit ramp, and wherein the linearizer arrangement and the resistor arrangement are configured to provide a bias signal at an input of the power amplifier to improve the efficiency of the power amplifier.

In some embodiments, the resistor arrangement is a shunt resistor arrangement comprising a first resistor, wherein a first end of the first resistor is electrically connected to a first node, the first node being electrically connected to the input of the power amplifier.

In some embodiments, the second end of the first resistor is electrically connected to a first voltage source.

In some embodiments, the first node is also electrically connected to an ac power source.

In some embodiments, a bias circuit increases a magnitude of an input bias of the power amplifier during negative half cycles of the ac power source, and wherein the bias circuit increases or maintains the same magnitude of the input bias of the power amplifier during positive half cycles of the ac power source.

In some embodiments, the linearizer arrangement is a floating gate linearizer arrangement comprising a FET, wherein the FET comprises a first terminal, a second terminal, and a gate terminal. The gate terminal is electrically connected to a first end of the second resistor, and the first node is also electrically connected to a first terminal of the FET.

In some embodiments, the second node is electrically connected to the second terminal of the FET, the first end of the capacitor, and the first end of the third resistor.

In some embodiments, the second end of the first resistor is electrically connected to a first voltage source, a second voltage source is electrically connected to the second end of the second resistor, a third voltage source is electrically connected to the second end of the third resistor, and the first voltage source, the second voltage source, and the third voltage source are different.

In some embodiments, the values of the first voltage source, the second voltage source, and the third voltage source are based on the selected power amplifier class.

In some embodiments, the value of at least one of the first resistor, the second resistor, the third resistor, the capacitor, or the FET is based on the selected power amplifier class.

In some embodiments, the second end of the first resistor is electrically connected to a first voltage source, a second voltage source is electrically connected to the second end of the second resistor, a third voltage source is electrically connected to the second end of the third resistor, and at least two of the first voltage source, the second voltage source, and the third voltage source are connected.

In some embodiments, the second terminal of the capacitor is electrically connected to ground.

In some embodiments, the power amplifier is a CMOS power amplifier.

In some embodiments, there is provided a bias circuit for a power amplifier to control a bias ramp of the power amplifier, disclosing: a linearizer arrangement electrically connected to an input of the power amplifier in parallel with the MOSFET, wherein the linearizer arrangement is configured to enhance linearity of a bias ramp of the power amplifier.

In some embodiments, the linearizer arrangement is a floating gate linearizer comprising a first FET, wherein the first FET comprises a first terminal, a second terminal, and a gate terminal, wherein the gate terminal is electrically connected to a first end of a second resistor, and a first node is electrically connected to the input of the power amplifier, the first terminal of the first FET, and the alternating current power source.

In some embodiments, current propagates from the second terminal to the first terminal of the first FET during negative half-cycles of the ac power source, and current propagates from the first terminal to the second terminal of the first FET during positive half-cycles of the ac power source.

In some embodiments, a bias circuit reduces the amplitude of the input to the power amplifier during negative half cycles of the ac power source, and wherein the bias circuit increases the amplitude of the input to the power amplifier during positive half cycles of the ac power source.

In some embodiments, there is provided a bias circuit for a power amplifier to control a bias ramp of the power amplifier, disclosing: a resistor arrangement configured to enhance linearity of a bias ramp of the power amplifier.

In some embodiments, the resistor arrangement is a shunt resistor arrangement comprising a first resistor, wherein a first end of the first resistor is electrically connected to a first node, and the first node is electrically connected to an input of the power amplifier.

In some embodiments, the linearizer arrangement further comprises a second FET connected in parallel with the first FET.

For the purposes of summarizing the disclosure, certain aspects, advantages, and novel features of the invention have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment. Thus, the innovations may be implemented or performed in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.

Drawings

Embodiments of the present disclosure will now be described by way of non-limiting examples with reference to the accompanying drawings.

Fig. 1A is a schematic diagram of a conventional bipolar-based diode linearizer and one-to-one CMOS implementation thereof, according to one embodiment.

Fig. 1B is a schematic diagram of a 2-stage CMOS power amplifier according to one embodiment, where stage 1 does not employ linearization and stage 2 employs a conventional CMOS diode-connected linearization circuit.

Figure 2A is a CMOS power amplifier with a class a bias circuit (wireless) according to one embodiment.

Fig. 2B is a schematic diagram of a CMOS power amplifier with a diode linearizer, according to one embodiment.

Fig. 2C is a schematic diagram of a CMOS power amplifier with a bias circuit according to one embodiment.

Fig. 3A is a schematic diagram of a CMOS power amplifier with a shunt resistor arrangement and a bias circuit according to one embodiment.

Figure 3B is a schematic diagram of a CMOS power amplifier with a floating gate linearizer arrangement, according to one embodiment.

Figure 3C is a block diagram of a CMOS power amplifier with a shunt resistor arrangement and a floating gate linearizer arrangement in accordance with one embodiment.

Figure 3D is a schematic diagram of a floating gate linearizer arrangement, a CMOS power amplifier, and a shunt resistor arrangement, according to one embodiment.

Figure 3E is a schematic diagram of a CMOS power amplifier with a shunt resistor arrangement and a floating gate linearizer arrangement for high power applications, according to one embodiment.

Figure 4 is a graph of voltage bias for a CMOS power amplifier with a shunt resistor arrangement and a floating gate linearizer arrangement in accordance with one embodiment.

Fig. 5A is a diagram of a CMOS power amplifier with a shunt resistor arrangement and a floating gate linearizer arrangement during negative voltage periods, according to one embodiment.

Fig. 5B is a diagram of a CMOS power amplifier with a shunt resistor arrangement and a floating gate linearizer arrangement during a positive voltage period, according to one embodiment.

Figure 6A is an analog test bench for a CMOS power amplifier without an adaptive bias circuit according to one embodiment.

Figure 6B is an analog test bench of a CMOS power amplifier with adaptive bias circuits according to one embodiment.

Fig. 7A is a graph of gain versus output power, according to one embodiment.

Fig. 7B is a graph of power amplifier efficiency versus output power, according to one embodiment.

FIG. 7C is a graph of current consumption versus output power according to one embodiment

Fig. 8A is a graph of AM-AM distortion versus output power, according to one embodiment.

Fig. 8B is a graph of AM-PM distortion versus output power, according to one embodiment.

Fig. 9 is a diagram of output intercept point OIP3 versus output power, according to one embodiment.

Fig. 10 is a detailed schematic diagram of a differential 3-layer stacked class a CMOS power amplifier without new adaptive bias circuitry (wireless) according to one embodiment.

Fig. 11 is a detailed schematic diagram of a differential 3-layer stacked class AB CMOS power amplifier with a new adaptive bias circuit, according to one embodiment.

Fig. 12A is a graph of output P1dB compression point versus RF frequency according to one embodiment.

Fig. 12B is a graph of power amplifier efficiency versus output power, according to one embodiment.

Fig. 13 is a diagram of output intercept point OIP3 versus output power, according to one embodiment.

Fig. 14A is a graph of intermodulation distortion, IM3, versus output power using different tone spacing of two-tone signals, according to one embodiment.

Fig. 14B is a graph of third intercept point OIP3 versus output power using different tone spacing of a two-tone signal, according to an embodiment.

Fig. 15A is a graph of AM-AM distortion versus output power at approximately 28GHz, according to one embodiment.

Fig. 15B is a graph of AM-PM distortion versus output power at approximately 28GHz, according to one embodiment.

Fig. 15C is a graph of current versus output power at approximately 28GHz, according to one embodiment.

Fig. 16A is a graph of AM-AM distortion versus output power at approximately 28GHz, according to one embodiment.

Fig. 16B is a graph of AM to PM distortion versus output power at approximately 38GHz according to one embodiment.

Fig. 16C is a graph of current versus output power at approximately 38GHz, according to one embodiment.

Fig. 17 is a plot of the S21 parameter (forward voltage gain) versus frequency according to one embodiment.

Detailed Description

The following detailed description of certain embodiments presents various descriptions of specific embodiments. The innovations described herein may, however, be implemented in many different ways, for example, as defined and covered by the claims. In the description, reference is made to the drawings wherein like reference numbers may indicate identical or functionally similar elements. It will be understood that elements shown in the figures have not necessarily been drawn to scale. Further, it should be understood that certain embodiments may include more elements than shown in the figures and/or a subset of the elements shown in the figures. Furthermore, some embodiments may incorporate any suitable combination of features from two or more of the figures. Headings are provided herein for convenience only and do not necessarily affect the scope or meaning of the claims.

In today's wireless communication, a mobile network requires a high data rate and low power consumption. Architectures with power amplifiers are popular in these applications. However, there is a trade-off between efficiency and linearity of the power amplifier. Increasing the efficiency and linearity of a power amplifier may reduce power consumption and may require fewer devices to provide a particular RF output power, thus requiring less overall amplifier footprint. In power amplifiers, it is important to reduce power consumption using low cost solutions.

Systems, apparatus, and methods herein describe a bias circuit that uses a controllable bias network to improve overall efficiency, output power, and linearity of a power amplifier with reliable supply voltage levels. The bias circuit may be applied to a CMOS power amplifier, which may have many benefits such as low cost, high integration, universal calibration, etc. For example, the described bias circuit may be used for a 28nm cmos power amplifier for 5G applications. Such 5G applications may be for a wide frequency band, for example between about 24-44 GHz.

Although the amplification of some CMOS power amplifiers may be high, the conversion efficiency from DC power supply to AC power output is typically low. Although the power amplifier may be driven into its nonlinear region to improve efficiency, this typically results in distortion. Therefore, there is a need to improve the efficiency and output power of CMOS power amplifiers while maintaining high linearity. Another need is to improve the power consumption of power amplifiers.

Power amplifier and linearizer/bias circuit

Fig. 1A and 1B are schematic diagrams of a power amplifier with an integrated diode linearizer. Fig. 1A is a schematic diagram of a conventional bipolar-based diode linearizer and its one-to-one CMOS implementation.

Fig. 1B is a schematic diagram of a 2-stage CMOS power amplifier, where stage 1 does not employ linearization and stage 2 employs a conventional CMOS diode-connected linearization circuit. The power amplifier of fig. 1A and 1B uses an integrated diode by connecting the drain and gate of the NMOS transistor to function as a diode.

Fig. 2A and 2B are schematic diagrams of a CMOS power amplifier. Fig. 2A is a CMOS power amplifier with a class a bias circuit (wireless).

Fig. 2B is a schematic diagram of a CMOS power amplifier with a diode linearizer, e.g., with an additional resistor to bias a CMOS diode connected to the linearizer. A diode-connected NMOS transistor is used as the linearizer.

Fig. 2C is a schematic diagram 300 of a CMOS power amplifier 302 with a bias circuit 301. The bias circuit 301 may comprise a CMOS diode connected linearizer with an RC feedback circuit. The bias circuit may include ground 304, capacitor 306, resistor Rb 2308, MOSFET310, resistor Rb1312, and voltage source 314.

The bias circuit 301 may be connected to an alternating voltage source Vin and an input of the power amplifier 302 via a source of the MOSFET 310. The gate of MOSFET310 may be connected to resistor Rb 2308 and capacitor C306. The other end of the capacitor C306 may be connected to ground 304. The other end of the resistor Rb 2308 may be connected to the drain of the MOSFET310 and the resistor Rb 1312. The other end of the resistor Rb1312 may be connected to a voltage source Vb 1314.

If the input power increases, the bias circuit 301 may increase the bias point at the input of the power amplifier 302. However, for the bias circuit 301, the current is proportional or approximately proportional to the voltage input signal squared, thus resulting in an uncontrolled ramping. For example, an excessive current ramp does not necessarily result in an increase in output power, resulting in a decrease in power amplifier efficiency.

The above-described technique creates an uncontrolled ramp that can affect the efficiency of the power amplifier 302. Uncontrolled ramping further reduces AM-AM distortion and AM-PM distortion, which are important parameters for 5G and beamforming applications. Furthermore, uncontrolled ramping may lead to overdrive conditions, resulting in highly saturated amplifiers, which may affect the temperature of the device and/or lead to device failure.

Overview of novel adaptive bias circuit for power amplifier

Aspects of the present disclosure relate to technical solutions that may mitigate uncontrolled ramping of a power amplifier. Accordingly, aspects of the present invention improve efficiency, linearity, AM-AM distortion, and AM-PM distortion via a bias circuit that adjusts a bias point according to output power in a controlled manner. Therefore, if the system requires high output power, the bias point can be increased by increasing the bias current. If the system requires low output power, the bias current can be reduced to achieve high efficiency and low power consumption. The bias circuit may achieve this performance by controlling the bias ramp of the power amplifier. In some embodiments, such control may be achieved without the use of a controller, which may limit maximum efficiency.

Fig. 3A is a schematic diagram 330 of a CMOS power amplifier 302 with a shunt resistor arrangement 349 and a bias circuit 301, according to some embodiments. The bias circuit 301 may include ground 304, capacitor 306, resistor Rb 2308, MOSFET310, resistor Rb1312, and voltage source 314, as shown in fig. 2C.

The shunt resistor arrangement 349 may include a resistor Rb 3346 and a voltage source Vb 3348. A first end of resistor Rb 3346 may be electrically connected to the input of power amplifier 302 and one of the source or drain of MOSFET 310. A second terminal of resistor Rb 3346 may be electrically connected to a voltage source Vb 3348.

In some implementations, a shunt resistor arrangement 349 adds a linear element to the bias circuit of fig. 2C. Thus, the shunt resistor arrangement 349 adds a linear ramp term to the quadratic term of the MOSFET310, improving the bias ramp of the power amplifier 302. The bias point may be a function of the device and the resistor, thereby creating a non-linear bias circuit and increasing the efficiency of the power amplifier.

Figure 3B is a schematic 360 of CMOS power amplifier 302 with a floating gate linearizer arrangement 369. The schematic 360 as shown in fig. 3B also includes a resistor Rb2370, a voltage source Vb2372, a capacitor 374 and ground 376. The floating gate linearizer arrangement 369 may comprise a MOSFET 340, a resistor Rb 1366, and a voltage source Vb 1364.

The MOSFET 340 may include a first terminal, a second terminal, and a gate. The gate may be connected to a first end of a resistor Rb 1366. A second terminal of resistor Rb 1366 may be connected to voltage source Vb 1364. A first terminal of the MOSFET 340 may be connected to an ac voltage source and an input of the power amplifier 302. A second terminal of MOSFET 340 may be connected to a first end of resistor Rb2370 and a first end of capacitor 374. A second terminal of the resistor Rb2370 may be connected to a voltage source Vb 2372. A second terminal of capacitor 374 may be connected to ground 376. The floating gate linearizer arrangement 369 allows gate swing and gate floating in the linearizer circuit reduces Vgs on the device, which reduces the bias ramp and improves the efficiency of the power amplifier.

Figure 3C is a block diagram 380 of a CMOS power amplifier 302 having a shunt resistor arrangement 349 and a floating gate linearizer arrangement 369 according to some embodiments. Block diagram 380 shown in fig. 3C also includes resistor Rb2370, voltage source Vb2372, capacitor 374, and ground 376. The floating gate linearizer arrangement 369 may comprise a floating gate linearizer arrangement as shown in figure 3B. The shunt resistor arrangement 349 may include a shunt resistor arrangement as shown in fig. 3A.

A shunt resistor arrangement 349 may be provided in parallel with the floating gate linearizer arrangement 369. A first end of the shunt resistor arrangement 349 and a first end of the floating gate linearizer arrangement 369 may be electrically connected to the input of the power amplifier 302 and an alternating voltage source. A second end of the floating gate linearizer arrangement 369 may be connected to a first end of a resistor Rb2370 and a first end of a capacitor C374. A second end of the resistor Rb2370 may be electrically connected to a voltage source Vb 2372. A second terminal of capacitor C374 may be electrically connected to ground 376.

Figure 3D is a schematic diagram 390 of a floating gate linearizer arrangement 369, CMOS power amplifier 302, and shunt resistor arrangement 349. The schematic diagram 390 shown in FIG. 3D also includes a resistor Rb2370, a voltage source Vb2372, a capacitor 374, and ground 376.

The shunt resistor arrangement 349 may include a resistor Rb 3346 and a voltage source Vb 3348, as shown in fig. 3A. The floating gate linearizer arrangement 369 may comprise a MOSFET 340, a resistor Rb 1366, and a voltage source Vb1364, as shown in fig. 3B. The shunt resistor arrangement 349 as shown in figure 3A may be combined with a floating gate linearizer arrangement 369 as shown in figure 3B.

The floating gate linearizer arrangement 369 and the shunt resistor arrangement 349 as shown in figures 3C and 3D add more degrees of freedom to control the biasing of the different operating modes using three voltage sources Vb1364, Vb2372 and Vb 3348. The voltage sources Vb1364, Vb2372, and Vb 3348 may be bias voltages, may be generated using current sources, and may be determined according to the type of bias circuit desired. In some embodiments, two or more voltage sources Vb1364, Vb2372, and Vb 3348 may be connected to each other (e.g., Vb2372 and Vb 3348 connected to each other). The floating gate linearizer arrangement 369 and the shunt resistor arrangement 349 as shown in figures 3C and 3D further add more degrees of freedom by resistors Rb 1366, Rb2370 and Rb 3346, capacitor C374 and MOSFET 368.

The degree of freedom may be varied to change the rank of the power amplifier. For example, changing the Vb 3348 voltage value from a low value to a high value may convert the power amplifier from a class B to a class a power amplifier. Advantageously, the power amplifier may change from a more linear class a amplifier to a more efficient class B amplifier based on the desired application. Other embodiments describe a single voltage source Vb 1314 that can limit the operation of the power amplifier.

Table 1 depicts an illustrative example of how certain parameters of the floating gate linearizer arrangement 369 and the shunt resistor arrangement 349 as shown in fig. 3C and 3D may be determined:

table 1: example parameters of bias circuits

Fig. 3E is a schematic 391 of a CMOS power amplifier 302 with a shunt resistor arrangement 349 and a floating gate linearizer arrangement 369 for high power applications, according to some embodiments. A schematic diagram 391 as shown in fig. 3E includes similar elements to the floating gate linearizer arrangement 369 and the shunt resistor arrangement 349 in fig. 3D, with the addition of a second MOSFET394, a second voltage source Vb 4392 and a resistor Rb 4393. The floating gate linearizer may be configured with one or more MOSFET stacks, e.g., 340 and 394 in series, to further divide the swing across the MOSFETs.

Novel adaptive bias circuit voltage bias enhanced linearization

Figure 4 is a graph of voltage bias for a CMOS power amplifier with a shunt resistor arrangement and a floating gate linearizer arrangement in accordance with some embodiments. The graph illustrates the variation of the voltage bias on the input power. Generally, as the input power increases, the voltage bias also increases. A CMOS power amplifier with a shunt resistor arrangement and a floating gate linearizer arrangement allows for increased output power and increased efficiency while increasing input power.

The shunt resistor arrangement and floating gate linearizer arrangement as shown in figure 3C allow for an enhanced control ramp. The shunt resistor arrangement and floating gate linearizer can improve the linearization of the MOSFET in region 402 of fig. 4 using resistor Rb3 at reverse power as shown in fig. 3D. At higher powers, the secondary element will have more effect, for example in region 404 of fig. 4. The floating gate linearizer arrangement may improve the linearization of the MOSFETs in region 404.

The voltage deviation can be expressed as:

V_biasingQuadratic plus linear terms

Where the quadratic term comes from the MOSFET, where a floating gate linearizer arrangement may allow swing on the gate of the MOSFET, reducing Vgs and the slope. The floating gate linearizer arrangement allows the voltage on the gate due to the divided voltage to swing across the MOSFET capacitors Cgs and Cgd, as shown in fig. 5B.

The saturation region of a MOSFET can be determined by:

wherein C is_gs～C_gd＝C_n. In some embodiments, the MOSFET may include a depletion-mode MOSFET, an enhancement-mode MOSFET, a double-gate MOSFET, a metal-insulator-semiconductor fet (misfet), a power MOSFET, a double-diffused metal-oxide-semiconductor (DMOS), a radiation-hardened design (RHBD), a p-channel MOSFET (pmos), a tri-gate MOSFET (finfet), and/or the like. The gain source voltage can be expressed as:

thus, the floating gate effect can be expressed as:

a linear term may be added from the shunt resistor arrangement, which allows a linear ramp term to be added to the quadratic term of the MOSFET, which may enhance the control of the ramp. The linear term of the shunt resistance can be expressed as:

novel adaptive bias circuit performance in positive and negative voltage cycles

Fig. 5A is a diagram 500 of a CMOS power amplifier with a shunt resistor arrangement and a floating gate linearizer arrangement during a negative voltage period. Fig. 5B is a diagram 520 of a CMOS power amplifier with a shunt resistor arrangement and a floating gate linearizer arrangement during a positive voltage period. Diagrams 500, 520 of a CMOS power amplifier having a shunt resistor arrangement and a floating gate linearizer arrangement during negative voltage periods and positive voltage periods may include a shunt resistor arrangement 349 and a floating gate linearizer arrangement 369, as shown in fig. 3D.

In fig. 5A, a negative voltage period 502 is input. Without the shunt resistor arrangement and floating gate linearizer arrangement and using a constant bias, the input to power amplifier 302 may be voltage wave 508. With the shunt resistor arrangement 349 and the floating gate linearizer arrangement 369, a current 504 may flow through the shunt resistor arrangement 349 and the floating gate linearizer arrangement 369. Thus, terminal b of the MOSFET becomes the drain and terminal a of the MOSFET becomes the source, and the voltage bias will be supported to the input from voltage source Vb 3. Thus, the input to the power amplifier 302 may be a voltage wave 506. The voltage amplitude during the negative voltage period will increase which may result in higher average power and higher efficiency.

In fig. 5B, a positive voltage period 522 is input. Without the shunt resistor arrangement and floating gate linearizer arrangement and using a constant bias, the input to power amplifier 302 may be voltage wave 528. With the shunt resistor arrangement 349 and the floating gate linearizer arrangement 369, a current 524 may flow through the shunt resistor arrangement 349 and the floating gate linearizer arrangement 369. Thus, the terminal b of the MOSFET becomes the source, and the terminal a of the MOSFET becomes the drain, and will support a voltage bias from the input to the voltage source Vb 3. Thus, the input to the power amplifier 322 may be a voltage wave 526. The voltage amplitude during the positive voltage period will increase which may also result in higher average power and higher efficiency. Advantageously, the power amplifier and bias circuit may require a smaller heat sink due to the increased efficiency.

Simulation of novel adaptive bias circuit

Fig. 6A is an analog test bench of a CMOS power amplifier without an adaptive bias circuit. The circuit 602 shown in fig. 6A does not include an adaptive bias circuit.

Figure 6B is an analog test bench of a CMOS power amplifier with adaptive bias circuits. The adaptive bias circuit 652 may include a shunt resistor arrangement 349 and a floating gate linearizer arrangement 369, as shown in fig. 3D.

Fig. 7A is a graph 700 of gain versus output power. Trace 704 shows the gain versus output power for an analog CMOS power amplifier with an adaptive bias circuit, as shown in fig. 6A. Trace 702 shows the gain versus output power for an analog CMOS power amplifier without an adaptive bias circuit, as shown in fig. 6B. Simulations of CMOS power amplifiers with and without adaptive bias circuits show improvements in more constant gain with reduced slope and smaller peak gain values over power output.

Fig. 7B is a graph 710 of power amplifier efficiency versus output power. Trace 714 shows the power amplifier efficiency versus output power for an analog CMOS power amplifier with an adaptive bias circuit, as shown in fig. 6A. Trace 712 shows the power amplifier efficiency versus output power for an analog CMOS power amplifier without an adaptive bias circuit, as shown in fig. 6B. Simulations of CMOS power amplifiers with and without adaptive bias circuits showed 16% improvement at the P1dB point and 6% improvement at the 6dB back-off point.

Fig. 7C is a graph 720 of current consumption versus output power. Trace 724 shows current consumption versus output power for an analog CMOS power amplifier with adaptive bias circuits, as shown in FIG. 6A. Trace 722 shows the current consumption versus output power for an analog CMOS power amplifier without an adaptive bias circuit, as shown in fig. 6B. Simulations of CMOS power amplifiers with and without adaptive bias circuits show reduced slope, improved linearity and enhanced controlled ramp of the ramp.

Fig. 8A is a graph 800 of AM-AM distortion versus output power. Trace 804 shows the distortion versus output power for an analog CMOS power amplifier with an adaptive bias circuit, as shown in fig. 6A. Trace 802 shows the distortion versus output power for an analog CMOS power amplifier without an adaptive bias circuit, as shown in fig. 6B.

Fig. 8B is a graph 810 of AM-PM distortion versus output power. Trace 814 shows the AM-PM distortion versus output power for an analog CMOS power amplifier with an adaptive bias circuit, as shown in fig. 6A. Trace 812 shows the AM-PM distortion versus output power for an analog CMOS power amplifier without an adaptive bias circuit, as shown in fig. 6B.

As shown, the CMOS power amplifier with the adaptive bias circuit improves AM-AM distortion and AM-PM distortion. The AM-AM distortion of the power amplifier (fig. 8A) is improved because the adaptive biasing circuit flattens the AM-AM distortion and becomes constant with output power, thereby improving the linearity of the communication system, reducing EVM (error vector magnitude) and OIP 3. The AM-PM distortion is improved compared to the output power of the power amplifier (fig. 8B) because the adaptive biasing circuit flattens the AM-PM distortion and becomes constant with the output power, which improves the output power intercept point OIP 3.

Fig. 9 is a graph 900 of output intercept point OIP3 versus output power. Trace 904 shows the output intercept point OIP3 versus output power for an analog CMOS power amplifier with an adaptive bias circuit, as shown in fig. 6A. Trace 902 shows the output intercept point OIP3 versus output power for an analog CMOS power amplifier without an adaptive bias circuit, as shown in fig. 6B. As shown, the effect of the shunt resistor arrangement and floating gate linearizer arrangement improves the output intercept point OIP 3. Since the distortion of the AM-AM and AM-PM in the output power is improved, the linearizer improves the OIP3 and the output power of the power amplifier.

Test results achieved by new adaptive bias circuits

Fig. 10 is a detailed schematic diagram of a differential class-3 class-a CMOS power amplifier without a new adaptive bias circuit (wireless) according to some embodiments. Fig. 11 is a detailed schematic diagram of a differential class-3 class AB CMOS power amplifier with a new adaptive bias circuit according to some embodiments.

The OP1dB measurements for the CMOS power amplifier without the new adaptive bias circuit are shown in fig. 10 with a minimum of 11dBm, typically 12.2 dBm. The OP1dB measurements for the CMOS power amplifier with the new adaptive bias circuit are shown in fig. 11 with a minimum of 14dBm, typically 15 dBm.

A typical value for the measured value of the power consumption (2 volts Vdd) of a CMOS power amplifier without the new adaptive bias circuit shown in fig. 10 is 98 mW. The measured values of power consumption (2 volt Vdd) for a CMOS power amplifier with the new adaptive bias circuit are shown in fig. 11 with a minimum of 14dBm, and a typical value of 50 mW.

For a CMOS power amplifier without the new adaptive bias circuit shown in fig. 10, the measured value of the power amplifier efficiency at P1dB at 28GHz is 18%. For a CMOS power amplifier with the new adaptive bias circuit shown in fig. 11, the measured values of power amplifier efficiency at P1dB at 28dB are at least 14dBm and 27%.

FIG. 12A is a graph 1300 of the output P1dB compression point versus RF frequency. Trace 1302 shows the output P1dB compression point versus RF frequency for a CMOS power amplifier with the new adaptive bias circuit of fig. 11. Trace 1304 shows the output P1dB compression point versus RF frequency for a CMOS power amplifier without the new adaptive bias circuit shown in fig. 10.

Fig. 12B is a graph 1310 of power amplifier efficiency versus output power. Trace 1312 illustrates the power amplifier efficiency versus output power for a CMOS power amplifier with the new adaptive bias circuit (fig. 11). Trace 1314 shows the power amplifier efficiency versus output power for a CMOS power amplifier without the new adaptive bias circuit (fig. 10).

As shown in fig. 12A and 12B, the output P1dB compression point and efficiency performance are improved with the new adaptive bias circuit. This improvement is achieved over a wide frequency band. With the new adaptive bias circuit, the output P1dB in fig. 12A is increased by more than 2 dBm.

Fig. 13 is a graph 1420 of output intercept point OIP3 versus output power. Trace 1401 shows the power amplifier efficiency versus output power for a CMOS power amplifier with the new adaptive bias circuit (fig. 11) at 25 GHz. Trace 1403 shows the power amplifier efficiency versus output power for a CMOS power amplifier without the new adaptive bias circuit (fig. 10) at 25 GHz.

Trace 1402 shows power amplifier efficiency versus output power for a CMOS power amplifier with the new adaptive bias circuit (fig. 11) at 28 GHz. Trace 1404 shows the power amplifier efficiency versus output power for a CMOS power amplifier without the new adaptive bias circuit (fig. 10) at 28 GHz. As shown, the new adaptive bias circuit improves IM3 components and OIP3 at higher output power.

Fig. 14A is a graph 1500 of intermodulation distortion IM3 versus output power for different tone spacing of two-tone signals using a CMOS power amplifier with the new adaptive bias circuit shown in fig. 11. Fig. 14B is a graph 1510 of the third intercept point OIP3 versus output power for different tone spacing of a two-tone signal using a CMOS power amplifier with the new adaptive bias circuit shown in fig. 11. As shown, the new adaptive biasing circuit can support enhanced linearity across different tone intervals, and thus the new adaptive biasing circuit enhances the linearity and efficiency of the wideband signal.

FIG. 15A is a graph 1600 of AM-AM distortion versus output power at approximately 28 GHz. Trace 1604 shows the AM to AM distortion versus output power for a CMOS power amplifier without the new adaptive bias circuit shown in fig. 10, and trace 1602 shows the AM to AM distortion versus output power for a CMOS power amplifier with the new adaptive bias circuit shown in fig. 11.

FIG. 15B is a graph 1610 of AM-PM distortion versus output power at approximately 28 GHz. Trace 1614 shows the AM to PM distortion versus output power for a CMOS power amplifier without the new adaptive bias circuit shown in fig. 10, and trace 1612 shows the AM to PM distortion versus output power for a CMOS power amplifier with the new adaptive bias circuit shown in fig. 11.

Fig. 15C is a graph 1620 of current versus output power at approximately 28 GHz. Trace 1624 shows the current versus output power relationship for a CMOS power amplifier without the new adaptive bias circuit shown in fig. 10, and trace 1622 shows the current versus output power relationship for a CMOS power amplifier with the new adaptive bias circuit shown in fig. 11.

Fig. 16A is a graph 1700 of AM-AM distortion versus output power at approximately 38 GHz. Trace 1704 shows the AM to AM distortion versus output power for a CMOS power amplifier without the new adaptive bias circuit shown in fig. 10, and trace 1702 shows the AM to AM distortion versus output power for a CMOS power amplifier with the new adaptive bias circuit shown in fig. 11.

Fig. 16B is a graph 1710 of AM to PM distortion versus output power at approximately 38 GHz. Trace 1714 shows the AM to AM distortion versus output power for a CMOS power amplifier without the new adaptive bias circuit shown in fig. 10, and trace 1712 shows the AM to AM distortion versus output power for a CMOS power amplifier with the new adaptive bias circuit shown in fig. 11.

Fig. 16C is a graph 1720 of current versus output power at approximately 38 GHz. Trace 1724 shows the current versus output power relationship for a CMOS power amplifier without the new adaptive bias circuit shown in fig. 10, and trace 1722 shows the current versus output power relationship for a CMOS power amplifier with the new adaptive bias circuit shown in fig. 11.

Graphs 1600, 1610, 1700, 1710 of fig. 15A, 15B, 16A and 16B show the improvement in distortion performance of the new adaptive circuit. Graphs 1620, 1720 of fig. 15C and 16C illustrate the reduced current required for voltage output using the new adaptive circuit.

Fig. 17 is a plot 1800 of the S21 parameter (forward voltage gain) versus frequency. Trace 1804 shows the S21 parameter (forward voltage gain) versus frequency for a CMOS power amplifier without the new adaptive bias circuit shown in fig. 10, and trace 1802 shows the S21 parameter (forward voltage gain) versus frequency for a CMOS power amplifier with the new adaptive bias circuit shown in fig. 11.

Applications of

Any of the principles and advantages discussed herein may be applied to other systems, not just the systems described above. The elements and operations of the various embodiments described above can be combined to provide further embodiments. Some embodiments described above provide examples related to transceiver integrated circuits. However, the principles and advantages of the embodiments may be employed in conjunction with any other system, apparatus, or method that may benefit from any of the teachings herein.

Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, components of consumer electronics such as semiconductor chips and/or package modules, electronic test equipment, wireless communication devices, personal area network communication devices, cellular communication infrastructure such as base stations, and so forth. Examples of consumer electronics products may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smart watches or headsets, telephones, televisions, computer monitors, computers, routers, modems, handheld computers, laptop computers, tablet computers, Personal Digital Assistants (PDAs), microwave ovens, refrigerators, automotive electronic systems such as car electronic systems, stereos, DVD players, CD players, digital music players such as MP3 players, radios, camcorders, cameras such as digital cameras, portable memory chips, washing machines, dryers, washing/drying machines, peripherals, clocks, and so forth. Further, the electronic device may include unfinished products.

Conclusion

Unless the context requires otherwise, throughout the description and the claims, the words "comprise," "comprising," "have," "having," and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, in the sense of "including, but not limited to". As generally used herein, the term "coupled" refers to two or more elements that may be coupled to each other directly or through one or more intermediate elements. Likewise, the word "connected," as generally used herein, refers to two or more elements that may be connected directly or through one or more intermediate elements. Additionally, as used in this application, the words "herein," "above," "below," and words of similar import shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above detailed description of certain embodiments using the singular or plural number may also include the plural or singular number, respectively. The word "or" in reference to a list of two or more items is generally intended to include all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

Furthermore, conditional language, e.g., "can," might, "" e.g., "such as" and the like, as used herein are generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or states, unless expressly stated otherwise or otherwise understood in the context of such use. Thus, such conditional language is not generally intended to imply that features, elements, and/or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for determining whether such features, elements, and/or states are included or are to be performed in any particular embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the present disclosure. Indeed, the novel methods, apparatus and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods, devices, and systems described herein may be made without departing from the spirit of the disclosure. For example, circuit blocks described herein may be deleted, moved, added, subdivided, combined, and/or modified. Each of these circuit blocks may be implemented in a variety of different ways. The accompanying claims and their equivalents are intended to cover any such forms or modifications as fall within the scope and spirit of the disclosure.