阅读说明：本技术 一种基于边沿控制的降低脉冲信号抖动方法及系统 (Method and system for reducing pulse signal jitter based on edge control ) 是由 朱卫国 罗阳 滕友伟 逄锦昊 李旭 李茂林 于 2019-11-12 设计创作，主要内容包括：本公开提出了一种基于边沿控制的降低脉冲信号抖动方法及系统,方法包括：采用固定的采样率,根据脉冲的频率控制字,通过累加的方式实时生成数字脉冲信号的相位信息序列；根据相位信息序列与脉冲的占空比控制字生成数字脉冲序列；对数字脉冲序列的边沿进行调节；将边沿调节后的数字脉冲序列进行数字平均运算,获得新的数字脉冲序列,将新的数字脉冲序列进行数模转换输出脉冲信号。通过实时边沿数值控制和实时数字平均方法,针对FPGA与DAC能力范围内的任何频率、任何占空比的脉冲信号,无需提升或改变采样率,可以实现对任何采样率下连续输出脉冲信号的降抖动,控制灵活,能有效解决FPGA产生脉冲信号固有的抖动过大的问题。(The present disclosure provides a method and a system for reducing pulse signal jitter based on edge control, the method includes: generating a phase information sequence of the digital pulse signal in real time in an accumulation mode by adopting a fixed sampling rate and according to the frequency control word of the pulse; generating a digital pulse sequence according to the phase information sequence and the duty ratio control word of the pulse; adjusting the edge of the digital pulse sequence; and carrying out digital average operation on the digital pulse sequence after edge adjustment to obtain a new digital pulse sequence, and carrying out digital-to-analog conversion on the new digital pulse sequence to output a pulse signal. By means of the real-time edge numerical control and real-time digital averaging method, pulse signals of any frequency and any duty ratio within the capacity range of the FPGA and the DAC are subjected to pulse signal reduction and jitter output continuously under any sampling rate without increasing or changing the sampling rate, control is flexible, and the problem that the inherent jitter of the pulse signals generated by the FPGA is too large can be effectively solved.)

1. A method for reducing pulse signal jitter based on edge control is characterized by comprising the following steps:

generating a phase information sequence of the digital pulse signal in real time in an accumulation mode by adopting a fixed sampling rate and according to the frequency control word of the pulse;

generating a digital pulse sequence according to the phase information sequence and the duty ratio control word of the pulse;

the edges of the digital pulse sequence are adjusted: calculating the error between the ideal edge moment and the actual sampling moment, correcting the output edge moment according to the error, and generating an edge-adjusted digital pulse sequence;

and carrying out digital average operation on the digital pulse sequence after edge adjustment to obtain a new digital pulse sequence, and carrying out digital-to-analog conversion on the new digital pulse sequence to output a pulse signal.

2. The method for reducing the jitter of the pulse signal based on the edge control as claimed in claim 1, wherein: the steps before the digital-to-analog conversion can be realized in the FPGA, and the frequency control word and the duty ratio control word of the pulse are two characteristic parameters for generating the digital pulse.

3. The method for reducing the jitter of the pulse signal based on the edge control as claimed in claim 1, wherein: the method for generating the digital pulse sequence according to the phase information sequence and the duty ratio control word of the pulse specifically comprises the following steps: the value of the phase information is a low level value of-1 when the value of the phase information is lower than the duty ratio control word, and the value of the phase information is a high level value of +1 when the value of the phase information is higher than the duty ratio control word.

4. The method for reducing the jitter of the pulse signal based on the edge control as claimed in claim 1, wherein: a method for generating a phase information sequence of a digital pulse signal in real time in an accumulation manner, comprising the steps of:

initializing a phase value of a phase information sequence of the digital pulse signal;

the phase values are accumulated for each processing clock by a frequency control word of one pulse to form a sequence of phase information.

5. The method for reducing the jitter of the pulse signal based on the edge control as claimed in claim 1, wherein: the method for calculating the error between the ideal edge time and the actual sampling time and correcting the output edge time according to the error may specifically be:

calculating and generating the time position of the ideal edge moment in the actual sampling sequence according to the phase information sequence and the duty ratio control word of the pulse;

calculating the time difference △ T between the ideal edge time and the left adjacent sampling time according to the time position_leftAnd simultaneously calculating the time difference △ T between the ideal edge moment and the right adjacent sampling moment_rightAccording to △ T_leftAnd △ T_rightThe ratio of the sampling points is calculated according to the proportion to generate an adjustment limit, and the numerical value of the left adjacent sampling point is adjusted.

6. The method for reducing jitter of pulse signals based on edge control as claimed in claim 5, wherein: the step of adjusting the value of the left adjacent sampling point further comprises normalizing the adjustment range between-1 and + 1.

7. The method for reducing the jitter of the pulse signal based on the edge control as claimed in claim 1, wherein: and carrying out digital average operation on the digital pulse sequence after edge adjustment, wherein the number of average points is not less than 3 and is an odd number.

8. The method for reducing the jitter of the pulse signal based on the edge control as claimed in claim 1, wherein: the step of performing digital average operation on the digital pulse sequence after edge adjustment comprises the following steps:

setting the numerical value of the average point number N, and calculating and generating an average coefficient according to the average point number N, wherein the average coefficient k is 1/N;

and for the digital pulse sequence after edge adjustment, multiplying N pulse number digital values in the pulse sequence by an average coefficient k every time one processing clock comes, and adding the N products to generate a new pulse value serving as the pulse number digital value at the middle of the N pulse number digital values, thereby forming a new digital pulse sequence.

9. An edge control-based system for reducing pulse signal jitter is characterized in that: the FPGA device comprises an FPGA device and a digital-to-analog converter, wherein a chip processor of the FPGA device comprises:

a phase information sequence generation module: the phase information sequence is used for generating a phase information sequence of the digital pulse signal in real time in an accumulation mode according to the frequency control word of the pulse by adopting a fixed sampling rate;

a first pulse sequence generation module: the digital pulse sequence is generated according to the phase information sequence and the duty ratio control word of the pulse;

an edge value adjusting module: the digital pulse sequence is used for adjusting the edge of the digital pulse sequence, calculating the error between the ideal edge moment and the actual sampling moment, correcting the output edge moment according to the error and generating the digital pulse sequence after edge adjustment;

a digital averaging module: and the digital average operation is carried out on the digital pulse sequence after the edge adjustment to obtain a new digital pulse sequence.

10. The system of claim 9, wherein the edge value adjusting module comprises:

a module for calculating and generating the time position of the ideal edge moment in the actual sampling sequence according to the phase information sequence and the duty ratio control word of the pulse;

for calculating the time difference △ T between the ideal edge time and the left adjacent sampling time according to the time position_leftAnd simultaneously calculating the time difference △ T between the ideal edge moment and the right adjacent sampling moment_rightAccording to △ T_leftAnd △ T_rightThe ratio of the sampling points is calculated according to the proportion to generate an adjusting limit, and the numerical value of the left adjacent sampling point is adjusted.

Technical Field

The disclosure relates to the technical field of electronic test and measurement, in particular to a method and a system for reducing pulse signal jitter based on edge control.

Background

The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.

Pulse signals and square wave signals (square waves are special pulses with the duty ratio of 1:2) are very widely applied signals and have very wide application in the fields of radar, digital signal transmission, industrial flaw detection and the like. The frequency and the duty ratio of modern pulse signals are various, the high frequency can reach GHz level, the low frequency can be as low as mu Hz level, and the pulse signals from low frequency to high frequency can be conveniently generated in a Field Programmable Gate Array (FPGA) through a direct digital frequency synthesis mode, so the modern pulse signals are mainly realized by adopting the FPGA and a digital-to-analog converter (DAC), pulse digital sampling signals are generated in the FPGA firstly and are sent to the DAC through a parallel or serial interface, and the DAC completes the conversion from digital pulse signals to analog pulse signals to generate the required pulse signals.

The level of the pulse signal theoretically has only two values: high level, low level, duty cycle is high level time/pulse period. When a digital pulse signal is generated in an FPGA, a digital pulse sampling sequence is generated at a fixed sampling rate, and the numerical value of each sample point in the sequence generally corresponds to two values: +1 or-1 (normalized value), the instant of switching of these two values in the sequence being the edge of the pulse. In the FPGA, when the sampling rate is not in integral multiple relation with the frequency of a pulse signal, the moment of a pulse edge can fall at a position in the middle of two sampling moments, at the moment, the values of the two sampling moments are not equal to minus 1 or plus 1, so that the actual edge is inconsistent with the ideal edge, and the pulse edge can shake in the middle of the two sampling moments in a time domain, thereby causing the edge shake of the actually generated pulse signal. The magnitude of the jitter error depends on the sampling rate in the FPGA, for example when the sampling rate is 200MHz, the typical output jitter is 1/200 MHz-5 ns.

In the fields of radar, industrial flaw detection and the like, pulse jitter directly affects measurement accuracy, for example, in a radar, a jitter error of 1ns brings about a distance measurement error of about 0.3 m, and the damage to the measurement accuracy is very large. How to effectively reduce the output jitter of the pulse signal to be below ps (generally hundreds of fs levels) in the FPGA is a technical problem which needs to be broken through.

The existing pulse signal jitter reduction method is mainly realized by increasing the sampling rate or changing the sampling rate of the pulse signal. The method for increasing the sampling rate is limited by the sampling rate of the FPGA and the DAC, so that the method is difficult to increase to a large extent, and the jitter is difficult to be reduced to be below ps by increasing the sampling rate in the modern FPGA and DAC; the "changing the sampling rate of the pulse signal" is generally to select the sampling rate according to the frequency of the pulse signal, and the period corresponding to the selected sampling rate can exactly divide the pulse period, which is very effective for pulse signals with special duty ratios, for example, the pulse signal period is 100ns, the duty ratio is 1:2, the duration of the high level and the low level of the pulse is 50ns, and if the sampling period is 5ns, the jitter can be eliminated in the digital domain. However, this method has a very obvious disadvantage that jitter exists on one edge of the rising edge or the falling edge when the high level time or the low level time of the pulse corresponding to the duty ratio is not an integral multiple of the sampling period. Therefore, the existing methods of "increasing the sampling rate" or "changing the sampling rate of the pulse signal" still cannot completely avoid the jitter.

Disclosure of Invention

The invention aims to solve the problems and provides a method and a system for reducing the jitter of a pulse signal based on edge control, wherein the output jitter of the pulse signal is reduced by a real-time digital signal processing method in an FPGA (field programmable gate array), the output jitter of the pulse signal is mainly reduced by the numerical control of pulse edge sampling points and the digital averaging of the sampling points in the FPGA, the jitter of the output pulse signal can be obviously reduced without increasing or changing the sampling rate aiming at the pulse signal with any frequency and any duty ratio in the capacity range of the FPGA and a DAC (digital-to-analog converter), the jitter of the continuously output pulse signal under any sampling rate can be reduced, the typical jitter can be reduced to be less than 500fs, and the jitter reduction effect is obvious. The method is suitable for the pulse signal jitter reduction processing in radars and electronic equipment, is realized through FPGA digital signal processing software, is flexible to control, and can effectively solve the problem of excessive intrinsic jitter of pulse signals generated by the FPGA.

In order to achieve the purpose, the following technical scheme is adopted in the disclosure:

one or more embodiments provide a method for reducing pulse signal jitter based on edge control, comprising the following steps:

generating a phase information sequence of the digital pulse signal in real time in an accumulation mode by adopting a fixed sampling rate and according to the frequency control word of the pulse;

generating a digital pulse sequence according to the phase information sequence and the duty ratio control word of the pulse;

the edges of the digital pulse sequence are adjusted: calculating the error between the ideal edge moment and the actual sampling moment, correcting the output edge moment according to the error, and generating an edge-adjusted digital pulse sequence;

and carrying out digital average operation on the digital pulse sequence after edge adjustment to obtain a new digital pulse sequence, and carrying out digital-to-analog conversion on the new digital pulse sequence to output a pulse signal.

Further, the steps before the digital-to-analog conversion can be implemented in the FPGA, and the frequency control word and the duty ratio control word of the pulse are two characteristic parameters for generating the digital pulse.

Further, the method for generating the digital pulse sequence according to the phase information sequence and the duty ratio control word of the pulse specifically comprises the following steps: the value of the phase information is a low level value of-1 when the value of the phase information is lower than the duty ratio control word, and the value of the phase information is a high level value of +1 when the value of the phase information is higher than the duty ratio control word.

Further, a method for generating a phase information sequence of a digital pulse signal in real time by accumulation comprises the following steps:

initializing a phase value of a phase information sequence of the digital pulse signal;

the phase values are accumulated for each processing clock by a frequency control word of one pulse to form a sequence of phase information.

Further, the method for calculating the error between the ideal edge time and the actual sampling time and correcting the output edge time according to the error may specifically be:

calculating and generating the time position of the ideal edge moment in the actual sampling sequence according to the phase information sequence and the duty ratio control word of the pulse;

calculating the time difference △ T between the ideal edge time and the left adjacent sampling time according to the time position_leftAnd simultaneously calculating the time difference △ T between the ideal edge moment and the right adjacent sampling moment_rightAccording to △ T_leftAnd △ T_rightThe ratio of the sampling points is calculated according to the proportion to generate an adjustment limit, and the numerical value of the left adjacent sampling point is adjusted.

Further, the step of adjusting the value of the left adjacent sampling point further comprises normalizing the adjustment range between-1 and + 1.

Further, the digital pulse sequence after edge adjustment is subjected to digital average operation, and the number of average points is not less than 3 and is an odd number.

Further, the step of performing digital average operation on the edge-adjusted digital pulse sequence includes:

setting the numerical value of the average point number N, and calculating and generating an average coefficient according to the average point number N, wherein the average coefficient k is 1/N;

and for the digital pulse sequence after edge adjustment, multiplying N pulse number digital values in the pulse sequence by an average coefficient k every time one processing clock comes, and adding the N products to generate a new pulse value serving as the pulse number digital value at the middle of the N pulse number digital values, thereby forming a new digital pulse sequence.

An edge control-based system for reducing pulse signal jitter comprises an FPGA device and a digital-to-analog converter, wherein a chip processor of the FPGA device comprises:

a phase information sequence generation module: the phase information sequence is used for generating a phase information sequence of the digital pulse signal in real time in an accumulation mode according to the frequency control word of the pulse by adopting a fixed sampling rate;

a first pulse sequence generation module: the digital pulse sequence is generated according to the phase information sequence and the duty ratio control word of the pulse;

an edge value adjusting module: the digital pulse sequence is used for adjusting the edge of the digital pulse sequence, calculating the error between the ideal edge moment and the actual sampling moment, correcting the output edge moment according to the error and generating the digital pulse sequence after edge adjustment;

a digital averaging module: and the digital average operation is carried out on the digital pulse sequence after the edge adjustment to obtain a new digital pulse sequence.

Further, the edge value adjusting module comprises:

a module for calculating and generating the time position of the ideal edge moment in the actual sampling sequence according to the phase information sequence and the duty ratio control word of the pulse;

for calculating the time difference △ T between the ideal edge time and the left adjacent sampling time according to the time position_leftAnd simultaneously calculating the time difference △ T between the ideal edge moment and the right adjacent sampling moment_rightAccording to △ T_leftAnd △ T_rightThe ratio of the sampling points is calculated according to the proportion to generate an adjusting limit, and the numerical value of the left adjacent sampling point is adjusted.

Compared with the prior art, the beneficial effect of this disclosure is:

the method realizes jitter reduction through pulse edge sampling point numerical control and sampling point digital average, can be realized through digital signal operation in FPGA, does not need to improve or change the sampling rate aiming at pulse signals with any frequency and any duty ratio in the capacity range of FPGA and DAC, can obviously reduce the jitter of output pulse signals, can realize the jitter reduction of continuously output pulse signals under any sampling rate, can reduce the typical jitter to below 500fs, and has obvious jitter reduction effect.

The method and the device have the advantages that the error between the ideal edge moment and the actual sampling moment is calculated and generated according to the phase information and the duty ratio control word, the real-time adjustment of the pulse edge position can be realized, the adjustment precision is high, the implementation in the FPGA is simpler, and a lot of FPGA resources are not required to be occupied.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and not to limit the disclosure.

FIG. 1 is a flow diagram of a method in accordance with one or more embodiments;

fig. 2 is a graph of the effect of edge offset achieved by edge value adjustment and digital averaging according to embodiment 1 of the present disclosure;

fig. 3 is a schematic diagram of the edge timing error extraction technique in embodiment 1 of the present disclosure;

fig. 4 is a system block diagram of embodiment 2 of the present disclosure.

The specific implementation mode is as follows:

the present disclosure is further described with reference to the following drawings and examples.

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments in the present disclosure may be combined with each other. The embodiments will be described in detail below with reference to the accompanying drawings.

In one or more embodiments, as shown in fig. 1, a method for reducing pulse signal jitter based on edge control includes the following steps:

s1, adopting a fixed sampling rate f_sGenerating a phase information sequence of the digital pulse signal in real time in an accumulation mode according to the frequency control word of the pulse;

s2, generating a digital pulse sequence according to the phase information sequence and the duty ratio control word of the pulse;

s3, adjusting the edge of the digital pulse sequence: calculating the error between the ideal edge moment and the actual sampling moment, correcting the output edge moment according to the error, and generating an edge-adjusted digital pulse sequence;

and S4, carrying out digital average operation on the digital pulse sequence after edge adjustment to obtain a new digital pulse sequence, and carrying out digital-to-analog conversion on the new digital pulse sequence to output a pulse signal.

In this embodiment, optionally, the step before the analog-to-digital conversion in the above step may be implemented in an FPGA, and the frequency control word and the duty ratio control word of the pulse are two characteristic parameters for generating the digital pulse.

In step S2, a digital pulse sequence is generated according to the phase information sequence and the duty cycle control word of the pulse, the generated digital pulse value has only two values, which are either equal to the high level value +1 or equal to the low level value-1, the value of the phase information is equal to the low level value-1 when the value of the phase information is lower than the duty cycle control word, and the value of the phase information is equal to the high level value +1 when the value of the phase information is higher than the duty cycle control word.

As a further improvement, the method for generating the phase information sequence of the digital pulse signal in real time by means of accumulation comprises the following steps:

s11, initializing a phase value of a phase information sequence of the digital pulse signal;

optionally, when the pulse parameter is changed, setting an initial phase value to be 0 in the FPGA; the pulse parameters are frequency control words and duty ratio control words of the pulses.

S12, accumulating the phase values for each processing clock to form a frequency control word of one pulse, and forming a phase information sequence.

In an FPGA, the phase values accumulate the frequency control words of one pulse each time a clock is processed, forming a sequence of phase information.

In step S3, the method for calculating the error between the ideal edge time and the actual sampling time and correcting the output edge time according to the error may specifically be:

calculating and generating the time position of the ideal edge moment in the actual sampling sequence according to the phase information sequence and the duty ratio control word of the pulse;

calculating the time difference △ T between the ideal edge time and the left adjacent sampling time according to the time position_leftAnd simultaneously calculating the time difference △ T between the ideal edge moment and the right adjacent sampling moment_rightAccording to △ T_leftAnd △ T_rightThe ratio of the sampling points is calculated according to the proportion to generate an adjustment limit, and the numerical value of the left adjacent sampling point is adjusted.

According to △ T_leftAnd △ T_rightThe ratio is calculated according to a proportion to generate an adjustment limit, the numerical value of the left adjacent sampling point is adjusted to obtain an adjusted numerical value D of the left adjacent sampling point, and the adjustment limit is calculated according to the following formula:

in some embodiments, the step of adjusting the value of the left adjacent sample point further comprises normalizing the adjustment range to be between-1 and + 1.

In step S4, the digital pulse sequence with the edge adjusted is subjected to digital average operation, and the number of average points is not less than 3.

Optionally, the step of performing digital average operation on the edge-adjusted digital pulse sequence includes:

1. setting the numerical value of the average point number N, and calculating and generating an average coefficient according to the average point number N, wherein the average coefficient k is 1/N; the value of N is typically odd.

2. And for the digital pulse sequence after edge adjustment, multiplying N pulse number digital values in the pulse sequence by an average coefficient k every time one processing clock comes, and adding the N products to generate a new pulse value serving as the pulse number digital value at the middle of the N pulse number digital values, thereby forming a new digital pulse sequence.

Specifically, if the digital pulse sequence after edge adjustment is (a1, a2, A3, a4, a5, a6, a7, A8), N is 5; update a3 to a value of

Update A4 to a value of

The same method is adopted for updating other values A5 and A6 in the sequence. For a digital pulse sequence with only 1 and-1 pulse digital values, only the value at the point of change from 1 to-1 or from-1 to 1 changes.

The following is a description of the process and principle of the above steps:

for a typical digital pulse sequence, the value is either +1 (normalized value) or-1. If the sampling period is not divided by the high-level time or the low-level time of the pulse, the value change of "+ 1 to-1" and "-1 to + 1" will cause the rising or falling edge time to deviate from the ideal time, and the deviation is not fixed, and will change in one sampling period during the continuous output of the pulse sequence, thereby causing jitter. In this embodiment, an edge value adjustment technology is adopted, a new value of a sampling point before the edge time after step S3 is executed is D by adjusting a value of a sampling point before the rising or falling edge time, and the time position of the edge can be moved in a digital average manner, which is determined by adjusting the limit, and the edge position can be controlled to coincide with the ideal position infinitely by adjusting the limit, thereby reducing jitter. The effect of reducing jitter depends on the sampling period and the resolution of D, for example, the sampling period is 200ps, the resolution of D is 1/512, the jitter can be reduced to 200 ps/512-390 fs, but the higher the resolution of D, the more FPGA resources are consumed, the jitter is limited by DAC, and the above factors are taken into consideration, and the resolution corresponding to the jitter precision of less than 500fs is generally selected. In table 1, edge value adjustment and digital averaging are performed on the rising edge of a consecutive sequence of originally sampled digital pulses (… …, -1, -1, -1, +1, +1, … …), and the sequence values before and after the point of change are numerically averaged: the average coefficient k corresponding to the 5-value digital average is 0.2, 5 sampling points of each sampling point and adjacent sampling points are multiplied by the average coefficient 0.2, and the 5 products are added to obtain a new value, so that a new sequence is generated, and the edge time position corresponding to the output new sequence is subjected to expected offset and is consistent with an ideal position, as shown in fig. 2. The value range of the new value D is between-1 and +1, and the corresponding adjustable range of the edge time is one sampling period.

TABLE 1 pulse sequence comparison table before and after "edge value adjustment and digital averaging

Regulating limit	Novel sequences after modulation	New sequence after 5 value number average
			Is not regulated	…,-1,-1,-1,-1,+1,+1,+1,+1,…	…,-1,-0.6,-0.2,+0.2,+0.6,+1,…
Adjust-1 to 0	…,-1,-1,-1,0,+1,+1,+1,+1,…	…,-0.8,-0.4,0,+0.4,+0.8,+1,…
			Adjust-1 to +1	…,-1,-1,-1,+1,+1,+1,+1,+1,…	…,-0.6,-0.2,+0.2,+0.6,+1,+1…

To reduce jitter in the FPGA, the FPGA processor must know the error between the ideal edge time and the actual sampling time, and the output edge time can be corrected according to the error, thereby reducing jitter.

In the embodiment, firstly, a phase accumulation method is utilized to generate pulse phase information, an error between an ideal edge moment and an actual sampling moment is calculated and generated according to the phase information and a duty ratio control word, and real-time adjustment of a pulse edge is realized according to an error value. For the sake of convenience of explaining the technical principle, as shown in fig. 3, the pulse frequency control word is set to 8' h25(8 bits, corresponding to a frequency of f)_sX 0x 25/0 xFF), a duty ratio control word is 8 'h 7F (corresponding to a duty ratio of 1:2), a phase value P is initialized to 0 in the FPGA, the phase value P is increased by 8' h25 every time a sampling clock comes later, when the phase value P is more than 8 'hFF after the sampling is added to the overflow, the overflow is shown to be completed in one pulse period, meanwhile, the next period is started, the P value has a rising process and a falling process in one pulse period, the intersection point of a numerical value line of the duty ratio control word 8' h7F and a rising process straight line is an ideal rising edge time, namely, the intersection point of the overflow value 0xFF and the rising process straight line is an ideal falling edge time, and the difference value of the time and the left adjacent sampling time is △ T_leftThe difference value from the right adjacent sampling time is △ T_right，△T_leftAnd △ T_rightNamely, the time errors of the ideal edge moment and the two adjacent real sampling moments are represented.

According to △ T_leftAnd △ T_rightAdjust the value of the left adjacent sample point, the current value of the left adjacent sample point is 0x6F_leftAnd △ T_rightBecause division operation has larger time delay in FPGA, △ T is obtained by using a table look-up method_leftAnd △ T_rightThe ratio of (A) is only one clock cycle of delay, which is convenient for implementation in an FPGA, △ T for the rising edge in FIG. 3_left＝0x7F-0x6F＝0x10，△T_right＝0x94-0x7F＝0x15，△T_leftAnd △ T_rightIs 16:21, then △ T_left/(△T_left+△T_right)＝16/(16+21)≈0.43, according to the proportional relation in the general technical principle, a new value can be calculated according to the formula 0.43 × (+1) - (-1)) -1 ═ 0.14, the value of the sampling point before the rising edge is adjusted from-1 to-0.14, and after digital averaging, the edge offset effect shown in fig. 2 can be achieved, so that the jitter is reduced.

Therefore, all the processing procedures of the method can be realized in the FPGA through digital signal operation, the realization is convenient, the method removes the limitation of adopting the method of increasing the sampling rate or changing the sampling rate of the pulse signal, is suitable for the pulse jitter reduction processing of any frequency and duty ratio in the bandwidth range of the FPGA and the DAC, has wide application range, can realize low jitter below 500fs, and has obvious effect of reducing the pulse jitter.