阅读说明：本技术 一种基于双mos栅控的p型碳化硅晶闸管及其制备方法 (P-type silicon carbide thyristor based on double MOS gate control and preparation method thereof ) 是由 汤晓燕 周腾鹏 元磊 宋庆文 张艺蒙 张玉明 张义门 于 2019-11-04 设计创作，主要内容包括：本发明公开了一种基于双MOS栅控的P型碳化硅晶闸管,包括：钝化层(1)、阳极接触金属(2)、关断栅极接触金属(3)、开启栅极接触金属(4)、栅氧化层(5)、N+短路区(6)、P+阳极区(7)、N-漂移区(8)、P-漂移区(9)、缓冲层(10)、衬底(11)以及阴极接触金属(12)。本发明通过引入双MOS栅结构,将器件的驱动控制从传统的电流型转变为电压型,有利于前端控制电路的设计、实现以及功耗的降低；且开启栅和关断栅独立工作,分别控制器件的开启和关断,有利于器件在开关或脉冲工作状态下的快速导通和关断,可以显著提高器件的工作频率。(The invention discloses a P-type silicon carbide thyristor based on double MOS gate control, which comprises: the gate-on-insulator structure comprises a passivation layer (1), anode contact metal (2), gate-off contact metal (3), gate-on contact metal (4), a gate oxide layer (5), an N + short circuit region (6), a P + anode region (7), an N-drift region (8), a P-drift region (9), a buffer layer (10), a substrate (11) and cathode contact metal (12). According to the invention, by introducing a double-MOS gate structure, the drive control of the device is changed from a traditional current mode to a voltage mode, so that the design and the realization of a front-end control circuit and the reduction of power consumption are facilitated; and the turn-on grid and the turn-off grid work independently to control the turn-on and the turn-off of the device respectively, so that the device is favorable for being quickly turned on and off in a switch or pulse working state, and the working frequency of the device can be obviously improved.)

1. A P-type silicon carbide thyristor based on dual MOS gate control is characterized by comprising: a passivation layer (1), an anode contact metal (2), a gate off contact metal (3), a gate on contact metal (4), a gate oxide layer (5), an N + short circuit region (6), a P + anode region (7), an N-drift region (8), a P-drift region (9), a buffer layer (10), a substrate (11) and a cathode contact metal (12), wherein,

the buffer layer (10), the P-drift region (9), the N-drift region (8) and the P + anode region (7) are sequentially arranged on the upper surface of the substrate (11), and the cathode contact metal (12) is arranged on the lower surface of the substrate (11);

the N + short circuit region (6) is arranged at the upper right part inside the P + anode region (7) and is flush with the upper surface of the P + anode region (7);

the gate oxide layer (5) comprises two parts which are spaced from each other, one part is arranged at the right side of the P + anode region (7) and extends to the upper part of the N + short-circuit region (6) and the upper part of an N-drift region (8), and the other part is arranged at the left side of the N-drift region (8) and extends to the upper part of the P + anode region (7) and the upper part of the P-drift region (9);

the opening grid contact metal (4) and the closing grid contact metal (3) are respectively arranged on the surface of the grid oxide layer (5) and partially cover the grid oxide layer (5);

the anode contact metal (2) is arranged on the upper surfaces of the P + anode region (7) and the N + short circuit region (6) and is positioned between two parts of the gate oxide layer (5);

the passivation layer (1) is arranged on partial upper surfaces of the turn-off grid contact metal (3), the turn-on grid contact metal (4) and the anode contact metal (2).

2. The P-type silicon carbide thyristor according to claim 1, further comprising a surface thin layer of Si by carbon implantation in a device turn-on gate region ₃N ₄A process forming a high lifetime region (13).

3. The P-type silicon carbide thyristor according to claim 1 or 2, wherein the area ratio of the turn-on gate contact metal (4) to the turn-off gate contact metal (3) is 3:1 to 5: 1.

4. A preparation method of a P-type silicon carbide thyristor based on double MOS gate control is characterized by comprising the following steps:

(a) sequentially epitaxially growing a buffer layer, a P-drift region, an N-drift region and a P + anode region on an N + silicon carbide substrate;

(b) etching the silicon carbide substrate to form a gate-off table top and a gate-on table top;

(c) performing ion implantation on one side of the gate-off mesa to form an N + short-circuit region;

(d) preparing a high-service-life area by adopting a carbon ion implantation process;

(e) using a thin layer of Si ₃N ₄Preparing a gate oxide layer by deposition and high-temperature thermal oxidation processes;

(f) depositing metal to form a cathode contact metal layer, an anode contact metal layer and a double-grid contact metal layer respectively;

(g) and depositing a passivation layer to complete the manufacture of the device.

5. The method of claim 4, wherein step (a) comprises:

(a1) carrying out RCA standard cleaning on the N + type silicon carbide substrate;

(a2) respectively epitaxially growing the buffer layer, the P-drift region, the N-drift region and the P + anode region on the N + type silicon carbide substrate by adopting a low-pressure hot-wall chemical vapor deposition method; wherein the epitaxial temperature is 1600 ℃, the pressure is 100mbar, the reaction gases are silane and propane, and the carrier gas is pure hydrogen.

6. The method of claim 4, wherein step (b) comprises:

(b1) performing magnetron sputtering on a layer of Ti film on the silicon carbide substrate to be used as an etching mask;

(b2) etching two sides of a P + anode region of the device by adopting an ICP (inductively coupled plasma) etching process to form a cut-off grid table surface and an open grid table surface, wherein the etching depth of one side of the cut-off grid is 3.2-4.1 mu m, and the etching depth of one side of the open grid is 7.0-8.5 mu m;

(b3) and removing the etching mask and cleaning the light forming sheet.

7. The method of claim 4, wherein step (c) comprises:

(c1) depositing a layer of SiO with the thickness of 1.0 mu m on the whole silicon carbide surface by adopting a low-pressure chemical vapor deposition mode ₂The N + short circuit area is used as a barrier layer for nitrogen ion implantation of the N + short circuit area, and the N + implantation area is formed by photoetching and etching;

(c2) performing nitrogen ion implantation at 600 ℃;

(c3) and cleaning and drying the silicon carbide surface in sequence by adopting an RCA cleaning standard.

8. The method of claim 4, wherein step (d) comprises:

(d1) blocking other regions with photoresist, and depositing a layer of SiO 3.0 μm thick on the whole surface of silicon carbide by low pressure chemical vapor deposition ₂As a barrier layer for carbon ion implantation in the long-life region, and forming a carbon ion implantation region by photoetching and etching;

(d2) blocking other areas with photoresist, and implanting carbon ions at 600 deg.C;

(d3) and sequentially cleaning, drying and protecting a C film on the surface of the silicon carbide by adopting an RCA cleaning standard, and carrying out ion activation annealing for 1h in an argon atmosphere at 1800 ℃ to form a high-service-life region.

9. The method of claim 4, wherein step (f) comprises:

(f1) depositing Ni/Ti/Al alloy on the back of the whole silicon carbide wafer to form a cathode contact metal layer;

(f2) coating photoresist on the front side of the silicon carbide wafer, and forming a P + ohmic contact area through development; depositing Ni/Ti/Al alloy on the silicon carbide chip, and stripping by ultrasonic wave to form an anode contact metal layer on the front surface;

(f3) and coating photoresist on the front surface of the silicon carbide wafer, forming a double-gate region through development, and depositing Al alloy to form a double-gate contact metal layer.

10. The method of claim 9, wherein step (f1) and step (f2) are both followed by:

the silicon carbide wafer was annealed at a temperature of 1000 c for 3 minutes in a nitrogen atmosphere to form an ohmic contact.

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a P-type silicon carbide thyristor based on dual MOS gate control and a preparation method thereof.

Background

With the rapid development of semiconductor technology, the third generation semiconductor material attracts people's interest with its excellent characteristics, wherein, silicon carbide has the advantages of high carrier saturation mobility, high temperature resistance, high thermal conductivity and the like, so that the silicon carbide device has more advantages under the conditions of high temperature, high pressure, high speed and the like, thereby being widely applied.

Silicon carbide thyristors have very high voltage blocking capability, excellent current handling capability and high on-state di/dt capability as high-voltage high-power devices, and thus are widely used in power electronic equipment such as high-power inverters, high-voltage pulse switches, uninterruptible power supplies and the like. A conventional sic thyristor structure is shown in fig. 1, wherein a region 1 is an anode contact metal, a region 2 is a P + anode region, a region 3 is a gate contact metal, and a region 4 is a cathode contact metal, and the gate contact metal controls the on and off of the device by applying a pulse current signal to the gate, and during this process, the gate metals on both sides perform the same function.

However, the front-end control circuit of the conventional silicon carbide thyristor is complex and consumes high power due to the need of current drive control; in addition, the PN junction type gate structure of the conventional silicon carbide thyristor makes the optimization of the turn-on time and the turn-off time of the device difficult, which is not favorable for the turn-on and the turn-off of the device in a high-speed working state.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a P-type silicon carbide thyristor based on dual MOS gate control and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:

a P-type silicon carbide thyristor based on double MOS gate control comprises: a passivation layer, an anode contact metal, a gate off contact metal, a gate on contact metal, a gate oxide, an N + short circuit region, a P + anode region, an N-drift region, a P-drift region, a buffer layer, a substrate, and a cathode contact metal,

the buffer layer, the P-drift region, the N-drift region and the P + anode region are sequentially arranged on the upper surface of the substrate, and the cathode contact metal is arranged on the lower surface of the substrate;

the N + short circuit area is arranged at the upper right part inside the N + anode area and is flush with the upper surface of the P + anode area;

the gate oxide layer comprises two parts which are spaced from each other, one part of the gate oxide layer is arranged at the right side of the P + anode region and extends to the upper part of the N + short circuit region and the upper part of the N-drift region, and the other part of the gate oxide layer is arranged at the left side of the N-drift region (8) and extends to the upper part of the P + anode region and the upper part of the P-drift region;

the opening grid contact metal and the closing grid contact metal are respectively arranged on the surface of the grid oxide layer and partially cover the grid oxide layer;

the anode contact metal is arranged on the upper surfaces of the P + anode region and the N + short circuit region and is positioned between the two parts of the gate oxide layer;

the passivation layer is disposed on a portion of upper surfaces of the off gate contact metal, the on gate contact metal, and the anode contact metal.

In one embodiment of the invention, the method further comprises the steps of performing carbon implantation and surface thin layer Si in the device opening gate region ₃N ₄And forming a high-life area by the process.

In one embodiment of the invention, the area ratio of the opening gate contact metal to the closing gate contact metal is 3:1 to 5: 1.

Another embodiment of the present invention further provides a method for preparing a P-type silicon carbide thyristor based on dual MOS gate control, including the following steps:

(a) sequentially epitaxially growing a buffer layer, a P-drift region, an N-drift region and a P + anode region on an N + silicon carbide substrate;

(b) etching the silicon carbide substrate to form a gate-off table top and a gate-on table top;

(c) performing ion implantation on one side of the gate-off mesa to form an N + short-circuit region;

(d) preparing a high-service-life area by adopting a carbon ion implantation process;

(e) using a thin layer of Si ₃N ₄Preparing a gate oxide layer by deposition and high-temperature thermal oxidation processes;

(f) depositing metal to form a cathode contact metal layer, an anode contact metal layer and a double-grid contact metal layer respectively;

(g) and depositing a passivation layer to complete the manufacture of the device.

In one embodiment of the present invention, step (a) comprises:

(a1) carrying out RCA standard cleaning on the N + type silicon carbide substrate;

(a2) respectively epitaxially growing the buffer layer, the P-drift region, the N-drift region and the P + anode region on the N + type silicon carbide substrate by adopting a low-pressure hot-wall chemical vapor deposition method; wherein the epitaxial temperature is 1600 ℃, the pressure is 100mbar, the reaction gases are silane and propane, and the carrier gas is pure hydrogen.

In one embodiment of the present invention, step (b) comprises:

(b1) performing magnetron sputtering on a layer of Ti film on the silicon carbide substrate to be used as an etching mask;

(b2) etching two sides of a P + anode region of the device by adopting an ICP (inductively coupled plasma) etching process to form a cut-off grid table surface and an open grid table surface, wherein the etching depth of one side of the cut-off grid is 3.2-4.1 mu m, and the etching depth of one side of the open grid is 7.0-8.5 mu m;

(b3) and removing the etching mask and cleaning the light forming sheet.

In one embodiment of the present invention, step (c) comprises:

(c1) depositing a layer of SiO with the thickness of 1.0 mu m on the whole silicon carbide surface by adopting a low-pressure chemical vapor deposition mode ₂The N + short circuit area is used as a barrier layer for nitrogen ion implantation of the N + short circuit area, and the N + implantation area is formed by photoetching and etching;

(c2) performing nitrogen ion implantation at 600 ℃;

(c3) and cleaning and drying the silicon carbide surface in sequence by adopting an RCA cleaning standard.

In one embodiment of the present invention, step (d) comprises:

(d1) blocking other regions with photoresist, and depositing a layer of SiO 3.0 μm thick on the whole surface of silicon carbide by low pressure chemical vapor deposition ₂As a barrier layer for carbon ion implantation in the long-life region, and forming a carbon ion implantation region by photoetching and etching;

(d2) blocking other areas with photoresist, and implanting carbon ions at 600 deg.C;

(d3) and sequentially cleaning, drying and protecting a C film on the surface of the silicon carbide by adopting an RCA cleaning standard, and carrying out ion activation annealing for 1h in an argon atmosphere at 1800 ℃ to form a high-service-life region.

In one embodiment of the present invention, step (f) comprises:

(f1) depositing Ni/Ti/Al alloy on the back of the whole silicon carbide wafer to form a cathode contact metal layer;

(f2) coating photoresist on the front side of the silicon carbide wafer, and forming a P + ohmic contact area through development; depositing Ni/Ti/Al alloy on the silicon carbide chip, and stripping by ultrasonic wave to form an anode contact metal layer on the front surface;

(f3) and coating photoresist on the front surface of the silicon carbide wafer, forming a double-gate region through development, and depositing Al alloy to form a double-gate contact metal layer.

In one embodiment of the present invention, step (f1) and step (f2) are both followed by:

the silicon carbide wafer was annealed at a temperature of 1000 c for 3 minutes in a nitrogen atmosphere to form an ohmic contact.

The invention has the beneficial effects that:

1. the double-MOS-gate-control-based P-type silicon carbide thyristor provided by the invention adopts an MOS gate control structure, the drive control of a device is changed from a traditional current mode to a voltage mode, and the structure is favorable for the design and realization of a front-end control circuit and the reduction of power consumption;

2. the double-MOS gate structure is introduced into the P-type silicon carbide thyristor based on double-MOS gate control, the turn-on gate and the turn-off gate work independently to control the turn-on and turn-off of the device respectively, so that the device can be turned on and off rapidly in a switch or pulse working state, and the working frequency of the device can be improved remarkably;

3. the P-type silicon carbide thyristor based on dual MOS gate control provided by the invention is subjected to carbon injection and surface thin layer Si in the device conducting region ₃N ₄The process manufactures a long service life region, thereby effectively reducing the composite action of the SiC body and the interface, improving the current density during conduction and reducing the on-resistance.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a schematic diagram of a conventional silicon carbide thyristor structure provided by an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a P-type silicon carbide thyristor based on dual MOS gate control according to an embodiment of the present invention;

fig. 3 is a schematic flow chart of a method for manufacturing a P-type silicon carbide thyristor based on dual MOS gate control according to an embodiment of the present invention;

fig. 4a to 4n are schematic diagrams of a process flow of manufacturing a P-type silicon carbide thyristor based on dual MOS gate control according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.