DVI adapter
阅读说明：本技术 一种dvi转接头 (DVI adapter ) 是由 王宏利 于 2019-12-03 设计创作，主要内容包括：本发明涉及连接器技术领域,公开了一种DVI转接头,其包括：中空的壳体；设置在所述壳体内部的电路板,所述电路板上设有电源电路、信号检测电路以及防止电子器件被击穿的保护电路；接口公头,外露于所述壳体的一端,所述接口公头与所述壳体连接,所述接口公头的两侧分别设有固定螺杆；接口母头,外露于所述壳体的远离所述接口公头的一端,所述接口母头与所述壳体连接,所述接口母头的两侧分别设有固定螺母；信号指示灯,设置在所述壳体的外侧,所述信号指示灯位于所述接口公头与所述接口母头之间,所述信号指示灯的下端与所述电路板连接。本发明的DVI转接头结构紧凑,装配稳定可靠,且能够对连接后的电子产品起到有效的保护。(The invention relates to the technical field of connectors, and discloses a DVI adapter, which comprises: a hollow housing; the circuit board is arranged in the shell and is provided with a power circuit, a signal detection circuit and a protection circuit for preventing an electronic device from being broken down; the interface male head is exposed at one end of the shell and connected with the shell, and two sides of the interface male head are respectively provided with a fixing screw; the interface female head is exposed at one end of the shell far away from the interface male head and connected with the shell, and two sides of the interface female head are respectively provided with a fixing nut; the signal indicator lamp is arranged on the outer side of the shell and located between the interface male head and the interface female head, and the lower end of the signal indicator lamp is connected with the circuit board. The DVI adapter has a compact structure, is stable and reliable to assemble, and can effectively protect connected electronic products.)
1. A DVI adapter, comprising:
a hollow housing;
the circuit board is arranged in the shell and is provided with a power circuit, a signal detection circuit and a protection circuit for preventing an electronic device from being broken down;
the interface male head is exposed at one end of the shell and connected with the shell, and two sides of the interface male head are respectively provided with a fixing screw;
the interface female head is exposed at one end of the shell far away from the interface male head and connected with the shell, and two sides of the interface female head are respectively provided with a fixing nut;
the signal indicator lamp is arranged on the outer side of the shell and located between the interface male head and the interface female head, and the lower end of the signal indicator lamp is connected with the circuit board.
2. The DVI adapter of claim 1 wherein:
the power supply circuit comprises an input end, a voltage stabilizer and an output end, wherein a first voltage at the input end is converted into a second voltage at the output end through the voltage stabilizer.
3. The DVI adapter of claim 1 wherein:
the signal detection circuit is connected with the signal indicator lamp, the differential clock signal enters the signal detection circuit, the signal detection circuit detects the threshold voltage of the differential clock signal, the signal indicator lamp is not turned on when the differential clock signal input by detection is smaller than the threshold voltage, and the signal indicator lamp is turned on when the differential clock signal input by detection is larger than the threshold voltage.
4. The DVI adapter of claim 1 wherein: four electrostatic protectors are arranged in the protection circuit and are respectively connected with the interface male head and the interface female head.
5. The DVI adapter of any one of claims 1-4 wherein:
the shell comprises a first shell and a second shell, and the first shell and the second shell are matched and clamped to clamp the circuit board between the first shell and the second shell.
6. The DVI adapter of claim 5 wherein:
a first groove is formed in the inner side of one end of the shell, and a second groove is formed in the inner side of the other end of the shell;
the interface male head comprises an interface male head body and a plurality of first pins, a first boss matched with the first groove is arranged on the outer side of the interface male head body, and the plurality of first pins are connected with the circuit board;
the interface female head comprises an interface female head body and a plurality of second pins, a second boss matched with the second groove is arranged on the outer side of the interface female head body, and the plurality of second pins are connected with the circuit board;
the interface male head and the interface female head are clamped and fixed by the first shell and the second shell respectively.
7. The DVI adapter of claim 6 wherein:
a first screw hole and a second screw hole are respectively formed in two sides of the first shell, a first nut and a second nut are respectively arranged on two sides of one end, close to the first shell, of the second shell, and a first screw groove and a second screw groove are respectively formed in two sides of the circuit board;
a first screw penetrates through the first screw hole, the first screw groove and the first nut in sequence to fixedly connect the first shell with the second shell;
and a second screw penetrates through the second screw hole, the second screw groove and the second nut in sequence to fixedly connect the first shell with the second shell.
8. The DVI adapter of claim 7 wherein:
the two ends of the shell are symmetrically provided with a first cavity and a second cavity, the third cavity penetrates through the first cavity and the second cavity, and the first pin and the second pin are both located in the third cavity.
9. The DVI adapter of claim 8 wherein:
the cavity heights of the first cavity and the second cavity are both larger than the cavity height of the third cavity.
10. The DVI adapter of claim 9 wherein:
and positioning bosses are arranged at the inner edges of the ports of the first cavity and the second cavity in an inward protruding manner.
Technical Field
The invention relates to the technical field of connectors, in particular to a DVI adapter.
Background
Digital Visual Interface (DVI) is an international open interface standard, and has wide application in PC, DVD, High Definition Television (HDTV), high definition projector, and other devices. The DVI is used for transmitting digital signals based on a TMDS (Transition minimized differential Signaling) technology, the TMDS applies an advanced coding algorithm to encode 8-bit data (each road color signal in R, G, B) into 10-bit data (including line field synchronization information, clock information, data DE, error correction and the like) through minimum conversion, and after DC balance, the data are transmitted by adopting differential signals.
Disclosure of Invention
In order to solve the technical problems, the invention provides the DVI adapter which has a compact structure and stable and reliable assembly and can effectively protect connected electronic products.
The technical scheme provided by the invention is as follows:
a DVI adapter, comprising:
a hollow housing;
the circuit board is arranged in the shell and is provided with a power circuit, a signal detection circuit and a protection circuit for preventing an electronic device from being broken down;
the interface male head is exposed at one end of the shell and connected with the shell, and two sides of the interface male head are respectively provided with a fixing screw;
the interface female head is exposed at one end of the shell far away from the interface male head and connected with the shell, and two sides of the interface female head are respectively provided with a fixing nut;
the signal indicator lamp is arranged on the outer side of the shell and located between the interface male head and the interface female head, and the lower end of the signal indicator lamp is connected with the circuit board.
Preferably, the power supply circuit includes an input terminal, a voltage regulator and an output terminal, and a first voltage at the input terminal is converted into a second voltage at the output terminal by the voltage regulator.
Further preferably, the signal detection circuit is connected to the signal indicator, the differential clock signal enters the signal detection circuit, the signal detection circuit detects a threshold voltage of the differential clock signal, the signal indicator is not turned on when the differential clock signal is detected to be input and smaller than the threshold voltage, and the signal indicator is turned on when the differential clock signal is detected to be input and larger than the threshold voltage.
Further preferably, four electrostatic protectors are arranged in the protection circuit, and the four electrostatic protectors are respectively connected with the interface male head and the interface female head.
Further preferably, the housing includes a first housing and a second housing, and the first housing and the second housing are adapted to be engaged with each other to clamp the circuit board therebetween.
Further preferably, a first groove is formed in the inner side of one end of the shell, and a second groove is formed in the inner side of the other end of the shell;
the interface male head comprises an interface male head body and a plurality of first pins, a first boss matched with the first groove is arranged on the outer side of the interface male head body, and the plurality of first pins are connected with the circuit board;
the interface female head comprises an interface female head body and a plurality of second pins, a second boss matched with the second groove is arranged on the outer side of the interface female head body, and the plurality of second pins are connected with the circuit board;
the interface male head and the interface female head are clamped and fixed by the first shell and the second shell respectively.
Further preferably, two sides of the first shell are respectively provided with a first screw hole and a second screw hole, two sides of the second shell close to one end of the first shell are respectively provided with a first nut and a second nut, and two sides of the circuit board are respectively provided with a first screw groove and a second screw groove;
a first screw penetrates through the first screw hole, the first screw groove and the first nut in sequence to fixedly connect the first shell with the second shell;
and a second screw penetrates through the second screw hole, the second screw groove and the second nut in sequence to fixedly connect the first shell with the second shell.
Further preferably, a first cavity and a second cavity are symmetrically arranged at two ends of the shell, a third cavity penetrates through the first cavity and the second cavity, and the first pin and the second pin are both located in the third cavity.
Further preferably, the cavity heights of the first cavity and the second cavity are both greater than the cavity height of the third cavity.
Further preferably, the inner edges of the ports of the first cavity and the second cavity are both provided with positioning bosses protruding inwards.
Compared with the prior art, the DVI adapter has the beneficial effects that:
the DVI adapter is compact in structure and stable and reliable in assembly by arranging the circuit board in the hollow shell, arranging the interface male head at one end of the shell and leaking out of the shell, arranging the fixing screw rods at two sides of the interface male head respectively, arranging the interface female head at the other end of the shell and leaking out of the shell, arranging the fixing nuts at two sides of the interface female head respectively, and arranging the signal indicator lamp at the outer side of the shell; the circuit board is provided with the power supply circuit, the signal detection circuit and the protection circuit for preventing the electronic device from being broken down, so that the connected electronic product can be effectively protected.
Drawings
The foregoing features, technical features, advantages and embodiments are further described in the following detailed description of the preferred embodiments, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a first view angle of the DVI adapter according to this embodiment;
fig. 2 is a schematic structural diagram of another view angle of the DVI adapter according to this embodiment;
fig. 3 is an exploded view of the DVI adapter of the present embodiment;
fig. 4 is an exploded view of another view of the DVI adapter of the present embodiment;
fig. 5 is a power circuit diagram of the DVI adapter of the present embodiment;
fig. 6 is a circuit diagram of a signal detection circuit of the DVI adapter of the present embodiment;
fig. 7 is a circuit diagram of the first and second pin connections of the DVI adapter of the present embodiment;
fig. 8 is a diagram of an esd protection circuit of the DVI adapter of this embodiment.
The reference numbers illustrate:
1-shell, 11-first shell, 111-first screw hole, 112-second screw hole, 12-second shell, 121-first nut, 122-second nut, 2-circuit board, 21-first screw groove, 22-second screw groove, 3-interface male head, 31-first fixing screw rod, 32-second fixing screw rod, 33-first boss, 34-first pin, 4-interface female head, 41-first fixing nut, 42-second fixing nut, 43-second boss, 44-second pin, 5-signal indicator light, 61-first screw and 62-second screw.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
In the embodiments shown in the drawings, the directions such as up, down, left, right, front, and rear are used to explain the structure and movement of various components of the present invention not absolutely but relatively. These illustrations are appropriate when these components are in the positions shown in the figures. If the description of the positions of these components changes, the indication of these directions changes accordingly.
In addition, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not intended to indicate or imply relative importance.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
In this embodiment, as shown in fig. 1 to 4, this embodiment provides a DVI adapter, which includes:
Further, as shown in fig. 1 to 4, two sides of the
The first cavity and the second cavity are symmetrically arranged at two ends of the
Further, as shown in fig. 5, the power circuit includes an input terminal, a regulator U6, and an output terminal, wherein a first voltage at the input terminal is converted into a second voltage at the output terminal by the regulator U6. The voltage of the input end is 5V, the voltage stabilizer U6 is an RT9193-33GB voltage stabilizer, and the voltage of the output end is 3.3V. The input end is connected with VIN end and EN end of the voltage stabilizer U6, the output end is connected with a 4.7uF capacitor C55 which is grounded and a 0.1uF capacitor C56 which is grounded between the output end and the voltage stabilizer U6, GND end of the voltage stabilizer U6 is grounded, BP end of the voltage stabilizer U6 is connected with a 22nF capacitor C74 which is grounded, VOUT end of the voltage stabilizer U6 is connected with the output end, and the output end is connected with the 4.7uF capacitor C57 which is connected in parallel and the 0.1uF capacitor C75 and then is grounded. The 5V power supply at the input end is converted into the 3.3V power supply at the output end by the voltage regulator U6 for the use of a later stage IC.
As shown in fig. 6, the signal detection circuit is connected to the signal indicator lamp, the differential clock signal enters the signal detection circuit, the threshold voltage of the differential clock signal is detected by the signal detection circuit, the signal indicator lamp is not turned on when the input differential clock signal is detected to be less than the threshold voltage, and the signal indicator lamp is turned on when the input differential clock signal is detected to be greater than the threshold voltage. Specifically, the input end of the LED1 is connected with a 5V power supply, the output end of the LED1 is connected with the DIS end and the LOS end of a voltage regulator U10 through a resistor R18 with 1K ohm, and the model of the voltage regulator U10 is I7330M. The GND terminal of the voltage stabilizer U10 is grounded, the LOS terminal of the voltage stabilizer U10 is connected with 3.3V voltage through an 8.15K ohm resistor R8, and the VCC terminal of the voltage stabilizer U10 is connected with 3.3V voltage. The differential clock signal is connected to the IN + end and the IN-end of the voltage stabilizer U10, the IN + end and the IN-end of the voltage stabilizer U10 are respectively connected with a 50 ohm resistor to ensure impedance matching of the differential signal, the TH end of the voltage stabilizer U10 is connected with 3.3V voltage through a 7.59K ohm resistor R3, and threshold voltage for detecting the differential signal is set. When the difference clock signal input by detection is smaller than the threshold voltage, the LOS end of the voltage stabilizer U10 outputs high level, the LED lamp cannot be lightened at the moment, and the video signal can be judged not to be accessed into the DVI interface; when the differential clock signal of the detection input is larger than the threshold voltage, the LOS end of the voltage stabilizer U10 outputs low level, the LED lamp is lightened at the moment, and meanwhile, the video signal is judged to be accessed into the DVI interface.
As shown in fig. 7 and 8, the protection circuit is provided with four electrostatic protectors, the four electrostatic protectors are respectively an electrostatic protector U1, an electrostatic protector U7, an electrostatic protector U8 and an electrostatic protector U9, and the interface male connector J1 and the interface female connector J2 are connected through the four electrostatic protectors. Specifically, the male interface J1 is DVI-LJDVIM, and the female interface J2 is DVI-LJDVIF. TMDS2-, TMDS2+, TMDS4-, TMDS4+, DDC CLK, DDC DATA, TMDS1-, TMDS1+, TMDS3-, TMDS3+, HPDET, TMDS0-, TMDS0+, TMDS5-, TMDS5+, TMDS CLK-end of the interface male head J1 are respectively connected with the TMDS2-, TMDS2+, TMDS4-, TMDS4+, DDC CLK, DDC DATA, TMDS1-, TMDS1+, TMDS3-, TMDS3+, HPTMDS 0-, TMDS0+, TMDS5-, TMDS5+, TMDS CLK-end of the interface female head J2 in turn. 2/4GND, a-V SYNC, 1/3GND, 0/5GND, CLK GND, GND1, GND2 and GND4 of the male interface J1 are grounded, and 2/4GND, a-V SYNC, 1/3GND, 0/5GND, CLK GND, GND3 and GND5 of the female interface J2 are grounded. The +5V of the male joint J1 of interface connects the 5V power, and the +5V of the female joint J2 of interface connects the 5V power.
As shown in fig. 8, the electrostatic protectors U1, U7, U8, and U9 are Rclamp 0524. I1 of an electrostatic protector U1 is connected with TMDS2 of an interface male head J1, I2 of the electrostatic protector U1 is connected with TMDS2+ of an interface male head J1, I3 of the electrostatic protector U1 is connected with TMDS4+ of the interface male head J1, I4 of the electrostatic protector U1 is connected with TMDS4+ of the interface male head J1, GND of the electrostatic protector U1 is grounded, O1 of the electrostatic protector U1 is connected with TMDS2+ of an interface female head J2, O2 of the electrostatic protector U1 is connected with TMDS2+ of the interface female head J2, O3 of the electrostatic protector U1 is connected with S4+ of the interface female head J2, and O4 of the electrostatic protector U1 is connected with S4+ of the interface female head J2. I1 of an electrostatic protector U7 is connected with TMDS1 of an interface male head J1, I2 of the electrostatic protector U7 is connected with TMDS1+ of an interface male head J1, I3 of the electrostatic protector U7 is connected with TMDS0+ of the interface male head J1, I4 of the electrostatic protector U7 is connected with TMDS0+ of the interface male head J1, GND of the electrostatic protector U7 is grounded, O1 of the electrostatic protector U7 is connected with TMDS1+ of an interface female head J2, O2 of the electrostatic protector U7 is connected with TMDS1+ of the interface female head J2, O3 of the electrostatic protector U7 is connected with S0+ of the interface female head J2, and O4 of the electrostatic protector U7 is connected with S0+ of the interface female head J2. I1 of an electrostatic protector U8 is connected with TMDS5 of an interface male head J1, I2 of the electrostatic protector U8 is connected with TMDS5+ of an interface male head J1, I3 of the electrostatic protector U8 is connected with TMDS3+ of the interface male head J1, I4 of the electrostatic protector U8 is connected with TMDS3+ of the interface male head J1, GND of the electrostatic protector U8 is grounded, O1 of the electrostatic protector U8 is connected with TMDS5+ of an interface female head J2, O2 of the electrostatic protector U8 is connected with TMDS5+ of the interface female head J2, O3 of the electrostatic protector U8 is connected with S3+ of the interface female head J2, and O4 of the electrostatic protector U8 is connected with S3+ of the interface female head J2. I1 of the electrostatic protector U9 is connected with TMDS _ CLK + of the interface male head J1, I2 of the electrostatic protector U9 is connected with TMDS _ CLK of the interface male head J1, GND of the electrostatic protector U9 is grounded, O1 of the electrostatic protector U9 is connected with TMDS _ CLK + of the interface female head J2, and O2 of the electrostatic protector U9 is connected with TMDS _ CLK-of the interface female head J2. Accomplish DVI's switching through public first J1 of interface, female first J2 of interface, use electrostatic protection ware U1, electrostatic protection ware U7, electrostatic protection ware U8, electrostatic protection ware U9 to realize the electrostatic protection of port, prevent that the static from causing the loss to equipment.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or recited in detail in a certain embodiment.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
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