阅读说明：本技术 失锁检测器 (Lock loss detector ) 是由 A·玛尼安 R·吉普塔 于 2019-07-26 设计创作，主要内容包括：本申请公开了失锁检测器。一种失锁检测电路包括检测电路(201)和脉冲累加电路(220)。检测电路包括第一触发器(202)、第二触发器(204)和第三触发器(218)。第一触发器(208)被配置为将数据流(110)同步到时钟信号(112)的第一边缘。第二触发器(204)被配置为将数据流(110)同步到时钟信号(112)的第二边缘。第三触发器(218)由数据流(110)计时,并且被配置为在数据流(110)的边缘处存储第一触发器(202)和第二触发器(202)的组合输出。脉冲累加电路(220)耦合到检测电路(201)。脉冲累加电路(220)被配置为收集由第三触发器(218)生成的脉冲。(The application discloses an out-of-lock detector. An out-of-lock detection circuit includes a detection circuit (201) and a pulse summation circuit (220). The detection circuit includes a first flip-flop (202), a second flip-flop (204), and a third flip-flop (218). The first flip-flop (208) is configured to synchronize the data stream (110) to a first edge of the clock signal (112). The second flip-flop (204) is configured to synchronize the data stream (110) to a second edge of the clock signal (112). The third flip-flop (218) is clocked by the data stream (110) and is configured to store a combined output of the first flip-flop (202) and the second flip-flop (202) at an edge of the data stream (110). The pulse accumulation circuit (220) is coupled to the detection circuit (201). The pulse accumulation circuit (220) is configured to collect pulses generated by the third flip-flop (218).)

1. An out-of-lock detection circuit, comprising:

a detection circuit, comprising:

a first flip-flop configured to synchronize a data stream to a first edge of a clock signal;

a second flip-flop configured to synchronize the data stream to a second edge of the clock signal;

a third flip-flop clocked by the data stream and configured to store a combined output of the first flip-flop and the second flip-flop at an edge of the data stream; and

a pulse accumulation circuit coupled to the detection circuit, the pulse accumulation circuit configured to collect pulses generated by the third flip-flop.

2. The out-of-lock detection circuit of claim 1, further comprising a delay circuit configured to delay the data stream by a bit time of the data stream.

3. The out-of-lock detection circuit of claim 2, wherein a clock input of the third flip-flop is coupled to an output of the delay circuit.

4. The loss of lock detection circuit of claim 1, further comprising an exclusive nor gate coupled to the first flip-flop, the second flip-flop, and the third flip-flop; wherein the exclusive nor gate is configured to combine an output of the first flip-flop with an output of the second flip-flop to generate an input to the third flip-flop.

5. The out-of-lock detection circuit of claim 1, wherein the pulse accumulation circuit comprises a counter configured to count pulses generated by the third flip-flop.

6. The out-of-lock detection circuit of claim 1, wherein the pulse summation circuit comprises a capacitor configured to be charged by a pulse generated by the third flip-flop.

7. The out-of-lock detection circuit of claim 1, further comprising a comparator configured to compare a voltage across the capacitor to a threshold voltage.

8. A method for detecting a loss of lock, comprising:

synchronizing the data stream to a rising edge of a clock to produce a first half rate data stream;

synchronizing the data stream to a falling edge of the clock to produce a second half rate data stream;

combining the first half-rate data stream and the second half-rate data stream;

clocking the combined first and second half-rate data streams into a trigger; and

the output pulses of the flip-flops are accumulated to detect loss of lock.

9. The method of claim 8, further comprising delaying the data stream by a bit time of the data stream to generate a clock that clocks the flip-flop.

10. The method of claim 8, wherein the combining comprises providing the first half-rate data stream and the second half-rate data stream to an exclusive nor circuit.

11. The method of claim 8, wherein the accumulating comprises counting pulses generated by the trigger.

12. The method of claim 11, further comprising identifying loss of lock by counting a predetermined number of pulses within a predetermined time interval.

13. The method of claim 8, wherein the accumulating comprises charging a capacitor with a pulse generated by the trigger.

14. The method of claim 13, further comprising identifying loss of lock by comparing a voltage across the capacitor to a threshold voltage.

15. An out-of-lock detection circuit, comprising:

a first flip-flop, comprising:

a data input terminal; and

an output terminal;

a second flip-flop comprising:

a data input terminal coupled to the data input of the first flip-flop; and

an output terminal;

an exclusive nor gate, comprising:

a first input coupled to the output terminal of the first flip-flop;

a second input coupled to the output terminal of the second flip-flop; and

an output terminal;

a third flip-flop comprising:

a data input terminal coupled to an output of the exclusive nor gate;

a clock input terminal coupled to the data input terminal of the first flip-flop and the data input terminal of the second flip-flop; and

and an output terminal.

16. The out-of-lock detection circuit of claim 15, further comprising a delay circuit comprising:

an input terminal coupled to the data input terminal of the first flip-flop and the data input terminal of the second flip-flop; and

an output terminal coupled to the clock input terminal of the third flip-flop.

17. The out-of-lock detection circuit of claim 15, further comprising a counter coupled to the output terminal of the third flip-flop.

18. The out-of-lock detection circuit of claim 15, further comprising a filter circuit coupled to the output terminal of the third flip-flop.

19. The out-of-lock detection circuit of claim 18, wherein the filter circuit comprises a capacitor comprising:

a first terminal coupled to the output terminal of the third flip-flop; and

a second terminal coupled to ground.

20. The out-of-lock detection circuit of claim 18, wherein the filter circuit comprises a comparator comprising:

a first input terminal coupled to the first terminal of the capacitor; and

a second input terminal coupled to a threshold voltage source.

Background

In many communication systems, data is transmitted from one device to another without an accompanying clock signal. During transmission, the signal carrying the data may become jittery and difficult to decrypt and process by the receiving device. Accordingly, many systems utilize Clock and Data Recovery (CDR) circuits to retime an input signal and transmit the retimed signal to a receiving device. This requires the CDR circuit to generate a clock that locks to the frequency of the transmitted data. In many systems, the CDR circuit detects the frequency of the incoming signal and phase aligns the clock signal to the incoming signal. The incoming signal is then retimed with the clean clock that the CDR circuit has generated. The retimed signal may then be output to a receiving device for further processing.

Disclosure of Invention

An out-of-lock detection circuit for use with a half-rate clock and data recovery circuit is disclosed. In one example, the out-of-lock detection circuit includes a detection circuit and a pulse accumulation circuit. The detection circuit includes a first flip-flop, a second flip-flop, and a third flip-flop. The first flip-flop is configured to synchronize the data stream to a first edge of the clock signal. The second flip-flop is configured to synchronize the data stream to a second edge of the clock signal. The third flip-flop is clocked by the data stream and is configured to store a combined output of the first flip-flop and the second flip-flop at an edge of the data stream. The pulse accumulation circuit is coupled to the detection circuit. The pulse accumulation circuit is configured to collect pulses generated by the third flip-flop.

In another example, a method for detecting a loss of lock includes synchronizing a data stream to a rising edge of a clock to produce a first half rate data stream and synchronizing the data stream to a falling edge of the clock to produce a second half rate data stream. The first half rate data stream and the second half rate data stream are combined. The combined first half rate data stream and second half rate data stream are clocked into the flip-flop. The output pulses of the flip-flops are accumulated to detect loss of lock.

In another example, an out-of-lock detection circuit includes a first flip-flop, a second flip-flop, an exclusive nor gate, and a third flip-flop. The first flip-flop includes a data input terminal and an output terminal. The second flip-flop includes a data input terminal and an output terminal. The exclusive nor gate includes a first input, a second input, and an output terminal. The first input is coupled to an output terminal of the first flip-flop. The second input is coupled to the output terminal of the second flip-flop. The third flip-flop includes a data input terminal, a clock input terminal, and an output terminal. The data input terminal of the third flip-flop is coupled to the output of the exclusive nor gate. The clock input terminal of the third flip-flop is coupled to the data input terminal of the first flip-flop and the data input terminal of the second flip-flop.

Drawings

For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

FIG. 1 illustrates a block diagram of a half rate Clock and Data Recovery (CDR) system according to the present disclosure;

FIG. 2 shows a schematic diagram of an example of an out-of-lock detection circuit suitable for use in a half-rate CDR circuit according to the present disclosure;

FIGS. 3 and 4 illustrate examples of pulse summation circuits suitable for use in an out-of-lock detection circuit in accordance with the present invention;

FIGS. 5 and 6 illustrate timing diagram examples of the operation of an out-of-lock detection circuit according to the present invention; and

fig. 7 shows a flowchart of an example of a method for detecting out-of-lock in a half-rate CDR circuit according to the present disclosure.

Detailed Description

Certain terms are used throughout the description and claims to refer to particular system components. As one skilled in the art will appreciate, different parties may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the present disclosure and claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to … …". Furthermore, the term "coupled" is intended to mean either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation "based on" is intended to mean "based, at least in part, on". Thus, if X is based on Y, X may be a function of Y and any number of other factors.

Clock and Data Recovery (CDR) circuits use phase and frequency detectors to recover a frequency and phase aligned clock to a clock embedded in received data. The frequency acquisition loop includes a frequency detector that acquires a frequency close to the frequency of the embedded clock, and the phase tracking loop includes a phase detector that phase aligns the recovered clock to the frequency aligned embedded clock. In some embodiments, the frequency and phase detection is performed in a single loop. The recovered clock is used to generate recovered data from the received data.

In some applications, the CDR circuit includes a reference clock in the frequency acquisition loop, while for other applications, the CDR circuit is reference-free and only the location of the data edges is known. In particular, but not exclusively, for reference-less CDR circuits, a mechanism for detecting out-of-lock conditions (including false locks) is advantageous. For example, in a CDR circuit, the frequency detector may be turned off after initial frequency acquisition to save power. The out-of-lock detection circuit may detect/identify an out-of-lock condition and enable the CDR to take corrective action, which may include powering up the frequency detector and resuming frequency acquisition.

Out-of-lock detection circuits designed for full-rate CDR circuits are not suitable for use with half-rate CDR circuits. The out-of-lock detection circuit disclosed herein detects out-of-lock and mis-lock in a half-rate CDR circuit. Embodiments of an out-of-lock detection circuit of the present disclosure determine whether half-rate retimed data includes transitions corresponding to transitions in the original data. Lost transitions in half-rate retimed data may be due to clock frequencies below or above half the data rate, resulting in lost transitions due to undersampling or sample/hold time violations. The out-of-lock detection circuit disclosed herein is suitable for use with various half-rate phase/frequency detectors and does not require the use of a reference clock.

Fig. 1 shows a block diagram of a half-rate CDR system 100 according to the present disclosure. Half-rate CDR system 100 includes CDR circuit 102 and out-of-lock detection circuit 108. CDR circuit 102 recovers a clock signal from the received data and retimes the received data using the recovered clock signal. CDR circuit 102 includes a data recovery circuit 104 and a clock recovery circuit 106. Clock recovery circuit 106 may include a frequency detection circuit and a phase detection circuit to generate recovered clock signal 112 based on transitions of original data stream 110. The frequency and phase of the recovered clock signal 112 aligns the recovered clock signal 112 with the bit timing of the original data stream 110. The data recovery circuit 104 applies the recovered clock signal 112 to retime (i.e., retime) the original data stream 110. Data recovery circuit 104 generates two retimed data streams 114 and 116 from original data stream 110. Each of retimed data streams 114 and 116 is half the bit rate of original data stream 110. For example, retimed data stream 114 includes only odd bits of original data stream 110, and retimed data stream 114 includes only even bits of original data stream 110.

The out-of-lock detection circuit 108 monitors the relationship of the recovered clock signal 112 and the original data stream 110 to determine whether the recovered clock signal 112 is locked to the original data stream 110. If the out-of-lock detection circuit 108 determines that the recovered clock signal 112 is not locked to the original data stream 110, the out-of-lock detection circuit 108 generates an out-of-lock indicator 118. Upon receipt of the out-of-lock indicator 118, the clock recovery circuit 106 may activate a frequency detection circuit and/or a phase detection circuit to resynchronize the recovered clock signal 112 to the original data stream 110.

Fig. 2 shows a schematic diagram of an example of an out-of-lock detection circuit 200 suitable for use in the half-rate CDR system 100. Out-of-lock detection circuit 200 is an embodiment of 108. Out-of-lock detection circuit 200 includes a detection circuit 201 and a pulse summation circuit 220 coupled to detection circuit 201. The detection circuit 201 includes a synchronous flip-flop 202, a synchronous flip-flop 204, an exclusive nor gate 214, a delay circuit 216, and a pulse generation flip-flop 218. The original data stream 110 received from a transmitting data source is clocked into a synchronization flip-flop 202 and a synchronization flip-flop 204 using a recovered clock signal 112 derived from the original data stream 110 by the half rate CDR circuit 102. In some embodiments, the synchronization trigger 202 and the synchronization trigger 204 may be included in the half-rate CDR circuit 102 (e.g., in the data recovery circuit 104).

The synchronization flip-flop 202 samples the original data stream 110 at the rising edge of the recovered clock signal 112 to produce a half-rate data stream 210 containing every other data bit (i.e., odd data bits) of the original data stream 110. The synchronous flip-flop 202 includes a data input terminal 236, a clock input terminal 238, and an output terminal 252. The data input terminal 236 receives the original data stream 110. Clock input 238 receives recovered clock signal 112. The synchronization flip-flop 204 samples the original data stream 110 at the falling edge of the recovered clock signal 112 to produce a half-rate data stream 212 containing every other data bit (i.e., even data bits) of the original data stream 110. The synchronous flip-flop 204 includes a data input terminal 240, a clock input terminal 242, and an output terminal 254. The data input terminal 240 receives the raw data stream 110 and is coupled to the data input terminal 236 of the flip-flop 202. The clock input 242 receives the recovered clock signal 112.

Xor gate 214 combines half-rate data stream 210 and half-rate data stream 212 to produce a signal that indicates whether half-rate data stream 210 and half-rate data stream 212 are the same or different logic values at any one time. Exclusive nor gate 214 includes an input 248, an input 250, and an output 246. Input 248 is coupled to an output terminal 252 of synchronous flip-flop 202. Input 250 is coupled to output terminal 254 of synchronous flip-flop 204. In some embodiments, exclusive or circuit or other circuit that compares two logic level signals may be used in place of exclusive nor gate 214.

Delay circuit 216 includes circuitry that delays original data stream 110 by approximately one bit time of original data stream 110 to produce delayed original data stream 224. For example, the delay circuit 216 may include one or more buffer circuits (inverting or non-inverting drivers) through which the original data stream 110 passes to delay the original data stream 110, where the drivers and their number are selected to produce a delay of approximately one bit time. The bit time is the shortest time between transitions in the original data 110. For example, in the case of non-return-to-zero data, the bit time is the inverse of the bit transfer rate (e.g., 1 nanosecond bit time for a 1 gigabit per second bit transfer rate). Delay circuit 216 includes an input terminal 230 and an output terminal 232. Input terminal 230 is coupled to input terminal 236 of synchronization flip-flop 202 and to input terminal 240 of synchronization flip-flop 204.

Pulse generating flip-flop 218 samples signal 222 on a transition (e.g., rising edge) of delayed original data stream 224. Clocking the signal 222 with the delayed original data stream 224 generates a signal 226 indicating that the synchronization flip-flop 202 or the synchronization flip-flop 204 did not transition in response to a transition in the original data stream 110. Lost transitions in half-rate data stream 210 or half-rate data stream 212 may be due to undersampling (i.e., the rate of recovered clock signal 112 is lower than the rate of original data stream 110) or setup or hold time violations in either synchronization flip-flop 202 or synchronization flip-flop 204, which may be caused by an incorrect rate of recovered clock signal 112. Signal 226 is provided to pulse accumulation circuit 220. Pulse generating flip-flop 218 includes data input terminal 244, clock input terminal 234, and output terminal 228. Data input terminal 244 is coupled to output 246 of exclusive or gate 214. Clock input terminal 234 is coupled to output terminal 232 of delay circuit 216.

In some embodiments of the out-of-lock detection circuit 200, the pulse generating flip-flop 218 includes an edge triggered set or reset input. In such an embodiment, an inverted version of the delayed original data stream 224 may be provided to the edge-triggered set or reset input, such that the pulse-generating flip-flop 218 is set or reset on each falling edge of the delayed original data stream 224. Thus, the pulse generating flip-flop 218 starts an output pulse on the rising edge of the delayed original data stream 224 and terminates the output pulse on the subsequent falling edge of the delayed original data stream 224.

The pulse summation circuit 220 is coupled to an output terminal of the pulse generation flip-flop 218. The pulse accumulation circuit 220 collects the pulses generated by the pulse generation flip-flop 218 and generates the out-of-lock indicator 118 based on the signal 226. Some embodiments of the pulse accumulation circuit 220 generate the out-of-lock indicator 118 based on generating a predetermined number of pulses on the signal 226 over a fixed time interval. Fig. 3 and 4 show examples of implementations of the pulse accumulation circuit 220. In fig. 3, digital counter 300 implements pulse accumulation circuit 220. The clock input of the digital counter is coupled to the output terminal of the pulse generating flip-flop. The pulse provided on signal 226 increments or decrements the digital counter 300 and when the digital counter 300 increments or decrements to a predetermined value, the digital counter 300 generates an output signal indicating that the recovered clock signal 112 has been out-of-lock with the original data stream 110. In some embodiments, digital counter 300 may be periodically set to a predetermined value (e.g., set to zero) to initialize digital counter 300 for out-of-lock detection.

Fig. 4 illustrates a pulse accumulation circuit 400, which is another embodiment of pulse accumulation circuit 220. The pulse summation circuit 400 includes a comparator 406 and a filter circuit 412. A filter circuit 412 is coupled to the output terminal of the pulse generating flip-flop 218. The filter circuit 412 includes a resistor 402 and a capacitor 404. A first terminal 414 of the capacitor 404 is coupled to the output terminal of the pulse generating flip-flop 218 and a second terminal 420 of the capacitor 404 is connected to ground. The pulse on signal 226 charges capacitor 404 such that voltage 410 across capacitor 404 increases in accordance with the change in the number of pulses on signal 226. A filter circuit 412 is also coupled to the comparator 406. The first terminal 414 of the capacitor 404 is coupled to the input terminal 422 of the comparator 406. Comparator 406 compares voltage 410 to threshold voltage 408. An input terminal 416 of comparator 406 is coupled to a threshold voltage source 418 that generates threshold voltage 408. If voltage 410 exceeds threshold voltage 408, comparator 406 drives out-of-lock indicator 118 to indicate that recovered clock signal 112 has been out-of-lock with original data stream 110. Embodiments of pulse summation circuit 400 may also include circuitry to periodically discharge capacitor 404 to initialize pulse summation circuit 400 for out-of-lock detection. Some embodiments of pulse accumulator circuit 400 may include a pulse generator 424, such as a monostable multivibrator circuit, that generates a pulse of defined width to charge capacitor 304 in response to a transition on signal 226.

Fig. 5 illustrates an example of a timing diagram of the operation of the out-of-lock detection circuit 200 according to the present disclosure. The original data stream 110 is sampled by the sync flip-flop 202 on the rising edge of the recovered clock signal 112 to capture the odd data bits B, D, F, etc. The original data stream 110 is sampled by the sync flip-flop 204 on the falling edge of the recovered clock signal 112 to capture the even data bits A, C, E, etc. Xor gate 214 combines half-rate data stream 210 and half-rate data stream 212 to generate a high or low going pulse (going pulses) when half-rate data stream 210 and half-rate data stream 212 are different. The delayed raw data stream 224 clocks the signal 222 to the pulse generating flip-flop 218. If signal 222 indicates that half-rate data stream 210 and half-rate data stream 212 are not different at the edge of the delayed original data, then the half-rate data stream misses the transition in original data stream 110 and signal 226 transitions to indicate the missing transition. The pulse accumulator 220 accumulates transitions or pulses on the out-of-lock indicator 118.

Fig. 6 shows an example of a timing diagram of the operation of the out-of-lock detection circuit 200 illustrating transitions on the original data stream 110. In fig. 6, the original data stream 110 is zero during bit a and is followed by 1. At 602, the original data stream 110 transitions from low to high. At 604, synchronization trigger 202 samples original data stream 110 and half-rate data stream 210 transitions from low to high. Half rate data stream 212 is low at 604 and signal 222 output by exclusive nor gate 214 indicates that half rate data stream 210 and half rate data stream 212 are different. At 608, the delayed original data stream 224 transitions from low to high and the pulse generating flip-flop 218 samples the signal 222 to set the signal 226. At 610, signal 226 indicates that a transition is detected in half-rate data stream 210 and half-rate data stream 212 in response to a transition in original data stream 110 at 602. Thus, the timing of recovered clock signal 112 is responsive to transitions in original data stream 110 at 602, producing transitions in half rate data stream 210 and half rate data stream 212. If there is no transition in half rate data stream 210 at 604, signal 222 would indicate that there is no difference in half rate data stream 210 and half rate data stream 212, and signal 226 would transition to indicate an error at 608.

Fig. 7 shows a flowchart of an example of a method 700 for detecting out-of-lock in a half-rate CDR circuit according to the present disclosure. Although depicted sequentially for convenience, at least some of the acts illustrated may be performed in a different order and/or performed in parallel. Additionally, some embodiments may perform only some of the acts shown. The operations of method 700 may be performed by embodiments of out-of-lock detection circuit 200. In method 700, half-rate CDR circuit 102 generates recovered clock signal 112 based on original data stream 110.

In block 702, the original data stream 110 is sampled and synchronized to the rising edge of the recovered clock signal 112 on the rising edge of the recovered clock signal 112 to produce the half-rate data stream 210. For example, the synchronization flip-flop 202 samples the original data stream 110 on the rising edge of the recovered clock signal 112.

In block 704, the original data stream 110 is sampled and synchronized to the falling edge of the recovered clock signal 112 on the falling edge of the recovered clock signal 112 to produce the half-rate data stream 212. For example, the synchronization flip-flop 204 samples the original data stream 110 that recovered the falling edge of the clock signal 112.

In block 706, the results of sampling the original data stream 110 on the rising and falling edges of the recovered clock signal 112 are combined. For example, exclusive nor gate 214 logically combines half-rate data stream 210 generated by synchronization flip-flop 202 and half-rate data stream 212 generated by synchronization flip-flop 204. Some embodiments may apply an exclusive nor circuit or other comparison logic for combining the results of sampling the original data stream 110 on the rising and falling edges of the recovered clock signal 112.

In block 708, the original data stream 110 is delayed by approximately one bit time. For example, delay circuit 216 delays original data stream 110 by one bit time.

In block 710, the combined rising edge and falling edge sampled recovered clock signal 112 is sampled (i.e., clocked) on the rising edge of the delayed original data stream 224. For example, pulse generating flip-flop 218 samples signal 222 on the rising edge of delayed raw data stream 224.

In block 712, the pulses generated by sampling signal 222 on the rising edge of delayed raw data stream 224 are accumulated. For example, counter 300 may count rising or falling edges that occur in a predetermined time interval, where each rising or falling edge indicates a transition in original data stream 110 that is not included (i.e., lost) in half-rate data stream 210 and half-rate data stream 212.

In block 714, the number of pulses accumulated in block 712 is compared to a threshold. If the number of pulses accumulated in block 712 exceeds the threshold, an out-of-lock indication is generated. In response to the out-of-lock indication, CDR circuit 102 may activate a circuit to resynchronize recovered clock signal 112 to original data stream 110. For example, the CDR circuit may activate a frequency detector and/or a phase detector to synchronize the recovered clock signal 112 to the original data stream 110.

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.