DLL locking indicating circuit and method

文档序号：1523834 发布日期：2020-02-11 浏览：8次中文

阅读说明：本技术 一种dll锁定指示电路及方法 (DLL locking indicating circuit and method ) 是由吴江于 2019-10-30 设计创作，主要内容包括：本发明公开一种DLL锁定指示电路及方法,属于集成电路设计技术领域。所述DLL锁定指示电路包括鉴相器模块、电荷泵/环路滤波器模块、压控延时线模块和锁定指示模块,其中所述鉴相器模块比对CLKD_0、CLKD_N、CLKD_2N三个输入时钟之间的相位差,并输出脉冲控制信号UP、DN；所述电荷泵/环路滤波器模块根据脉冲控制信号UP、DN对控制电压V<Sub>C</Sub>进行充放电；所述压控延时线模块通过控制电压V<Sub>C</Sub>调节其延时,输出CLKD_1~CLKD_2N共2N个时钟信号；所述锁定指示模块根据2N个时钟信号判定DLL是否锁定,并指示锁定是正确锁定还是谐波锁定。(The invention discloses a DLL locking indicating circuit and a DLL locking indicating method, and belongs to the technical field of integrated circuit design. The DLL locking indicating circuit comprises a phase discriminator module, a charge pump/loop filter module, a voltage-controlled delay line module and a locking indicating module, wherein the phase discriminator module compares the phase difference between three input clocks of CLKD _0 and CLKD _ N, CLKD _2N and outputs pulse control signals UP and DN; the charge pump/loop filter module controls the voltage V according to pulse control signals UP and DN C Carrying out charge and discharge; the voltage-controlled delay line module controls the voltage V C Adjusting the time delay of the clock signals, and outputting 2N clock signals of CLKD _ 1-CLKD _2N in total; the lock indication module determines whether the DLL is locked based on the 2N clock signals and indicates whether the lock is a correct lock or a harmonic lock.)

1. A DLL lock indication circuit for use in a circuit system, the DLL lock indication circuit comprising:

the phase detector module compares the phase difference between three input clocks of CLKD _0 and CLKD _ N, CLKD _2N and outputs pulse control signals UP and DN;

a charge pump/loop filter module for controlling the voltage V according to the pulse control signals UP and DN _CCarrying out charge and discharge;

voltage-controlled delay line module by controlling voltage V _CAdjusting the time delay of the clock signals, and outputting 2N clock signals of CLKD _ 1-CLKD _2N in total;

and the locking indicating module is used for judging whether the DLL is locked or not according to the 2N clock signals and indicating whether the locking is correct or harmonic locking.

2. The DLL lock indication circuit of claim 1, wherein the lock indication module comprises a pulse generation unit, a lock detection unit, and a lock type determination unit; wherein the content of the first and second substances,

the PULSE generating unit delays an input clock CLK _ P and generates a narrow PULSE CLK _ PULSE, and the center of the narrow PULSE CLK _ PULSE is aligned with a clock signal CLKD _ 0;

the locking detection unit samples the narrow PULSE CLK _ PULSE, and determines DLL locking and pulls up a locking indication signal when the accumulated M periodic sampling results are all high; m is a counter value of the circuitry configuration;

the locking type judging unit judges the DLL locking type after the locking indication signal is pulled up, and indicates whether the DLL is correctly locked or harmonically locked; when the DLL is locked by harmonic waves, the circuit system resets the DLL and configures the delay of the voltage-controlled delay line module to be the minimum value, so that the DLL retraces and enters a correct locking state.

3. The DLL lock indication circuit of claim 2, wherein the voltage controlled delay line module comprises 2N identical voltage controlled delay cells, an input of which is a clock signal CLKD _0, the voltage controlled delay cells outputting clock signals CLKD _1, ·, CLKD _ N, ·, CLKD _2N, respectively.

4. The DLL lock indication circuit of claim 3, wherein a PULSE width of the narrow PULSE CLK _ PULSE generated by the PULSE generation unit is determined by a number of buffers configured by circuitry.

5. The DLL lock indication circuit of claim 4, wherein the pulse generation unit comprises two stages of a buffer and an xor gate, the buffer having a delay of △ t _dThe narrow PULSE CLK _ PULSE is generated with a PULSE width of 2 △ t _dThe locked clock signal CLKD _2N is in phase with the clock signal CLKD _0, and if the sampling results are all 1 for M periods, the DLL is judged to be locked.

6. The DLL lock indication circuit of claim 5, wherein the lock detection unit comprises a D flip-flop and a counter M, the D flip-flop input terminal being connected to the exclusive or gate output terminal.

7. The DLL lock indication circuit of claim 3, wherein the lock type determination unit comprises an and gate and N-1D flip-flops, the CLK input terminals of the N-1D flip-flops are respectively connected to clock signals CLKD _1,. and CLKD _ (N-1), and the D input terminals are respectively connected to a clock CLKD _ 0; the output ends are all connected to the AND gate.

8. A DLL lock indication method, comprising the steps of:

step 1, a circuit system configures a buffer in a pulse generating unit and determines the time delay of the buffer;

step 2, the circuit system configures the counter M and determines the times of pulling up the continuous sampling value required by the locking indication to be high;

step 3, after resetting the DLL, starting working and generating a narrow PULSE CLK _ PULSE with the width determined by the step 1;

step 4, sampling the narrow PULSE CLK _ PULSE by a clock signal CLKD _2N clock, judging DLL locking if continuous M periods are all high, and pulling up a locking indication signal;

step 5, when detecting that the locking indication signal is high, the locking type judgment unit starts to work, and clock signals CLKD _1 to CLKD _ (N-1) sample a clock signal CLKD _ 0;

step 6, when all sampling values are in phase with the result being high, the locking type is correct locking, otherwise, the locking type is judged to be harmonic locking;

step 7, resetting the DLL when the DLL is subjected to harmonic locking, and setting the delay of the voltage-controlled delay line module to be minimum;

and 8, repeating the steps 3-7 until the DLL is correctly locked.

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a DLL locking indicating circuit and a DLL locking indicating method.

Background

With the rapid development of integrated circuits, the operating speed of circuit systems is higher and higher, and challenges are provided for data transmission, recovery and the like. To reduce the need for high speed clocks, multi-phase clocks have become a solution. DLL (Delay-locked loop) can generate a multi-phase clock with fixed intervals, and is widely applied to the fields of data recovery, oversampling and the like. As the clock frequency range gets wider, how to ensure that the DLL locks correctly and outputs multi-phase clocks at various frequencies becomes a key requirement for DLL design.

The DLL works under a plurality of frequency bands, the voltage-controlled delay line needs to cover a larger delay range, and harmonic locking is easy to occur at the moment, namely the overall delay of the voltage-controlled delay line is n (n =2,3, 4.) clock cycles, so that the phase of an output clock deviates from the phase of a required clock. In order to ensure the DLL to work normally, a lock indication circuit which can monitor the DLL locking condition on line and give an alarm signal when the DLL is locked in a harmonic mode is designed to be a good solution.

Disclosure of Invention

The invention aims to provide a DLL locking indicating circuit and a DLL locking indicating method, which aim to solve the problem that the phase of an output clock deviates from a required clock phase because the current DLL is easy to generate harmonic locking because a voltage-controlled delay line covers a larger delay range.

In order to solve the above technical problem, the present invention provides a DLL lock indicating circuit for use in a circuit system, the DLL lock indicating circuit comprising:

the phase detector module compares the phase difference between three input clocks of CLKD _0 and CLKD _ N, CLKD _2N and outputs pulse control signals UP and DN;

a charge pump/loop filter module for controlling the voltage V according to the pulse control signals UP and DN _CCarrying out charge and discharge;

voltage-controlled delay line module by controlling voltage V _CAdjusting the time delay of the clock signals, and outputting 2N clock signals of CLKD _ 1-CLKD _2N in total;

and the locking indicating module is used for judging whether the DLL is locked or not according to the 2N clock signals and indicating whether the locking is correct or harmonic locking.

Optionally, the lock indication module includes a pulse generation unit, a lock detection unit, and a lock type determination unit; wherein the content of the first and second substances,

the PULSE generating unit delays an input clock CLK _ P and generates a narrow PULSE CLK _ PULSE, and the center of the narrow PULSE CLK _ PULSE is aligned with a clock signal CLKD _ 0;

Optionally, the voltage-controlled delay line module includes 2N same voltage-controlled delay units, an input of which is a clock signal CLKD _0, and the voltage-controlled delay units respectively output the clock signals CLKD _1,. lograph, CLKD _ N,. lograph, CLKD _ 2N.

Optionally, the PULSE width of the narrow PULSE CLK _ PULSE generated by the PULSE generating unit is determined by the number of buffers configured by the circuitry.

Optionally, the pulse generating unit includes two stages of buffers and an xor gate, and the delay of the buffers is △ t _dThe narrow PULSE CLK _ PULSE is generated with a PULSE width of 2 △ t _dThe locked clock signal CLKD _2N is in phase with the clock signal CLKD _0, and if the sampling results are all 1 for M periods, the DLL is judged to be locked.

Optionally, the lock detection unit includes a D flip-flop and a counter M, and an input end of the D flip-flop is connected to an output end of the xor gate.

Optionally, the lock type determining unit includes an and gate and N-1D flip-flops, CLK input ends of the N-1D flip-flops are respectively connected to clock signals CLKD _1,. and CLKD _ (N-1), and D input ends are all connected to a clock CLKD _ 0; the output ends are all connected to the AND gate.

The invention also provides a DLL locking indication method, which comprises the following steps: