阅读说明：本技术 基于多块底层板卡的逻辑保护装置及方法 (Logic protection device and method based on multiple bottom-layer board cards ) 是由 杨开明 朱煜 成荣 雷声 鲁森 李鑫 刘涛 于 2021-06-09 设计创作，主要内容包括：本发明提供基于多块底层板卡的逻辑保护装置及方法,包含：多块底层板卡使用恒流源产生的电流以电流环的形式依次串联；多块底层板卡通过通信总线连接,形成通信回路；通过电流环与通信总线触发底层板卡与底层板卡之间的触发逻辑保护联动,包括：将发生故障的底层板卡作为故障板卡,通过所述故障板卡切断电流环,触发通信总线,电流环中故障板卡外的其他底层板卡作为联动板卡,所述联动板卡对与故障板卡相连的输出通道进行置位。上述装置及方法通过通信总线和电流环实现逻辑保护联动。(The invention provides a logic protection device and a method based on a plurality of bottom layer boards, comprising the following steps: the plurality of bottom-layer board cards are sequentially connected in series in a current loop mode by using current generated by a constant current source; the plurality of bottom-layer board cards are connected through a communication bus to form a communication loop; triggering logic protection linkage between the bottom board card and the bottom board card through the current loop and the communication bus comprises the following steps: the method comprises the following steps that a bottom board card with a fault is used as a fault board card, a current ring is cut off through the fault board card, a communication bus is triggered, other bottom board cards outside the fault board card in the current ring are used as linkage board cards, and the linkage board cards are used for setting an output channel connected with the fault board card. The device and the method realize logic protection linkage through the communication bus and the current loop.)

1. The utility model provides a logic protection device based on polylith bottom layer integrated circuit board which characterized in that contains:

the bottom-layer board cards are respectively connected with the controlled sensor and the actuator;

the BCC card generates constant current sources, the currents generated by the bottom layer boards by the constant current sources are sequentially connected in series in a current loop mode, and the on-off of the current loop is controlled by each bottom layer board;

the communication bus is connected with the plurality of bottom-layer board cards to form a communication loop;

logic protection linkage is triggered between the bottom board card and the bottom board card through a current loop and a communication bus, the bottom board card with a fault serves as a fault board card, the current loop is cut off through the fault board card, the communication bus is triggered, other bottom board cards outside the fault board card in the current loop serve as linkage board cards, the linkage board cards set output channels connected with the fault board cards, fault information is sent outwards according to a communication loop and sequentially transmitted to the BCC card, and the fault information is sent to an upper computer through the BCC card.

2. The logic protection device based on the plurality of bottom layer boards as claimed in claim 1, further comprising an analog switch disposed on the bottom layer board for switching off and on the current loop.

3. The logic protection device based on the multiple bottom-layer boards as claimed in claim 1, further comprising a sampling resistor connected in series between different bottom-layer boards, wherein the high-low level of the current detection resistor is used to determine whether triggering is required.

4. The logic protection device of claim 1, wherein the bottom board includes an eddy current sensor input channel, a temperature sensor input channel, a motor control channel, and a solenoid valve control channel.

5. The logic protection device based on the multiple bottom board cards according to claim 1, wherein the bottom board cards comprise a DSP and an FPGA, the sensor collects data and transmits the data to the FPGA, the FPGA transmits the data to the DSP, the data are calibrated and subjected to threshold judgment, if the data exceed the threshold, the data are judged to be abnormal, the data and error codes are transmitted to the FPGA to be packaged into a data packet and transmitted to the upper computer, meanwhile, the FPGA sets the output channel and cuts off a current loop on the bottom board card to trigger an interrupt service program on the DSP, and an error linkage signal is broadcasted to other bottom board cards through a communication bus, so that linkage of all the bottom board cards is triggered, and logic protection is executed.

6. The logic protection device based on the multiple bottom-layer boards as claimed in claim 1, wherein the bottom-layer boards comprise an ARM and an FPGA, the bottom-layer boards receive multiple sensor signals simultaneously, multiple sensor data after AD conversion are written into the FPGA, the FPGA transfers the data to the ARM, the ARM calibrates the sensor data to judge whether a threshold condition is met, and if all calibrated data of the bottom-layer boards meet the threshold condition, a current loop and a communication bus are not triggered; if the data of the bottom board card does not meet the threshold condition, the ARM confirms the error type according to the source channel and the numerical value of the error data, and sends the data and the error type to the FPGA to be packaged into a data packet, the FPGA operates a corresponding actuator according to the error type, and simultaneously cuts off a current loop on the bottom board card, an external interrupt service program in the ARM on the bottom board card detects that the current loop is cut off, triggers a communication bus, sends the error information outwards, sequentially transmits the error information to the BCC card according to a communication loop, and the BCC card sends the error information to an upper computer.

7. The logic protection device based on the multiple bottom-layer boards as claimed in claim 1, wherein the communication bus is an RS485 bus.

8. The logic protection device based on multiple bottom layer boards of claim 1, wherein the multiple bottom layer boards comprise a GIC card, a first DIO card, a second DIO card, an SB card and a PAC card, the GIC card is used for data collection of a sensor; the first DIO card is used for collecting and outputting digital quantity; the SB card is used for acquiring signals of the eddy current sensor and the motor temperature sensor; the PAC card is used for motor driver control and the second DIO card is used for output of a motor enable signal.

9. A logic protection method based on a plurality of bottom layer boards is characterized by comprising the following steps:

the plurality of bottom-layer board cards are sequentially connected in series in a current loop mode by using current generated by a constant current source;

the plurality of bottom-layer board cards are connected through a communication bus to form a communication loop;

triggering logic protection linkage between the bottom board card and the bottom board card through the current loop and the communication bus comprises the following steps: the method comprises the following steps that a bottom board card with a fault is used as a fault board card, a current ring is cut off through the fault board card, a communication bus is triggered, other bottom board cards outside the fault board card in the current ring are used as linkage board cards, and the linkage board cards are used for setting an output channel connected with the fault board card.

10. The logic protection method according to claim 9, further comprising the step of determining whether the underlying board card has failed, including:

receiving data collected by a sensor through a bottom board card;

calibrating the data and judging a threshold value;

and when the data exceeds the threshold value, the bottom board card is judged to be a fault board card.

Technical Field

The invention belongs to the technical field of semiconductor equipment, and relates to a logic protection device and method based on a plurality of bottom-layer board cards.

Background

In the control of the workpiece table, the number of sensors and actuators is large, instructions are complex, equipment is expensive, and operation precision is high, so that once data detected by a certain sensor exceeds a threshold value, a plurality of actuators need to be triggered to act simultaneously, and further expansion of faults is prevented, and equipment damage and material loss are caused. However, since the actuators are controlled by a plurality of bottom board cards respectively, and communication with the upper computer only exists in the BCC card, once a certain bottom board card judges that the sensor data is abnormal, the board card is required to process the abnormality in a fast manner, and other board cards are required to assist in processing the abnormality, and the specific fault type is fed back to the upper computer.

Disclosure of Invention

The invention provides a logic protection device and a logic protection method based on a plurality of bottom-layer board cards, wherein the logic protection device and the logic protection method are used for realizing logic protection linkage through a communication bus and a current loop.

According to an aspect of the present invention, there is provided a logic protection apparatus based on a plurality of underlying boards, comprising:

the bottom-layer board cards are respectively connected with the controlled sensor and the actuator;

the BCC card generates constant current sources, the currents generated by the bottom layer boards by the constant current sources are sequentially connected in series in a current loop mode, and the on-off of the current loop is controlled by each bottom layer board;

the communication bus is connected with the plurality of bottom-layer board cards to form a communication loop;

logic protection linkage is triggered between the bottom board card and the bottom board card through a current loop and a communication bus, the bottom board card with a fault serves as a fault board card, the current loop is cut off through the fault board card, the communication bus is triggered, other bottom board cards outside the fault board card in the current loop serve as linkage board cards, the linkage board cards set output channels connected with the fault board cards, fault information is sent outwards according to a communication loop and sequentially transmitted to the BCC card, and the fault information is sent to an upper computer through the BCC card.

The logic protection device based on the plurality of bottom-layer board cards further comprises an analog switch which is arranged on the bottom-layer board card and used for cutting off and conducting the current loop.

The logic protection device based on the plurality of bottom-layer board cards further comprises a sampling resistor which is connected in series between different bottom-layer board cards, and whether triggering is needed or not is judged through the high and low levels of a current detection resistor.

The logic protection device based on the plurality of bottom-layer board cards is characterized in that the bottom-layer board cards comprise an eddy current sensor input channel, a temperature sensor input channel, a motor control channel and an electromagnetic valve control channel.

The logic protection device based on the plurality of bottom board cards is characterized in that the bottom board cards comprise a DSP (digital signal processor) and an FPGA (field programmable gate array), data collected by a sensor are transmitted to the FPGA, the data are transmitted to the DSP by the FPGA, are calibrated and judged according to a threshold value, if the data exceed the threshold value, the data are judged to be abnormal, the data and error codes are transmitted to the FPGA to be packaged into a data packet and transmitted to an upper computer, meanwhile, the FPGA sets an output channel, a current loop on the bottom board card is cut off, an interrupt service program on the DSP is triggered, an error linkage signal is broadcasted to other bottom board cards through a communication bus, and therefore all bottom board card linkage is triggered and logic protection is executed.

The logic protection device based on the plurality of bottom-layer board cards is characterized in that the bottom-layer board cards comprise an ARM (advanced RISC machine) and an FPGA (field programmable gate array), the bottom-layer board cards receive multiple sensor signals at the same time, the multiple sensor data subjected to AD (analog-to-digital) conversion are written into the FPGA, the FPGA transfers the data to the ARM, the ARM calibrates the sensor data to judge whether a threshold condition is met, and if all calibrated data of the bottom-layer board cards meet the threshold condition, a current loop and a communication bus are not triggered; if the data of the bottom board card does not meet the threshold condition, the ARM confirms the error type according to the source channel and the numerical value of the error data, and sends the data and the error type to the FPGA to be packaged into a data packet, the FPGA operates a corresponding actuator according to the error type, and simultaneously cuts off a current loop on the bottom board card, an external interrupt service program in the ARM on the bottom board card detects that the current loop is cut off, triggers a communication bus, sends the error information outwards, sequentially transmits the error information to the BCC card according to a communication loop, and the BCC card sends the error information to an upper computer.

The logic protection device based on the plurality of bottom layer board cards is characterized in that the communication bus is an RS485 bus.

The logic protection device based on the plurality of bottom layer boards comprises a GIC card, a first DIO card, a second DIO card, an SB card and a PAC card, wherein the GIC card is used for data acquisition of a sensor; the first DIO card is used for collecting and outputting digital quantity; the SB card is used for acquiring signals of the eddy current sensor and the motor temperature sensor; the PAC card is used for motor driver control and the second DIO card is used for output of a motor enable signal.

The logic protection device based on the multiple bottom layer board cards is characterized in that the BCC card, the GIC card, the first DIO card and the SB card are arranged in an electric cabinet, the PAC card and the second DIO card are arranged in a PA cabinet, and the PA cabinet is arranged on the outer side of a workpiece platform.

The logic protection device based on the plurality of bottom layer boards comprises a DSP (digital signal processor) or an ARM (advanced RISC machine) and an FPGA (field programmable gate array), wherein the FPGA comprises a register, a packing module and a setting register, the DSP or the ARM comprises a buffer area, a calibration data register, an error code register, a signal transceiving module and an interrupt service module, the register of the FPGA receives data of a sensor and sends the data to the buffer area of the DSP or the ARM, the calibration data register calibrates the data, if the data meets a threshold condition, the data is packed into a data packet and transmitted to the packing module of the FPGA, and the data packet is uploaded to other bottom layer boards or BCC cards through an HSSL optical port; if the data does not meet the threshold condition, the error type is confirmed according to the source channel and the numerical value of error data, the data and the error type are converted into error codes and stored in an error code register, the error code register sends the error codes to a packaging module of the FPGA, the error codes are packaged into error packets and uploaded to other bottom layer boards or BCC cards through an HSSL optical port, the packaging module of the FPGA receives the error codes, a current loop is cut off, an interrupt service module of the DSP or ARM stores an interrupt service program to detect the current loop, the cut-off of the current loop is detected, a signal receiving and sending module on the DSP or ARM is triggered, an error linkage signal is transmitted to other bottom layer boards through a communication bus, a setting register of the FPGA is triggered, and an output channel is set.

According to another aspect of the present invention, a logic protection method based on multiple bottom layer boards is provided, including:

the plurality of bottom-layer board cards are sequentially connected in series in a current loop mode by using current generated by a constant current source;

the plurality of bottom-layer board cards are connected through a communication bus to form a communication loop;

triggering logic protection linkage between the bottom board card and the bottom board card through the current loop and the communication bus comprises the following steps: the method comprises the following steps that a bottom board card with a fault is used as a fault board card, a current ring is cut off through the fault board card, a communication bus is triggered, other bottom board cards outside the fault board card in the current ring are used as linkage board cards, and the linkage board cards are used for setting an output channel connected with the fault board card.

Optionally, the logic protection method further includes a step of determining whether the bottom board card fails, where the step includes:

receiving data collected by a sensor through a bottom board card;

calibrating the data and judging a threshold value;

and when the data exceeds the threshold value, the bottom board card is judged to be a fault board card.

The logic protection device and the method based on the plurality of bottom-layer board cards establish a logic protection device based on a communication bus and a current loop. When the data measured by the sensor exceeds the threshold value, the bottom-layer board card can quickly execute linkage and report faults, the system is protected from being damaged, and the fault reasons can be quickly found through fault information.

Drawings

Fig. 1 is a schematic diagram of a block diagram of a logic protection device based on a plurality of bottom-layer boards according to the present invention;

FIG. 2 is a schematic diagram of a plurality of substrate boards connected in series in a current loop manner according to the present invention;

FIG. 3 is a schematic diagram of one embodiment of a building block for the underlying board card of the present invention;

fig. 4 is a schematic diagram of a flow chart of a logic protection method based on multiple bottom-layer boards according to the present invention.

Detailed Description

In order to fully illustrate the invention, various figures are provided to illustrate the invention in detail as follows:

fig. 1 is a block diagram of a logic protection device based on multiple underlying boards according to the present invention, as shown in fig. 1. The logic protection device comprises:

the bottom-layer board cards 10 are respectively connected with the controlled sensor 1 and the actuator 2;

the BCC card 20 generates constant current sources, the currents generated by the bottom layer boards by using the constant current sources are sequentially connected in series in a current loop mode, and the on-off of the current loop is controlled by each bottom layer board;

the communication bus 30 is connected with a plurality of bottom-layer board cards to form a communication loop;

logic protection linkage is triggered between the bottom board card and the bottom board card through a current ring and a communication bus, the failed bottom board card serves as a fault board card, the current ring is cut off through the fault board card, the communication bus is triggered, other bottom board cards outside the fault board card in the current ring serve as linkage board cards, the linkage board cards set output channels connected with the fault board card (for example, relays are arranged on the output channels, the bottom board card is switched on normally, and the bottom board card is switched off after fault setting), fault information (for example, data when a threshold value is abnormal, data packets packed by error codes and the like) is sent outwards according to a communication loop and sequentially transmitted to the BCC card, and the fault information is sent to an upper computer through the BCC card.

The BCC card is a control board card which is used for managing the moving-in and moving-out of the workpiece platform on the workpiece platform, and as the hardware resources on the BCC card are rich, the BCC card is added with the function of overall safety logic protection.

In one embodiment, the logic protection device based on the plurality of bottom layer boards further comprises an analog switch, which is arranged on the bottom layer board and used for cutting off and conducting the current loop.

In one embodiment, the logic protection device based on the multiple bottom layer boards further includes sampling resistors connected in series between different bottom layer boards, and determines whether triggering is needed or not by the high and low levels of the current detection resistors, for example, high level triggering, that is, it determines voltage change on the sampling resistors to cooperatively process faults, sets some output channels (for example, output channels of a motor which does not affect the safety of the workpiece stage after stopping operation), determines whether setting is performed by voltage change, sets the output channels to cause the disconnection of a current loop, and drops the voltage of the sampling resistors to 0, which indicates that the linked boards stop operating simultaneously.

In one embodiment, the bottom board card includes multiple analog input channels, digital input channels, analog output channels, and digital output channels.

Optionally, the bottom board card includes an eddy current sensor input channel, a temperature sensor input channel, a motor control channel, and an electromagnetic valve control channel, and the eddy current sensor input channel, the temperature sensor input channel, the motor control channel, and the electromagnetic valve control channel are all included in the analog input/output channel and the digital input/output channel.

In one embodiment, as shown in fig. 3, the bottom board includes a DSP and an FPGA, the sensor collects data and transmits the data to the FPGA, the FPGA transmits the data to the DSP, the data is calibrated (for example, curve fitting is performed on an analog signal and a digital signal), a threshold is determined, if the data exceeds the threshold, it determines that the data is abnormal, and sends the data and an error code (error type divided according to different moving parts of the workpiece stage, such as a coarse stage error, a fine stage error, and the like) to the FPGA to be packaged into a data packet and transmits the data packet to an upper computer, and the FPGA sets an output channel (an output channel of the bottom board, which is used for controlling the moving parts, an analog output channel, and a digital output channel) and cuts off a current loop on the bottom board, triggers an interrupt service program on the DSP, and transmits an error linkage signal (the error linkage signal does not include specific error information and only includes a request for performing linkage, the error linkage signal is transmitted to all bottom-layer board cards participating in logic protection, the signal is simple, and the required communication time is short; a data packet formed by packaging the data and the error codes contains detailed fault information which is transmitted to an upper computer, and the required communication time is long) and is broadcasted to other bottom-layer board cards through a communication bus, so that all the bottom-layer board cards are triggered to be linked, and logic protection is executed.

The logic protection device firstly needs to monitor various indexes of the equipment according to a certain frequency by using a sensor and transmit the indexes to a bottom board card for processing and judging when judging whether the equipment has a fault in the working process. Generally, data measured by the sensor belongs to an analog signal, and an ADC chip on a bottom board converts the data into a digital signal and writes the digital signal into a memory of the FPGA. The DSP reads the data by accessing the memory of the FPGA, the DSP calibrates the original data, the calibrated data is returned to the FPGA memory register, the threshold value judgment is carried out, and the judged result is written back to the FPGA memory register. And packaging all input sensor information and threshold judgment result information by the FPGA, and reporting to the control system through the HSSL optical port. The FPGA sends the data to a control cabinet through an optical port for debugging; if the error type of the data exceeds the threshold value, the calibrated data and the error type package are transmitted back to the FPGA, the FPGA operates the peripheral equipment according to the error type, and meanwhile, the DSP sends the error alarm to the adjacent board card until the error alarm is sent to the upper computer. If the data received by the bottom layer board card is normal, but other board cards generate false alarm, the DSP of the board card receives the alarm information, executes corresponding operation according to the alarm information, and continuously sends the false alarm information to the next level board card until the BCC card is collected and sent to the upper computer. When an error is detected, the other boards are protected by the link logic of the communication bus and the current loop in order to be able to process the error as quickly as possible and to know the type of the error.

In one embodiment, the bottom board card comprises an ARM and an FPGA, the bottom board card receives multiple sensor signals at the same time, multiple sensor data subjected to AD conversion are written into the FPGA, the FPGA transfers the data to the ARM, the ARM calibrates the sensor data to judge whether a threshold condition is met, and if all calibrated data of the bottom board card meet the threshold condition, a current loop and a communication bus are not triggered; if the data of the bottom plate card does not meet the threshold condition, the ARM confirms the error type (such as the exceeding of a temperature sensor, the exceeding of an eddy current sensor, the exceeding of a grating ruler, the exceeding of a laser triangle, the exceeding of a motor rotating speed and the like) according to the source channel and the numerical value of the error data, and sends the data and the error type to the FPGA to be packed into a data packet, the FPGA operates the corresponding actuator according to the error type (the corresponding actuator is determined according to the actuator monitored by the sensor, for example, if the eddy current sensor detects that the distance exceeds the standard, the coarse moving table motor is operated to return to the zero point), and meanwhile, a current loop on the bottom layer board card is cut off, an external interrupt service program in an ARM on the bottom layer board card detects that the current loop is cut off, a communication bus is triggered, error information (such as data when the error information exceeds a threshold value) is sent outwards and is sequentially transmitted to the BCC card according to a communication loop, and the BCC card sends the error information to an upper computer.

In one embodiment, the communication bus is an RS485 bus.

In one embodiment, as shown in fig. 2, the plurality of bottom-layer boards include a GIC card 11, a first DIO card 12, a second DIO card 13, an SB card 14, and a PAC card 15, where the GIC card 11 is used for data acquisition of sensors, such as a water path, a gas path, a grating ruler, a grating containing ruler, and the like; the first DIO card 12 is used for collecting and outputting digital quantity, such as input and output of digital quantity of devices such as a solenoid valve; the SB card 14 is used for signal acquisition of the eddy current sensor and the motor temperature sensor; the PAC card 15 is used for motor driver control and the second DIO card 13 is used for output of a motor enable signal.

Optionally, the BCC card, GIC card, first DIO card, SB card are disposed in an electric cabinet (the electric cabinet is used for unified installation and wiring), the PAC card and second DIO card are disposed in a PA cabinet (the cards used for installing PAC card, second DIO card, etc. directly used for motor control), and the PA cabinet is disposed outside the workpiece table.

In one embodiment, as shown in fig. 3, the bottom board card includes a DSP or an ARM, an FPGA, the FPGA includes a register 111, a packing module 112, and a setting register 113, the DSP or the ARM includes a buffer 121, a calibration data register 122, an error code register 123, a signal transceiver module, and an interrupt service module 125, the register of the FPGA receives data of the sensor and sends the data to the buffer of the DSP or the ARM, the calibration data register calibrates the data, and if the data meets a threshold condition, the data is packed into a data packet and transmitted to the packing module of the FPGA, and is uploaded to other bottom board cards or BCC cards through an HSSL optical interface; if the data does not meet the threshold condition, the error type is confirmed according to the source channel and the numerical value of error data, the data and the error type are converted into error codes and stored in an error code register, the error code register sends the error codes to a packaging module of the FPGA, the error codes are packaged into error packets and uploaded to other bottom layer boards or BCC cards through an HSSL optical port, the packaging module of the FPGA receives the error codes, a current loop is cut off, an interrupt service module of the DSP or ARM stores an interrupt service program to detect the current loop, the cut-off of the current loop is detected, a signal receiving and sending module on the DSP or ARM is triggered, an error linkage signal is transmitted to other bottom layer boards through a communication bus, a setting register of the FPGA is triggered, and an output channel is set.

In one embodiment, on hardware, first, each bottom board card is respectively connected with a sensor and an actuator which are responsible for the bottom board card; the BCC card is responsible for generating a constant current source, then the bottom layer cards are sequentially connected in series in a current loop mode by using the current to form a loop, each card can control the on-off of the current loop, when a serious fault occurs, the fault card cuts off the current in the loop, other cards in the loop cooperatively process the fault by judging the voltage change on the sampling resistor, and certain output channels are set to ensure that the workpiece platform is safely stopped; meanwhile, fault information is encoded and sent to the control system through the HSSL optical port.

When the workpiece table works, all the sensors transmit signals to the connected bottom board card according to the fixed sampling frequency. Because the sensor signal is an analog signal, the bottom board card can convert the sensor signal into a digital signal through the ADC chip; each bottom board card needs to receive multiple sensor signals at the same time, so that the parallel computing capability of the FPGA is utilized, multiple sensor data after AD conversion are written into the FPGA, then the FPGA transfers the data to the DSP or the ARM, the DSP or the ARM calibrates the sensor data, and then whether the threshold condition is met or not is judged. If all calibrated data of the board card meet the threshold condition, the system works normally, and the current loop and the RS485 cannot be triggered; if the data of the board card does not meet the threshold condition, the DSP or the ARM can confirm the error type according to the source channel and the numerical value of the error data, and send the data and the error type to the FPGA for packaging. After receiving the error packet, the FPGA immediately emergently operates the corresponding actuator according to the error type, simultaneously cuts off the current loop on the board card to inform other board cards of carrying out emergency linkage, when an external interrupt service program in a DSP or an ARM on the board card detects that the current loop is cut off, the FPGA triggers the RS485, sends error information outwards, sequentially transmits the error information to the BCC according to a loop, and sends the error information to an upper computer through the BCC; if the data of the board card meets the threshold condition, but other board cards detect that the data do not meet the threshold condition, the other board cards can cut off the current loop and send error information through the RS485, the board card can detect that the current loop is cut off later, the FPGA starts to operate the actuator emergently, and the DSP or the ARM starts to receive and send RS485 signals. When the fault is cleared, the system resets the error code register and the workpiece stage resumes operation.

In a workpiece table motion system, each bottom board card is responsible for receiving part of sensor signals and processing data of the system, and logic protection linkage is triggered between the bottom board card and the bottom board card through a current loop and RS 485. The bottom board card is provided with multiple paths of AI and DI inputs and AO and DO outputs and comprises an eddy current sensor input channel, a temperature sensor input channel, a motor control channel, an electromagnetic valve control channel and the like. The current loop circuit judges whether triggering is needed or not through the high and low levels of the current detection resistor, and the current loop is switched off and on through the analog switch.

As shown in fig. 2, each board card in the electronic control box is connected with the current loop through RS 485. When the device works normally, the current loop is connected, and the RS485 is not triggered; and after a fault occurs, the fault board card cuts off the current loop, so that other board cards also cut off the current loops of the fault board cards, linkage is executed, and RS485 triggers and reports the fault to BCC.

As shown in fig. 2, the specific executed block diagram connection relationship between the RS485 and the current loop in the bottom board card includes:

the sensor sends important monitoring data to the bottom board card, the FPGA on the bottom board card receives the data, the data are calibrated and then sent to the DSP, and the DSP judges the threshold value of the data. If the specified threshold value is exceeded, the fault is judged, and the fault type is determined according to the fault table. And then, sending the calibrated data and the fault type to the FPGA, cutting off a current loop by the FPGA and operating other peripheral equipment.

And when other board cards in the current loop detect the abnormality of the current loop, the emergency fault needing to execute linkage is determined, and corresponding linkage action is executed to protect the system.

The board card which triggers the linkage sends the detailed fault information to the BCC card through an RS485 bus, and reports the fault information to the host computer in real time after being gathered by the FPGA of the BCC card.

After the linkage fault is cleared, the bottom board card clears the linkage signal, the system resets, the analog switch on each board card is switched on, the current loop recovers to a normal operation state, and the operation is restarted.

Fig. 4 is a schematic diagram of a flowchart of a logic protection method based on multiple bottom-layer boards, where as shown in fig. 4, the logic protection method based on multiple bottom-layer boards includes:

step S1, sequentially connecting a plurality of bottom-layer board cards in series in a current loop mode by using current generated by a constant current source;

step S2, connecting a plurality of bottom-layer board cards through a communication bus to form a communication loop;

step S3, trigger logic protection linkage between bottom plate card and bottom plate card through electric current loop and communication bus, include: the method comprises the following steps that a bottom board card with a fault is used as a fault board card, a current ring is cut off through the fault board card, a communication bus is triggered, other bottom board cards outside the fault board card in the current ring are used as linkage board cards, and the linkage board cards are used for setting an output channel connected with the fault board card.

In one embodiment, the logic protection method further includes a step of determining whether the bottom board card has a fault, including:

receiving data collected by a sensor through a bottom board card;

calibrating the data and judging a threshold value;

and when the data exceeds the threshold value, the bottom board card is judged to be a fault board card.

In one embodiment, the logic protection method implemented on a large system composed of a plurality of bottom-layer boards based on RS485 communication and a current loop specifically includes: each bottom board card is composed of ARM + FPGA or DSP + FPGA according to different use requirements, and undertakes tasks such as motor control, valve control, sensor signal processing and communication with an upper computer. Firstly, continuously acquiring data by a sensor, transmitting the data to an FPGA (field programmable gate array) through AD (analog-to-digital) conversion, transmitting the data to a DSP (digital signal processor) by the FPGA, calibrating the converted data, and judging a threshold value; if the data is abnormal, the data and the error codes are sent to the FPGA for packaging, the FPGA transmits the data package to an upper computer, meanwhile, the FPGA also sets an output channel, cuts off a current loop on the board card, triggers an interrupt service program on the DSP, broadcasts an error linkage signal to other bottom board cards through RS485, and accordingly triggers linkage of all the bottom board cards and executes a logic protection function; when the data received by the bottom board card is normal and the data received by other bottom board cards is abnormal, the logic protection is completed by directly cutting off the current loop, and the speed is fastest.

In one embodiment, the method further comprises the step of grading the logic protection, wherein the logic protection of the highest level is completed by directly cutting off a current loop, the speed is fastest, and the logic protection of other levels is completed by receiving RS485 signals.

Optionally, the logic protection is divided into two stages, one stage is to cut off a current loop, the other stage is to stop an actuator corresponding to a sensor with abnormal data received by the bottom board card, for example, when the eddy current sensor detects that the distance exceeds the standard, the coarse moving table motor is operated to return to the zero point.

Optionally, the logic protection is divided into three stages, the first stage is a current cut-off loop, the second stage is an actuator corresponding to a sensor stopping abnormal data received by the bottom board card and an actuator not affecting the safety of the workpiece table, and the third stage is an actuator corresponding to a sensor stopping abnormal data received by the bottom board card.

The logic protection method provided by the invention can protect the whole system to the maximum extent and realize the logic protection linkage function of a complex system with a plurality of bottom layer boards and a plurality of actuators at high speed.

The present invention is capable of other embodiments, and various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.