阅读说明：本技术 脉冲信号产生电路 (Pulse signal generating circuit ) 是由 胡曙敏 于 2019-10-21 设计创作，主要内容包括：本发明公开了一种脉冲信号产生电路。脉冲信号产生电路包括第一反相器、第二反相器、第一电阻、第一NMOS管、第一电容、第三反相器和第一与非门。利用本发明提供的脉冲信号产生电路可以提供整个电路的稳定性,电路简单。(The invention discloses a pulse signal generating circuit. The pulse signal generating circuit comprises a first phase inverter, a second phase inverter, a first resistor, a first NMOS tube, a first capacitor, a third phase inverter and a first NAND gate. The pulse signal generating circuit provided by the invention can provide the stability of the whole circuit and has simple circuit.)

1. A pulse signal generating circuit, characterized by: comprises a first inverter, a second inverter, a first resistor

The NMOS transistor, the first capacitor, the third inverter and the first NAND gate;

the input end of the first phase inverter is connected with the input end IN of the pulse signal generating circuit, and the output end of the first phase inverter is connected with the input end of the second phase inverter and the grid electrode of the first NMOS tube; the input end of the second inverter is connected with the output end of the first inverter and the grid electrode of the first NMOS tube, and the output end of the second inverter is connected with one end of the first resistor; one end of the first resistor is connected with the output end of the second phase inverter, and the other end of the first resistor is connected with the drain electrode of the first NMOS tube, one end of the first capacitor and the input end of the third phase inverter; the grid electrode of the first NMOS tube is connected with the output end of the first phase inverter and the input end of the second phase inverter, the drain electrode of the first NMOS tube is connected with one end of the first resistor, one end of the first capacitor and the input end of the third phase inverter, and the source electrode of the first NMOS tube is grounded; one end of the first capacitor is connected with one end of the first resistor, the drain electrode of the first NMOS tube and the input end of the third inverter, and the other end of the first capacitor is grounded; the input end of the third inverter is connected with one end of the first resistor, the drain electrode of the first NMOS tube and one end of the first capacitor, and the output end of the third inverter is connected with one input end of the first NAND gate; one input end of the first NAND gate is connected with the input end IN of the pulse signal generating circuit, the other input end of the first NAND gate is connected with the output end of the third inverter, and the output end of the first NAND gate is the output end OUT of the pulse signal generating circuit.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a pulse signal generating circuit.

Background

The stability of the pulse information in the integrated circuit directly affects the function of the whole circuit, and the whole system is seriously disabled.

Disclosure of Invention

The invention aims to solve the defects of the prior art and provides a pulse signal generating circuit.

The pulse signal generating circuit comprises a first phase inverter, a second phase inverter, a first resistor, a first NMOS (N-channel metal oxide semiconductor) tube, a first capacitor, a third phase inverter and a first NAND gate:

the input end of the first phase inverter is connected with the input end IN of the pulse signal generating circuit, and the output end of the first phase inverter is connected with the input end of the second phase inverter and the grid electrode of the first NMOS tube; the input end of the second inverter is connected with the output end of the first inverter and the grid electrode of the first NMOS tube, and the output end of the second inverter is connected with one end of the first resistor; one end of the first resistor is connected with the output end of the second phase inverter, and the other end of the first resistor is connected with the drain electrode of the first NMOS tube, one end of the first capacitor and the input end of the third phase inverter; the grid electrode of the first NMOS tube is connected with the output end of the first phase inverter and the input end of the second phase inverter, the drain electrode of the first NMOS tube is connected with one end of the first resistor, one end of the first capacitor and the input end of the third phase inverter, and the source electrode of the first NMOS tube is grounded; one end of the first capacitor is connected with one end of the first resistor, the drain electrode of the first NMOS tube and the input end of the third inverter, and the other end of the first capacitor is grounded; the input end of the third inverter is connected with one end of the first resistor, the drain electrode of the first NMOS tube and one end of the first capacitor, and the output end of the third inverter is connected with one input end of the first NAND gate; one input end of the first NAND gate is connected with the input end IN of the pulse signal generating circuit, the other input end of the first NAND gate is connected with the output end of the third inverter, and the output end of the first NAND gate is the output end OUT of the pulse signal generating circuit.

The first inverter, the second inverter, the first resistor, the first NMOS transistor, the first capacitor and the third inverter form a delay part, and the product of the first resistor and the first capacitor determines the delay time of the delay part; when the input end IN of the pulse signal generating circuit is changed from low level to high level, one input end of the first NAND gate is connected with the input end IN of the pulse signal generating circuit and is firstly changed to high level, the other input end of the first NAND gate is connected with the delay part and is changed from high level to low level, and the output end OUT of the pulse signal generating circuit is changed to low level IN the delay process of the delay part; when the delay section becomes a low level, the output terminal OUT of the pulse signal generating circuit becomes a high level; when the input terminal IN of the pulse signal generating circuit changes from high level to low level, the output terminal OUT of the pulse signal generating circuit maintains high level because one terminal of the first nand gate has changed to low level.

Drawings

Fig. 1 is a circuit diagram of a pulse signal generating circuit of the present invention.

Detailed Description

The present invention will be further explained with reference to the accompanying drawings.

The pulse signal generating circuit, as shown in fig. 1, includes a first inverter 10, a second inverter 20, a first resistor 30, a first NMOS transistor 40, a first capacitor 50, a third inverter 60, and a first nand gate 70:

the input end of the first inverter 10 is connected with the input end IN of the pulse signal generating circuit, and the output end is connected with the input end of the second inverter 20 and the grid electrode of the first NMOS tube 40; the input end of the second inverter 20 is connected with the output end of the first inverter 10 and the grid of the first NMOS tube 40, and the output end is connected with one end of the first resistor 30; one end of the first resistor 30 is connected to the output end of the second inverter 20, and the other end is connected to the drain of the first NMOS transistor 40, one end of the first capacitor 50, and the input end of the third inverter 60; the gate of the first NMOS transistor 40 is connected to the output terminal of the first inverter 10 and the input terminal of the second inverter 20, the drain is connected to one end of the first resistor 30, one end of the first capacitor 50 and the input terminal of the third inverter 60, and the source is grounded; one end of the first capacitor 50 is connected to one end of the first resistor 30, the drain of the first NMOS transistor 40 and the input end of the third inverter 60, and the other end is grounded; the input end of the third inverter 60 is connected to one end of the first resistor 30, the drain of the first NMOS transistor 40 and one end of the first capacitor 50, and the output end is connected to one input end of the first nand gate 70; one input end of the first nand gate 70 is connected to the input end IN of the pulse signal generating circuit, the other input end is connected to the output end of the third inverter 60, and the output end is the output end OUT of the pulse signal generating circuit.

The first inverter 10, the second inverter 20, the first resistor 30, the first NMOS transistor 40, the first capacitor 50, and the third inverter 60 form a delay part, and the product of the first resistor 30 and the first capacitor 50 determines the delay time of the delay part; when the input end IN of the pulse signal generating circuit changes from low level to high level, one input end of the first NAND gate 70 is connected with the input end IN of the pulse signal generating circuit and is firstly changed to high level, the other input end of the first NAND gate 70 is connected with the delay part and is changed from high level to low level, and the output end OUT of the pulse signal generating circuit changes to low level IN the delay process of the delay part; when the delay section becomes a low level, the output terminal OUT of the pulse signal generating circuit becomes a high level; when the input terminal IN of the pulse signal generating circuit changes from high level to low level, the output terminal OUT of the pulse signal generating circuit maintains high level because one terminal of the first nand gate 70 has changed to low level.

The description of the embodiments provided above is merely illustrative of preferred embodiments of the present invention, and it will be apparent to those skilled in the art that the present invention can be implemented or used in light of the above description. It should be noted that, for those skilled in the art, it is possible to make several modifications and variations without departing from the technical principle of the present invention, and any invention that does not depart from the scope of the essential spirit of the present invention should be construed as the scope of the present invention.