阅读说明：本技术 一种静电感应晶闸管及其制作方法 (Electrostatic induction thyristor and manufacturing method thereof ) 是由 范捷 万立宏 王绍荣 于 2019-11-13 设计创作，主要内容包括：本发明公开了一种静电感应晶闸管及其制作方法,涉及半导体技术领域,提供了一种新的静电感应晶闸管的结构,其正面中间为栅极、两侧为阴极,背面为阳极,在其制作过程中,由于裸露在外的P+杂质区域较小,因此杂质自扩散的问题大幅减轻,电阻率的控制更为精准；形成的栅极引出区的纵向结深较深,不需要担心深度不够或者栅极引出区被刻透的问题,刻蚀深度控制难度较低,不容易因此导致器件失效；而且形成的N-沟道的宽度也较宽,且垂直距离更长,其中的杂质分布也更为均匀,这样的结构将具有更佳的沟道控制能力,更大的电流能力；制作方法难度较低,工艺控制较简单,制作得到的静电感应晶闸管的良品率较高且性能更优。(The invention discloses a static induction thyristor and a manufacturing method thereof, relates to the technical field of semiconductors, and provides a novel structure of the static induction thyristor, wherein the middle of the front surface of the static induction thyristor is provided with a grid, two sides of the static induction thyristor are provided with cathodes, and the back surface of the static induction thyristor is provided with an anode; the formed gate lead-out region has deeper longitudinal junction depth, so that the problem that the depth is not enough or the gate lead-out region is etched through is not needed to be worried about, the etching depth control difficulty is low, and the failure of a device is not easily caused; the width of the formed N-channel is wider, the vertical distance is longer, the impurity distribution is more uniform, and the structure has better channel control capability and larger current capability; the manufacturing method has lower difficulty and simpler process control, and the manufactured electrostatic induction thyristor has higher yield and better performance.)

1. A method for manufacturing a static induction thyristor, the method comprising:

etching the surface of an N-substrate to form gate grooves perpendicular to the surface, wherein the width of each gate groove is the same, a first distance is arranged between each gate groove in the middle of the N-substrate, and a second distance is arranged between the rest gate grooves on two sides of the N-substrate, the second distance is larger than the width of each gate groove, and the first distance is smaller than the width of each gate groove;

manufacturing a P + epitaxial layer in the gate groove;

manufacturing an N-type epitaxial layer on the N-substrate, wherein the concentration of the N-type epitaxial layer is higher than that of the N-substrate; continuing to grow an N-epitaxial layer on the N-type epitaxial layer;

manufacturing a back P + injection region on the back of the N-substrate;

the P + impurities are diffused by advancing, the P + epitaxial layers in the gate grooves are respectively diffused to form gate regions, and the P + epitaxial layers in the gate grooves which are positioned in the middle of the N-substrate and spaced by a first distance are diffused and completely fused to form a gate lead-out region;

manufacturing an N + injection region on the N-epitaxial layer;

etching the N + injection region and the N-epitaxial layer on the surface of the grid electrode lead-out region to expose the grid electrode lead-out region;

manufacturing a dielectric layer on the N + injection region, and etching the surface of the grid electrode leading-out region and the surfaces of the N + injection regions on two sides of the grid electrode leading-out region to form contact holes;

manufacturing a front metal layer and etching to form front electrodes which fill all the contact holes and are mutually spaced, wherein a grid is led out from the grid leading-out region through the front electrodes, and cathode source electrodes positioned at two sides of the grid are led out from the N + injection region through the front electrodes;

and manufacturing a back electrode, and leading out an anode drain electrode from the back P + injection region through the back electrode.

2. The method of claim 1, wherein the depth of the gate trench is between 3-10um, and the depth of the longitudinal junction of the gate region formed by diffusion of the P + epitaxial layer in the gate trench is between 5-12 um.

3. The method of claim 1, wherein the width of the gate trench is between 1-3um, and the second distance is greater than twice the width of the gate trench.

4. The method of any of claims 1-3, wherein said forming a P + epitaxial layer in said gate trench comprises:

carrying out P + epitaxial growth on the N-substrate, wherein the epitaxial temperature is less than 900 ℃, and the growth thickness is the same as the width of the gate groove; the grown P + epitaxial layer is filled in the gate groove and covers the surface of the N-substrate, and the resistivity is less than 0.1 ohm/cm;

and removing the P + epitaxial layer on the surface of the N-substrate by utilizing a CMP (chemical mechanical polishing) process to form the P + epitaxial layer filled in the gate groove.

5. The method of any of claims 1-3, wherein the N-type epitaxial layer fabricated on the N-substrate has a thickness of less than 1um and a resistivity of between 10-50 ohm/cm; the thickness of the N-epitaxial layer formed by continuously growing on the N-type epitaxial layer is between 10 and 20um, and the resistivity of the N-epitaxial layer is consistent with that of the N-substrate.

6. The method of any of claims 1-3, wherein said forming a back side P + implant region on the back side of said N-substrate comprises: and P + ion implantation is carried out on the back surface of the N-substrate, the implanted ions are N, the impurity concentration is between 2E15 and 2E16, and the implantation energy is between 50 and 300 kev.

7. The method as claimed in any one of claims 1-3, wherein the diffusion temperature is between 1000 ℃ and 1150 ℃ for 1-2 hours, and the diffusion depth of the P + impurities in the P + epitaxial layer and the back P + implantation region is within 1 um.

8. The method As claimed in any one of claims 1-3, wherein the impurity implanted during the N + implantation region is As or P, the implantation energy is 50-160kev, the implantation dose is 1E15-2E16, and the diffusion junction depth is within 1 um.

9. A static induction thyristor, characterized in that it is manufactured by the method according to any one of claims 1 to 8.

Technical Field

The invention relates to the technical field of semiconductors, in particular to an electrostatic induction thyristor and a manufacturing method thereof.

Background

The static Induction thyristor is abbreviated as sith (static Induction thyristor), and may also be referred to as field-controlled thyristor (FCT) or Bipolar Static Induction Thyristor (BSITH). The SITH is used as a high-power field control switch device and has a series of advantages of small on-state resistance, low on-state voltage, high switching speed, small switching loss, high reverse blocking gain, large on-off current gain and the like. Since the working frequency of the SITH can reach more than 100KHZ, the SITH can replace the traditional vacuum triode in the high-frequency induction heating power supply.

According to the structural division, the SITH can be divided into a normally-on type and a normally-off type. The SITH can be divided into a reverse blocking type and an anode emitter short-circuit type according to the characteristic of being capable of bearing the back pressure. A typical structure of the reverse blocking type SITH is shown in fig. 1, where the front surface of the chip is a source and a cathode gate of the device, and an anode drain of the device is located on the back surface of the chip. The current from drain to source is a vertical transistor structure. The typical manufacturing process is as follows:

1. the N-substrate with higher resistance is selected, the resistivity of the N-substrate is usually more than 100ohm. Growing a SiO2 oxide layer on the substrate by CVD or furnace tube thermal oxidation, wherein the thickness of the SiO2 oxide layer is between 3000-6000A. And the front side is coated with photoresist for protection, and the SiO2 oxide layer on the back side is completely etched by hydrofluoric acid.

2. And performing front-side gate photoetching, and then performing etching on the SiO2 oxide layer to define the gate. The gates are independent in cross section but are in series configuration with each other in plan view. Adopting BN (boron nitride) sheet with the same size as the substrate to carry out solid source doping diffusion and propulsion on the substrate in the furnace tube, wherein the propulsion temperature is between 1100 ℃ and 1200 ℃, and the propulsion time is usually between 1-3 h. At this time, the front and back surfaces of the wafer substrate are doped with a high concentration of impurity B, exhibiting P-type, as shown in fig. 2. Typically, the sheet resistance of the back side P-type impurity at this time is between 30-100 ohm/Squre. The diffusion junction depth of the gate P is between 3-6 um. The lateral diffusion of the gate at this time is about 2-4 um. Because the gate is laterally diffused more, the N-channel region between P + becomes relatively small and the current capability of the device becomes weaker. However, if the diffusion depth of P + is simply reduced at this time, another problem is caused: when the depth of the grid junction is too shallow, the subsequent control of the etching depth of the grid is more difficult, and the yield control of the product cannot be guaranteed. In addition, it can be seen from the cross-sectional view that the gate P + is an independent doped block, and in fact, in a planar manner, it is a structure connected in series with each other, and the voltage of the gate P + is always consistent in operation.

N-type impurity masking is carried out on the left and right heavily doped P-type regions on the substrate, which is called as phosphorus dyeing, the phosphorus dyeing method is a POCL3 furnace tube, and the surface of the P-type impurity is subjected to N-type doping by adopting a PCOL3 source under the environment of 900-930C, so that the surface shows an N type. The purpose of this step is to protect the subsequent N-epitaxy from the self-doping effect of the P-type impurity, so that the P-type impurity is reversely diffused into the epitaxy, the resistivity of the epitaxy cannot be controlled, and even the epitaxy is reversely formed (the N-type reverse is P-type).

3. After the front SiO2 oxide layer is removed, N-epitaxy is carried out on the substrate, the resistivity of the epitaxial layer is basically consistent with that of the substrate, the thickness is approximately between 10 and 30 micrometers, the resistivity is more than 100ohm. The fluctuation of the resistivity is very large, so that the control of the device parameters is very difficult, and the yield of the product cannot be ensured.

If the epitaxy is directly carried out before the phosphorus-doping protection in the fourth step is not carried out, because the area of the P-type region exposed outside is very large, P-type impurities B are possibly released to an epitaxial furnace in the epitaxy process on the back surface and the front surface, and therefore the situation of inversion forming of the P-type is possibly caused in the epitaxy process, and the device is made to fail. After the fourth step of phosphorus-staining protection is performed, the surface is of an N type, and N type impurities of the surface are reversely diffused into the epitaxial layer to a certain extent, so that the resistivity of the epitaxial layer is lowered, the parameters of the device are unstable, or the preset target is not reached.

Because the N-type impurity amount on the surface of the P + region is less than the P-type impurity amount, the N-type impurity is compensated by the P-type impurity in the epitaxial thermal process, and the N-type impurity is still P-type after diffusion. When the epitaxy is completed, the P-type impurities simultaneously diffuse to the upper part of the epitaxial layer, and the P-type impurities on the back surface also diffuse deeper.

4. And (3) carrying out cathode N + implantation and diffusion on the front surface, wherein the N + implantation impurity is As or P, the implantation energy is between 50 and 160kev, the implantation dose is between 1E15 and 2E16, and the diffusion junction depth is within 2um, As shown in figure 3.

5. Front side lithography and trench etching are performed as shown in fig. 4. Note that at this step, the depth of the trench must reach the P + gate, but not penetrate the P + gate. Because the junction depth of the P + gate region is relatively thin compared with the thickness of the epitaxial layer, the depth control of the trench is relatively difficult, when the gate trench is too deep, the P + gate region may be etched through, and when the trench is too shallow, the P + gate region may not be reached, which also causes the failure of the device.

6. Metal growth and wet etching. The source and gate electrodes on the front side are defined, and then a back metal deposition is performed to form the anode contact of the device, resulting in the structure shown in fig. 1.

As can be seen from the above process, the manufacturing process of the SITH is complex, and the process control in the manufacturing process is relatively difficult, which is an important reason that the current market promotion of the SITH device is not superior to the traditional power devices such as MOS and IGBT, and mainly has the following difficulties:

(1) the problem of the loss of control of the N-epitaxial resistivity due to the autodoping effect.

(2) The etching depth of the grid is extremely difficult to control, and the device can be failed due to too deep or too shallow etching depth.

(3) Relatively speaking, the lateral diffusion distance of the gate is long, so that the concentration distribution of N-impurities in the channel is uneven, and the pinch-off characteristic of the device is poor. And the current capability of the device is weak due to the relatively low integration level of the device.

Due to the difficulty of the process, the yield of the product is relatively low, and the performance of the device is not good.

Disclosure of Invention

The invention provides a static induction thyristor and a manufacturing method thereof aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

a method for manufacturing a static induction thyristor, comprising the following steps:

etching the surface of the N-substrate to form gate grooves perpendicular to the surface, wherein the width of each gate groove is the same, a first distance is arranged between each gate groove in the middle of the N-substrate, a second distance is arranged between the rest gate grooves on two sides of the N-substrate, the second distance is larger than the width of each gate groove, and the first distance is smaller than the width of each gate groove;

manufacturing a P + epitaxial layer in the gate groove;

manufacturing an N-type epitaxial layer on an N-substrate, wherein the concentration of the N-type epitaxial layer is higher than that of the N-substrate; continuing to grow an N-epitaxial layer on the N-type epitaxial layer;

manufacturing a back P + injection region on the back of the N-substrate;

the P + impurities are diffused by advancing, the P + epitaxial layers in the gate grooves are respectively diffused to form gate regions, and the P + epitaxial layers in the gate grooves which are positioned in the middle of the N-substrate and spaced by a first distance are diffused and completely fused to form a gate lead-out region;

manufacturing an N + injection region on the N-epitaxial layer;

etching the N + injection region and the N-epitaxial layer on the surface of the grid lead-out region to expose the grid lead-out region;

manufacturing a dielectric layer on the N + injection region, and etching the surface of the grid electrode leading-out region and the surfaces of the N + injection regions at two sides of the grid electrode leading-out region to form contact holes;

manufacturing a front metal layer and etching to form front electrodes which fill the contact holes and are mutually spaced, leading out a grid electrode from a grid electrode leading-out region through the front electrodes, and leading out cathode source electrodes positioned at two sides of the grid electrode from an N + injection region through the front electrodes;

and manufacturing a back electrode, and leading out the anode drain electrode from the back P + injection region through the back electrode.

The further technical scheme is that the depth of the gate groove is between 3 and 10um, and the longitudinal junction depth of a gate region formed by diffusion of a P + epitaxial layer in the gate groove is between 5 and 12 um.

The further technical scheme is that the width of the grid groove is between 1 and 3um, and the second distance is larger than twice of the width of the grid groove.

The further technical scheme is that the P + epitaxial layer is manufactured in the gate groove, and the method comprises the following steps:

carrying out P + epitaxial growth on the N-substrate, wherein the epitaxial temperature is less than 900 ℃, and the growth thickness is the same as the width of the gate groove; the grown P + epitaxial layer fills the gate groove and covers the surface of the N-substrate, and the resistivity is less than 0.1 ohm/cm;

and removing the P + epitaxial layer on the surface of the N-substrate by utilizing a CMP (chemical mechanical polishing) process to form the P + epitaxial layer filled in the gate groove.

The further technical proposal is that the thickness of an N-type epitaxial layer manufactured on an N-substrate is less than 1um, and the resistivity is between 10 and 50 ohm/cm; the thickness of the N-epitaxial layer formed by continuous growth on the N-type epitaxial layer is between 10 and 20um, and the resistivity of the N-epitaxial layer is consistent with that of the N-substrate.

The further technical scheme is that a back P + injection region is manufactured on the back of the N-substrate, and the method comprises the following steps: and P + ion implantation is carried out on the back surface of the N-substrate, the implanted ions are N, the impurity concentration is between 2E15 and 2E16, and the implantation energy is between 50 and 300 kev.

The further technical scheme is that the diffusion temperature is between 1000-1150 ℃, the diffusion time is between 1-2 hours, and the diffusion depth of the P + impurities in the P + epitaxial layer and the back P + injection region is within 1 um.

The further technical scheme is that the impurity injected when the N + injection region is manufactured is As or P, the injection energy is between 50 and 160kev, the injection dosage is between 1E15 and 2E16, and the diffusion junction depth is within 1 um.

A static induction thyristor is manufactured by the manufacturing method disclosed by the application.

The beneficial technical effects of the invention are as follows:

the application provides a novel structure of a static induction thyristor, wherein the middle of the front surface of the structure is provided with a grid, two sides of the structure are provided with cathodes, and the back surface of the structure is provided with an anode; the formed grid lead-out region has deeper longitudinal junction depth, so that the process window is larger, the problem that the depth is not enough or the grid lead-out region is etched through is not needed to be worried about, the etching depth control difficulty is lower, and the failure of a device is not easily caused; the width of the formed N-channel is wider, the vertical distance is longer, the impurity distribution is more uniform, and the structure has better channel control capability and larger current capability; the difficulty of the manufacturing process is low, the process control is simple, and the manufactured electrostatic induction thyristor is high in yield and excellent in performance.

Drawings

Fig. 1 is a structural diagram of a conventional static induction thyristor.

Fig. 2 is a block diagram of one manufacturing step of the static induction thyristor of fig. 1.

Fig. 3 is a block diagram of another manufacturing step of the static induction thyristor of fig. 1.

Fig. 4 is a block diagram of another manufacturing step of the static induction thyristor of fig. 1.

Fig. 5 is a structural diagram of a manufacturing step of the method for manufacturing a static induction thyristor according to the present application.

Fig. 6 is a block diagram of another manufacturing step of the method for manufacturing a static induction thyristor according to the present application.

Fig. 7 is a block diagram of another manufacturing step of the method of manufacturing a static induction thyristor according to the present application.

Fig. 8 is a block diagram of another manufacturing step of the method of manufacturing a static induction thyristor according to the present application.

Fig. 9 is a block diagram of another manufacturing step of the method of manufacturing a static induction thyristor according to the present application.

Fig. 10 is a block diagram of another manufacturing step of the method of manufacturing a static induction thyristor according to the present application.

Fig. 11 is a block diagram of another manufacturing step of the method of manufacturing a static induction thyristor according to the present application.

Fig. 12 is a block diagram of another manufacturing step of the method of manufacturing a static induction thyristor according to the present application.

Fig. 13 is a structural diagram of the static induction thyristor manufactured by the manufacturing method of the present application.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses a manufacturing method of an electrostatic induction thyristor, which comprises the following steps:

1. referring to fig. 5, an N-substrate 1 with a high resistivity of over 100 ohm-cm is selected, and the front and back surfaces of the N-substrate are not protected by an oxide layer. And photoetching and etching the gate groove on the front surface of the N-substrate 1, and etching the surface of the N-substrate 1 to form the gate groove 2 vertical to the surface. The width of each gate groove 2 is the same, and each gate groove 2 located in the middle of the N-substrate 1 is spaced by a first distance L1, such as 3 gate grooves 2 in the dashed box in fig. 5, and the first distance L1 is smaller than the width of the gate groove 2. The rest gate grooves 2 on both sides of the N-substrate 1 are spaced apart by a second distance L2. The second distance L2 is greater than the width of the gate groove 2, and the second distance L2 is greater than twice the width of the gate groove 2. In actual manufacturing, the number of the gate grooves 2 spaced apart by the first distance L1 in the middle of the N-substrate 1 may be set as desired, and is not limited to three.

In the present application, the depth of the gate trench 2 is between 3-10um and the width is between 1-3 um.

2. And P + epitaxial growth is carried out above the N-substrate 1 with the gate groove 2 manufactured, and the growth thickness of the epitaxial layer is the same as the width of the gate groove 2. The epitaxial growth adopts low temperature epitaxy, the epitaxial temperature is less than 900 ℃, the P-type impurity is hardly diffused after the epitaxy is completed, and the grown P + epitaxial layer 3 fills the gate trench 2 and covers the surface of the N-substrate 1, please refer to fig. 6. The P + epitaxial layer 3 is doped with high concentration P +, and the resistivity of the P + epitaxial layer is less than 0.1 ohm/cm.

3. And processing the P + epitaxial layer 3 by using a CMP (chemical mechanical polishing) process, removing the P + epitaxial layer 3 on the surface of the N-substrate 1, and forming the P + epitaxial layer 3 filled in the gate groove 2.

4. Referring to fig. 7, an N-type epitaxial layer 4 is formed on a CMP N-substrate 1, wherein the thickness of the N-type epitaxial layer 4 is less than 1um, the concentration of the N-type epitaxial layer 4 is slightly higher than that of the N-substrate 1, and the resistivity is between 10-50 ohm/cm. Compared with the traditional process, the P + epitaxial layer 3 area exposed outside is smaller, namely the P + impurity area exposed outside is greatly reduced, so that the problem of impurity self-diffusion is greatly reduced. The adoption of the N-type epitaxial layer 4 with a slightly higher concentration can effectively prevent the occurrence of the epitaxial inversion.

5. Referring to fig. 8, the N-epitaxial layer 4 continues to grow on the N-epitaxial layer 4, and since the N-epitaxial layer and the N-epitaxial layer belong to the same epitaxial layer, the same reference numerals are used for the N-epitaxial layer and the N-epitaxial layer in the present application. The thickness of the N-epitaxial layer 4 is between 10-20um, and the resistivity is consistent with that of the N-substrate. The problem of autodoping of the N-epitaxial layer 4 is eliminated, and the control of the resistivity is more accurate.

6. Gluing to protect the front side, and performing P + ion implantation on the back side of the N-substrate 1 to form a back P + implantation region 5, wherein the implanted ions are N, the impurity concentration is between 2E15 and 2E16, and the implantation energy is between 50 and 300 kev.

7. The progress is made to diffuse the P + impurities, and at this time, the impurities in the front P + epitaxial layer 3 and the impurities in the back P + implanted region 5 are diffused. The diffusion temperature and time are lower than those of the traditional process, the diffusion temperature is between 1000-1150 ℃, the diffusion time is between 1-2 hours, and the diffusion depth of the P + impurities is within 1 um. Referring to fig. 9, for the front P + epitaxial layer 3, the gate trenches 2 located in the middle of the N-substrate 1 and spaced apart by the first distance L1 are diffused and completely merged to form a large gate lead-out region 6 because of the small pitch, and the remaining gate trenches 2 are not merged and formed into an independent gate region 7 because of the large pitch, and the longitudinal junction depth of the gate region formed by diffusion is between 5-12 um. As can be seen from fig. 9, N-channels are formed between the gate regions 7 and the gate lead-out regions 6, and since the second distance L2 between the gate trenches 2 is larger, the width of the N-channel is wider, the vertical distance is longer, the impurity distribution therein is more uniform, and such a structure will have better channel control capability and larger current capability. As can be seen from fig. 9, the back P + implantation region 5 has a wider width after diffusion.

8. Implantation and activation of N + impurities on the front side are performed on the N-epitaxial layer 4, and cathode N + implantation and diffusion are performed on the front side to form an N + implantation region 8, as shown in fig. 10. The impurity of N + implantation is As or P, the implantation energy is between 50 and 160kev, the implantation dosage is between 1E15 and 2E16, and the diffusion junction depth is within 1 um.

9. And photoetching and etching the grid, and etching the N + injection region 8 on the surface of the grid lead-out region 6 and the N-epitaxial layer 4 to expose the grid lead-out region, please refer to fig. 11. Because the depth of the previous gate groove 2 is 3-10um, and the longitudinal junction depth of the gate lead-out region 6 after the diffusion is finished is 5-12um, compared with the traditional diffused P + gate region, the depth of the gate groove is deeper, the process window is larger during etching, the problem that the depth is not enough or the gate lead-out region 6 is etched through is not needed to be worried about, and the difficulty in controlling the etching depth is lower.

10. Growing a SiO2 dielectric layer on the N + injection region 8, and performing contact hole photolithography and etching on the surface of the gate lead-out region 6 and the surfaces of the N + injection regions 8 at two sides of the gate lead-out region 6 to form a dielectric layer 9, as shown in fig. 12.

11. A front metal layer is grown on the N + implantation region 8, and photolithography and etching of the front metal layer are performed to form front electrodes 10 filling the contact holes and spaced apart from each other, as shown in fig. 13. The grid electrode leading-out region 6 leads out a grid electrode through a front electrode, and the N + injection region 8 leads out cathode source electrodes positioned on two sides of the grid electrode through the front electrode.

12. And growing a metal layer on the back surface of the back P + injection region 5 to form a back electrode 11, and leading out an anode drain from the back P + injection region 5 through the back electrode, as shown in fig. 13, thereby finally manufacturing the electrostatic induction thyristor with the novel structure.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.