Circuit giving consideration to both DC-DC dimming linearity and efficiency and implementation method thereof
阅读说明：本技术 一种兼顾dc-dc调光线性度和效率的电路及其实现方法 (Circuit giving consideration to both DC-DC dimming linearity and efficiency and implementation method thereof ) 是由 王彪 朱春强 雷海涛 张统 于 2019-10-17 设计创作，主要内容包括：本发明公开了一种兼顾DC-DC调光线性度和效率的电路,包括DC-DC芯片U1、电位器U3和主控器U4,主控器U4分别与电位器U3和DC-DC芯片U1连接,DC-DC芯片U1与电位器U3连接,DC-DC芯片U1分别与LED+端和LED-端连接；本发明还公开了一种兼顾DC-DC调光线性度和效率的电路的实现方法。本发明通过主控器U4的IO端调节电位器U3的阻值进而调节DC-DC芯片U1的开关频率,当PWM占空比占比较大的时候降低DC-DC芯片U1的开关频率达到高效率的目的；本发明当PWM占空比占比较小的时候提高DC-DC芯片U1的开关频率达到更好的调光线性度的目的；本发明通过上面两种方式的结合实现兼顾DC-DC调光线性度和效率的目的。(The invention discloses a circuit giving consideration to both DC-DC dimming linearity and efficiency, which comprises a DC-DC chip U1, a potentiometer U3 and a main controller U4, wherein the main controller U4 is respectively connected with the potentiometer U3 and a DC-DC chip U1, the DC-DC chip U1 is connected with the potentiometer U3, and the DC-DC chip U1 is respectively connected with an LED + end and an LED-end; the invention also discloses a realization method of the circuit giving consideration to both DC-DC dimming linearity and efficiency. According to the invention, the resistance value of the potentiometer U3 is adjusted through the IO end of the main controller U4, so that the switching frequency of the DC-DC chip U1 is adjusted, and when the PWM duty ratio is larger, the switching frequency of the DC-DC chip U1 is reduced, thus the purpose of high efficiency is achieved; according to the invention, when the duty ratio of the PWM is smaller, the switching frequency of the DC-DC chip U1 is increased to achieve the purpose of better dimming linearity; the invention realizes the aim of giving consideration to both DC-DC dimming linearity and efficiency by combining the two modes.)
1. A circuit for both DC-DC dimming linearity and efficiency, comprising: the LED driving circuit comprises a DC-DC chip U1, a potentiometer U3 and a master controller U4, wherein the master controller U4 is respectively connected with the potentiometer U3 and the DC-DC chip U1, the DC-DC chip U1 is connected with the potentiometer U3, and the DC-DC chip U1 is respectively connected with an LED + end and an LED-end.
2. The circuit of claim 1, wherein the DC-DC dimming linearity and efficiency are compatible: a pin 1 of the DC-DC chip U1 is connected with an inductor L1, the other end of the inductor L1 is connected with an LED-end, a pin 3 of the DC-DC chip U1 is connected with an LED + end, and a capacitor C1 is connected between the LED + end and the LED-end in parallel.
3. The circuit of claim 2, wherein the DC-DC dimming linearity and efficiency are compatible: the pin 1 of the DC-DC chip U1 is also connected with a diode D1, the other end of the diode D1 is respectively connected with a resistor R1 and a pin 2 of the DC-DC chip U1, and the other end of the resistor R1 is connected with a pin 3 of the DC-DC chip U1.
4. The circuit of claim 3, wherein the DC-DC dimming linearity and efficiency are compatible: and the pin 3 of the DC-DC chip U1 is connected with a power supply input end V-IN end.
5. The circuit of claim 4, wherein the DC-DC dimming linearity and efficiency are compatible: the pin 3 of the DC-DC chip U1 is further connected with a capacitor C2, the other end of the capacitor C2 is respectively connected with a capacitor C3 and a grounding end, and the other end of the capacitor C3 is connected with the pin 5 of the DC-DC chip U1.
6. The circuit of claim 5, wherein the DC-DC dimming linearity and efficiency are compatible with each other: the pin 4 of the DC-DC chip U1 is connected with the PWM end of the master controller U4.
7. The circuit of claim 6, wherein the DC-DC dimming linearity and efficiency are compatible: a pin 1 of the potentiometer U3 is connected with a pin 6 of the DC-DC chip U1, a pin 2 of the potentiometer U3 is connected with an IO end of the main controller U4, and a pin 3 of the potentiometer U3 is connected with a grounding end.
8. The circuit of claim 7, wherein the DC-DC dimming linearity and efficiency are compatible: the pin 10 of the DC-DC chip U1 is connected with a resistor R2, the pin 7 of the DC-DC chip U1 is connected with a capacitor C4, and the other end of the resistor R2, the other end of the capacitor C4, the pin 9 of the DC-DC chip U1 and the pin 8 of the DC-DC chip U1 are respectively connected with a grounding end.
9. The method for implementing a circuit with both DC-DC dimming linearity and efficiency as claimed in any one of claims 1-8, comprising the steps of:
the PWM dimming frequency is 10K, the dimming level is 100, and the duty ratio is 2% and 80%;
(II) obtaining by calculation: when the PWM duty ratio is 2%, a single on-time T1 is 1s/10000/100 is 2uS, and during T1, the DC-DC chip U1 needs to perform at least three switching operations to satisfy the requirement of dimming linearity, which is calculated as follows: when the PWM duty ratio is 2%, the switching frequency F1 of the DC-DC chip U1 is 1s/(2uS/3) 166.666K;
and (iii) when the PMW duty ratio is 80%, the single on-time T2 is 1s/10000/100 × 80 is 80uS, and the DC-DC chip U1 performs at least three switching operations within the time T2 to meet the requirement of dimming linearity, which is calculated as follows: when the PWM duty ratio is 80%, the switching frequency F2 of the DC-DC chip U1 is 1s/(80uS/3) 4.166K;
fourthly, calculating a required switching frequency range according to the predicted dimming frequency and the dimming technology through the calculation, and dynamically adjusting the switching frequency of the DC-DC chip U1 by adjusting the resistance value of the potentiometer U3;
when the duty ratio is 2%, the resistance value of the potentiometer U3 is controlled to be reduced through the IO end of the main controller U4, the switching frequency of the DC-DC chip U1 is improved to be more than 166.666K, and the requirement of dimming linearity is met; when the duty ratio is 80%, the IO end of the main controller U4 is used for controlling the resistance value of the potentiometer U3 to increase, the switching frequency of the DC-DC chip U1 is reduced to be more than 4.166K, and the purpose of reducing the switching loss of the MOS tube to improve the DC-DC efficiency is achieved.
10. The method of claim 9, wherein the DC-DC dimming linearity and efficiency circuit further comprises: a pin 1 of a DC-DC chip U1 is connected with an inductor L1, the other end of the inductor L1 is connected with an LED-end, a pin 3 of the DC-DC chip U1 is connected with an LED + end, a capacitor C1 is connected between the LED + end and the LED-end IN parallel, the pin 1 of the DC-DC chip U1 is further connected with a diode D1, the other end of the diode D1 is respectively connected with a resistor R1 and a pin 2 of the DC-DC chip U1, the other end of the resistor R1 is connected with a pin 3 of the DC-DC chip U1, the pin 3 of the DC-DC chip U1 is connected with a power input end V-IN end, the pin 3 of the DC-DC chip U1 is further connected with a capacitor C2, the other end of the capacitor C2 is respectively connected with a capacitor C3 and a ground end, the other end of the capacitor C3 is connected with a pin 5 of the DC-DC chip U1, a pin 4 of the DC-DC chip U1 is connected with a PWM end of a master controller U4, and a pin 686, a pin 2 of the potentiometer U3 is connected with an IO end of the master controller U4, a pin 3 of the potentiometer U3 is connected with a grounding end, a pin 10 of the DC-DC chip U1 is connected with a resistor R2, a pin 7 of the DC-DC chip U1 is connected with a capacitor C4, and the other end of the resistor R2, the other end of the capacitor C4, a pin 9 of the DC-DC chip U1 and a pin 8 of the DC-DC chip U1 are respectively connected with the grounding end.
Technical Field
The invention belongs to the technical field of single chip microcomputer control, and particularly relates to a circuit giving consideration to both DC-DC dimming linearity and efficiency and an implementation method thereof.
Background
In the existing DC-DC dimming technique, we always escape the problem that dimming linearity and efficiency are contradictory, because these two parameters are mutually influenced. To provide lamp reliability and longevity, it is common practice to reduce the overall temperature of the lamp and increase the efficiency of the power supply. In some applications, the dimming linearity is required to be very good, and the switching frequency of the DC-DC needs to be increased, which increases the switching loss of the MOS inside the DC-DC, thereby reducing the power efficiency of the entire lamp and increasing the heat generation. The prior art has the following defects:
1. dimming linearity and efficiency cannot be considered;
2. DC-DC cannot dynamically and controllably adjust the switching frequency.
Disclosure of Invention
The present invention is directed to a circuit that combines DC-DC dimming linearity and efficiency to solve the above-mentioned problems. The circuit giving consideration to both DC-DC dimming linearity and efficiency has the characteristic of giving consideration to both DC-DC dimming linearity and efficiency.
The invention also aims to provide a realization method of the circuit which gives consideration to both DC-DC dimming linearity and efficiency.
In order to achieve the purpose, the invention provides the following technical scheme: a circuit giving consideration to both DC-DC dimming linearity and efficiency comprises a DC-DC chip U1, a potentiometer U3 and a main controller U4, wherein the main controller U4 is connected with the potentiometer U3 and a DC-DC chip U1 respectively, a DC-DC chip U1 is connected with the potentiometer U3, and the DC-DC chip U1 is connected with an LED + end and an LED-end respectively.
Further, in the invention, pin 1 of the DC-DC chip U1 is connected to an inductor L1, the other end of the inductor L1 is connected to an LED-terminal,
In the invention, the pin 1 of the DC-DC chip U1 is further connected to a diode D1, the other end of the diode D1 is connected to a resistor R1 and a
IN the invention, the
In the invention, the
Further in the present invention, the 4 pin of the DC-DC chip U1 is connected to the PWM terminal of the master U4.
In the invention, pin 1 of the potentiometer U3 is connected with
In the invention, a
Further, the method for implementing the circuit with both DC-DC dimming linearity and efficiency includes the following steps:
the PWM dimming frequency is 10K, the dimming level is 100, and the duty ratio is 2% and 80%;
(II) obtaining by calculation: when the PWM duty ratio is 2%, a single on-time T1 is 1s/10000/100 is 2uS, and during T1, the DC-DC chip U1 needs to perform at least three switching operations to satisfy the requirement of dimming linearity, which is calculated as follows: when the PWM duty ratio is 2%, the switching frequency F1 of the DC-DC chip U1 is 1s/(2uS/3) 166.666K;
and (iii) when the PMW duty ratio is 80%, the single on-time T2 is 1s/10000/100 × 80 is 80uS, and the DC-DC chip U1 performs at least three switching operations within the time T2 to meet the requirement of dimming linearity, which is calculated as follows: when the PWM duty ratio is 80%, the switching frequency F2 of the DC-DC chip U1 is 1s/(80uS/3) 4.166K;
fourthly, calculating a required switching frequency range according to the predicted dimming frequency and the dimming technology through the calculation, and dynamically adjusting the switching frequency of the DC-DC chip U1 by adjusting the resistance value of the potentiometer U3;
when the duty ratio is 2%, the resistance value of the potentiometer U3 is controlled to be reduced through the IO end of the main controller U4, the switching frequency of the DC-DC chip U1 is improved to be more than 166.666K, and the requirement of dimming linearity is met; when the duty ratio is 80%, the IO end of the main controller U4 is used for controlling the resistance value of the potentiometer U3 to increase, the switching frequency of the DC-DC chip U1 is reduced to be more than 4.166K, and the purpose of reducing the switching loss of the MOS tube to improve the DC-DC efficiency is achieved.
Further, IN the present invention, IN the method for implementing the circuit considering both the DC-DC dimming linearity and the efficiency, pin 1 of the DC-DC chip U1 is connected to the inductor L1, the other end of the inductor L1 is connected to the LED-terminal,
Compared with the prior art, the invention has the beneficial effects that:
1. according to the invention, the resistance value of the potentiometer U3 is adjusted through the IO end of the main controller U4, so that the switching frequency of the DC-DC chip U1 is adjusted, and when the PWM duty ratio is larger, the switching frequency of the DC-DC chip U1 is reduced, thus the purpose of high efficiency is achieved;
2. according to the invention, when the duty ratio of the PWM is smaller, the switching frequency of the DC-DC chip U1 is increased to achieve the purpose of better dimming linearity;
3. the invention realizes the aim of giving consideration to both DC-DC dimming linearity and efficiency by combining the two modes.
Drawings
FIG. 1 is a schematic diagram of the circuit structure of the present invention;
FIG. 2 is a graph showing the relationship between the corresponding resistance and the switching frequency according to the relationship between the switching frequency and the resistance;
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
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