阅读说明：本技术 移位寄存器单元、栅极驱动电路及显示装置 (Shifting register unit, grid driving circuit and display device ) 是由 胡琪 顾可可 齐智坚 刘剑峰 陈莹 王�义 范晨晨 于 2021-07-15 设计创作，主要内容包括：本申请实施例提供一种移位寄存器单元、栅极驱动电路及显示装置,移位寄存器单元包括第一复位电路和第一输出电路,第一复位电路与上拉节点、第一电压端和第一复位信号端连接；第一输出电路与第一时钟信号端、第一输出端和上拉节点连接；第一输出端用于与像素晶体管相连,像素晶体管在输入第二导通电平时导通；上述移位寄存器单元在成盒后的点灯测试中,向第一复位信号端输入第一复位电平导通第一电压端和上拉节点,向第一电压端输入第一导通电平导通第一输出电路,使第一时钟信号通过第一输出电路输出至显示区打开像素晶体管,实现显示区放电。并且借助第一输出电路较好的输出能力,保证像素晶体管可以被充分打开,从而实现快速和充分的放电。(The embodiment of the application provides a shift register unit, a grid drive circuit and a display device, wherein the shift register unit comprises a first reset circuit and a first output circuit, and the first reset circuit is connected with a pull-up node, a first voltage end and a first reset signal end; the first output circuit is connected with the first clock signal end, the first output end and the pull-up node; the first output end is used for being connected with the pixel transistor, and the pixel transistor is conducted when a second conducting level is input; in the lighting test after the shift register unit is formed into a box, a first reset level is input to the first reset signal end to conduct the first voltage end and the pull-up node, the first conduction level is input to the first voltage end to conduct the first output circuit, so that the first clock signal is output to the display area through the first output circuit to open the pixel transistor, and the discharge of the display area is realized. And by means of the better output capability of the first output circuit, the pixel transistor can be fully turned on, so that rapid and full discharge is realized.)

1. A shift register unit is characterized by comprising a first reset circuit and a first output circuit, wherein the first reset circuit is connected with a pull-up node, a first voltage end and a first reset signal end and is used for conducting the pull-up node and the first voltage end when a first reset level is input into the first reset signal end;

the first output circuit is connected with a first clock signal end, a first output end and the pull-up node and is used for conducting the first clock signal end and the first output end when the pull-up node is at a first conducting level;

the first output end is used for being connected with a pixel transistor of the control pixel unit, and the pixel transistor is conducted when a second conducting level is input;

in the lighting test after the box formation, the shift register unit is configured to input the first reset level to the first reset signal terminal and the first on level to the first voltage terminal at a stage where the second on level is input to the first clock signal terminal.

2. The shift register cell of claim 1, wherein the first output circuit comprises:

a first transistor, a first electrode of which is connected with the first clock signal end, a second electrode of which is connected with the first output end, and a control electrode of which is connected with the pull-up node;

and one end of the bootstrap capacitor is connected with the pull-up node, and the other end of the bootstrap capacitor is connected with the first output end.

3. The shift register cell of claim 1 or 2, comprising a second output circuit comprising:

a second transistor, a first pole of which is connected with the first clock signal end, a second pole of which is connected with a second output end, and a control pole of which is connected with the pull-up node;

the second output end is used for outputting cascade signals to the cascade shift register units;

the second output circuit is configured to turn on the first clock signal terminal and the second output terminal when the pull-up node is at the first turn-on level.

4. The shift register unit according to claim 3, wherein the first reset circuit comprises a first sub-reset circuit, the first sub-reset circuit is connected to a first sub-reset signal terminal, the pull-up node, the first voltage terminal, the first output terminal, the second output terminal, and a second voltage terminal, and is configured to conduct the pull-up node and the first voltage terminal, conduct the first output terminal and the second voltage terminal, and conduct the second output terminal and the first voltage terminal when the first sub-reset signal terminal inputs a first sub-reset level;

in the lighting test after the box formation, the shift register unit is configured to input the first sub-reset level to the first sub-reset signal terminal, input the first on-level to the first voltage terminal, and input the second on-level to the second voltage terminal at a stage where the second on-level is input to the first clock signal terminal.

5. The shift register cell of claim 4, wherein the first sub-reset circuit comprises:

a third transistor, a control electrode and a first electrode of which are connected with the second reset signal end, and a second electrode of which is connected with the first pull-down node;

a fourth transistor, a first pole of which is connected with the pull-up node, a second pole of which is connected with the first voltage end, and a control pole of which is connected with the first pull-down node;

a fifth transistor, a first pole of which is connected with the second output end, a second pole of which is connected with the first voltage end, and a control pole of which is connected with the first pull-down node;

and a sixth transistor, a first pole of which is connected with the first output end, a second pole of which is connected with the second voltage end, and a control pole of which is connected with the first pull-down node.

6. The shift register cell of claim 5, wherein the first reset circuit comprises a second sub-reset circuit, the second sub-reset circuit comprising:

a seventh transistor, a first pole of which is connected with the pull-up node, a second pole of which is connected with the first voltage end, and a control pole of which is connected with the second sub-reset signal end;

the second sub-reset circuit is used for inputting a second sub-reset level at the second sub-reset signal end, and conducting the pull-up node and the first voltage end;

in the lighting test after the box formation, the shift register unit is configured to input the third sub-reset level to the second sub-reset signal terminal and the first on-level to the first voltage terminal at a stage where the second on-level is input to the first clock signal terminal.

7. The shift register unit according to claim 6, wherein the first reset circuit comprises a third sub-reset circuit, the third sub-reset circuit is connected to a third sub-reset signal terminal, the second voltage terminal, the first output terminal and the pull-up node, and is configured to conduct the pull-up node and the first voltage terminal when a third sub-reset level is inputted to the third sub-reset signal terminal;

in a lighting test after the box formation, the shift register unit is configured to input the first sub-reset level to the first sub-reset signal terminal, input the first on-level to the first voltage terminal, and input the second on-level to the second voltage terminal at a stage where the second on-level is input to the first clock signal terminal and the third sub-reset level is input to the third sub-reset terminal.

8. The shift register cell of claim 7, wherein the third sub-reset circuit comprises:

an eighth transistor having a control electrode and a first electrode connected to the third reset signal terminal, and a second electrode connected to the second pull-down node;

a ninth transistor, a first pole of which is connected to the pull-up node, a second pole of which is connected to the first voltage terminal, and a control pole of which is connected to the second pull-down node;

a tenth transistor, a first pole of which is connected to the second output terminal, a second pole of which is connected to the first voltage terminal, and a control pole of which is connected to the second pull-down node;

and the first pole of the eleventh transistor is connected with the first output end, the second pole of the eleventh transistor is connected with the second voltage end, and the control pole of the eleventh transistor is connected with the second pull-down node.

9. The shift register cell of claim 1, comprising a second reset circuit, the second reset circuit comprising:

a twelfth transistor, a first pole of which is connected with the first output end, a second pole of which is connected with the second voltage end, and a control pole of which is connected with the first output end of the next cascade shift register unit;

the second reset circuit is used for enabling a control electrode input signal of the twelfth transistor to conduct the first output end and the second voltage end of the stage;

in the lighting test after the box formation, the shift register unit is configured to input the first reset level to the first reset signal terminal, input the first on level to the first voltage terminal, and input the second on level to the second voltage terminal at a stage where the second on level is input to the first clock signal terminal.

10. The shift register unit according to any one of claims 4 to 9, wherein the second on level and the first on level are the same high level or low level, and the first voltage terminal and the second voltage terminal are the same input terminal.

11. A gate drive circuit comprising a plurality of cascaded shift register cells of any one of claims 1-10.

12. A display device comprising the gate driver circuit according to claim 11.

13. A discharging method of a display device, wherein a gate driving circuit of the display device comprises a plurality of cascaded shift register cells according to any one of claims 1 to 10, the discharging method comprising:

in a first sequence stage, inputting a first conduction level to a first voltage end and inputting a second conduction level to a first clock signal end;

in a second timing stage, a first reset level is input to the first reset signal terminal.

14. A discharging method of a display device, wherein a gate driving circuit of the display device comprises a plurality of cascaded shift register units according to claim 4 or 5, the discharging method comprising:

in a first sequence stage, inputting a first conduction level to a first voltage end and inputting a second conduction level to a first clock signal end;

and in a second time sequence stage, inputting a first sub reset level to the first sub reset signal end, and inputting the second conduction level to the second voltage end.

15. A discharging method of a display device, wherein a gate driving circuit of the display device comprises a plurality of cascaded shift register cells according to claim 6, the discharging method comprising:

in a first sequence stage, inputting a first conduction level to a first voltage end and inputting a second conduction level to a first clock signal end;

and in a second time sequence stage, inputting a first sub reset level to the first sub reset signal end, inputting a second sub reset level to the second sub reset signal end, and inputting the second conduction level to the second voltage end.

16. A discharging method of a display device, wherein a gate driving circuit of the display device includes a plurality of cascaded shift register cells according to claim 7 or 8, the discharging method comprising:

in a first sequence stage, inputting a first conduction level to a first voltage end, inputting a second conduction level to a first clock signal end, and inputting a third sub-reset level to a third sub-reset signal end;

and in a second time sequence stage, inputting a first sub reset level to the first sub reset signal end, inputting a second sub reset level to the second sub reset signal end, and inputting the second conduction level to the second voltage end.

Technical Field

The embodiment of the application relates to the technical field of display equipment, in particular to a shift register unit, a gate drive circuit and a display device.

Background

In the production and lighting test processes of the display panel, charges are easily induced or remained in the display panel, and if the charges remained in the display panel cannot be well released, the normal operation of the display panel is influenced.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a shift register unit, a gate driving circuit and a display device.

In a first aspect, an embodiment of the present application provides a shift register unit, including a first reset circuit and a first output circuit, where the first reset circuit is connected to a pull-up node, a first voltage terminal, and a first reset signal terminal, and is configured to turn on the pull-up node and the first voltage terminal when a first reset level is input to the first reset signal terminal;

the first output circuit is connected with a first clock signal end, a first output end and the pull-up node and is used for conducting the first clock signal end and the first output end when the pull-up node is at a first conducting level;

the first output end is used for being connected with a pixel transistor of the control pixel unit, and the pixel transistor is conducted when a second conducting level is input;

in the lighting test after the box formation, the shift register unit is configured to input the first reset level to the first reset signal terminal and the first on level to the first voltage terminal at a stage where the second on level is input to the first clock signal terminal.

In the lighting test after the shift register unit is formed into the box, the first reset level may be input to the first reset signal terminal to turn on the first voltage terminal and the pull-up node, and the first turn-on level is input to the first voltage terminal to turn on the first output circuit, so that the first clock signal is output to the display area through the first output circuit to turn on the pixel transistor, thereby realizing discharging. And by means of the better output capability of the first output circuit, the pixel transistors in the display area can be fully turned on, so that rapid and full discharge is realized.

In one possible implementation, the first output circuit includes:

a first transistor, a first electrode of which is connected with the first clock signal end, a second electrode of which is connected with the first output end, and a control electrode of which is connected with the pull-up node;

and one end of the bootstrap capacitor is connected with the pull-up node, and the other end of the bootstrap capacitor is connected with the first output end.

In one possible implementation, a second output circuit is included, the second output circuit including:

a second transistor, a first pole of which is connected with the first clock signal end, a second pole of which is connected with a second output end, and a control pole of which is connected with the pull-up node;

the second output end is used for outputting cascade signals to the cascade shift register units;

the second output circuit is configured to turn on the first clock signal terminal and the second output terminal when the pull-up node is at the first turn-on level.

In a possible implementation manner, the first reset circuit includes a first sub-reset circuit, and the first sub-reset circuit is connected to a first sub-reset signal terminal, the pull-up node, the first voltage terminal, the first output terminal, the second output terminal, and a second voltage terminal, and is configured to, when a first sub-reset level is input to the first sub-reset signal terminal, turn on the pull-up node and the first voltage terminal, turn on the first output terminal and the second voltage terminal, and turn on the second output terminal and the first voltage terminal;

in the lighting test after the box formation, the shift register unit is configured to input the first sub-reset level to the first sub-reset signal terminal, input the first on-level to the first voltage terminal, and input the second on-level to the second voltage terminal at a stage where the second on-level is input to the first clock signal terminal.

In one possible implementation, the first sub-reset circuit includes:

a third transistor, a control electrode and a first electrode of which are connected with the second reset signal end, and a second electrode of which is connected with the first pull-down node;

a fourth transistor, a first pole of which is connected with the pull-up node, a second pole of which is connected with the first voltage end, and a control pole of which is connected with the first pull-down node;

a fifth transistor, a first pole of which is connected with the second output end, a second pole of which is connected with the first voltage end, and a control pole of which is connected with the first pull-down node;

and a sixth transistor, a first pole of which is connected with the first output end, a second pole of which is connected with the second voltage end, and a control pole of which is connected with the first pull-down node.

In one possible implementation, the first reset circuit includes a second sub-reset circuit, and the second sub-reset circuit includes:

a seventh transistor, a first pole of which is connected with the pull-up node, a second pole of which is connected with the first voltage end, and a control pole of which is connected with the second sub-reset signal end;

the second sub-reset circuit is used for inputting a second sub-reset level at the second sub-reset signal end, and conducting the pull-up node and the first voltage end;

in the lighting test after the box formation, the shift register unit is configured to input the third sub-reset level to the second sub-reset signal terminal and the first on-level to the first voltage terminal at a stage where the second on-level is input to the first clock signal terminal.

In a possible implementation manner, the first reset circuit includes a third sub-reset circuit, and the third sub-reset circuit is connected to a third sub-reset signal terminal, the second voltage terminal, the first output terminal, and the pull-up node, and is configured to conduct the pull-up node and the first voltage terminal when a third sub-reset level is input to the third sub-reset signal terminal;

in a lighting test after the box formation, the shift register unit is configured to input the first sub-reset level to the first sub-reset signal terminal, input the first on-level to the first voltage terminal, and input the second on-level to the second voltage terminal at a stage where the second on-level is input to the first clock signal terminal and the third sub-reset level is input to the third sub-reset terminal.

In one possible implementation, the third sub-reset circuit includes:

an eighth transistor having a control electrode and a first electrode connected to the third reset signal terminal, and a second electrode connected to the second pull-down node;

a ninth transistor, a first pole of which is connected to the pull-up node, a second pole of which is connected to the first voltage terminal, and a control pole of which is connected to the second pull-down node;

a tenth transistor, a first pole of which is connected to the second output terminal, a second pole of which is connected to the first voltage terminal, and a control pole of which is connected to the second pull-down node;

and the first pole of the eleventh transistor is connected with the first output end, the second pole of the eleventh transistor is connected with the second voltage end, and the control pole of the eleventh transistor is connected with the second pull-down node.

In one possible implementation, a second reset circuit is included, the second reset circuit including:

a twelfth transistor, a first pole of which is connected with the first output end, a second pole of which is connected with the second voltage end, and a control pole of which is connected with the first output end of the next cascade shift register unit;

the second reset circuit is used for enabling a control electrode input signal of the twelfth transistor to conduct the first output end and the second voltage end of the stage;

in the lighting test after the box formation, the shift register unit is configured to input the first reset level to the first reset signal terminal, input the first on level to the first voltage terminal, and input the second on level to the second voltage terminal at a stage where the second on level is input to the first clock signal terminal.

In a possible embodiment, the second conduction level and the first conduction level are the same high level or low level, and the first voltage terminal and the second voltage terminal are the same input terminal.

In a second aspect, an embodiment of the present application provides a gate driving circuit, including a plurality of cascaded shift register units as described in any one of the embodiments of the first aspect.

In a third aspect, embodiments of the present application provide a display device including the gate driving circuit described in the second aspect.

In a fourth aspect, an embodiment of the present application provides a discharging method of a display device, where the discharging method includes:

in a first sequence stage, inputting a first conduction level to a first voltage end and inputting a second conduction level to a first clock signal end;

in a second timing stage, a first reset level is input to the first reset signal terminal.

In a fifth aspect, an embodiment of the present application provides a discharge method of a display device, where the discharge method includes:

in a first sequence stage, inputting a first conduction level to a first voltage end and inputting a second conduction level to a first clock signal end;

and in a second time sequence stage, inputting a first sub reset level to the first sub reset signal end, and inputting the second conduction level to the second voltage end.

In a sixth aspect, an embodiment of the present application provides a discharge method of a display device, where the discharge method includes:

in a first sequence stage, inputting a first conduction level to a first voltage end and inputting a second conduction level to a first clock signal end;

and in a second time sequence stage, inputting a first sub reset level to the first sub reset signal end, inputting a second sub reset level to the second sub reset signal end, and inputting the second conduction level to the second voltage end.

In a seventh aspect, an embodiment of the present application provides a discharge method of a display device, where the discharge method includes:

in a first sequence stage, inputting a first conduction level to a first voltage end, inputting a second conduction level to a first clock signal end, and inputting a third sub-reset level to a third sub-reset signal end;

and in a second time sequence stage, inputting a first sub reset level to the first sub reset signal end, inputting a second sub reset level to the second sub reset signal end, and inputting the second conduction level to the second voltage end.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or related technologies, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, it is obvious that the drawings in the following description are only examples of the embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a circuit diagram of a shift register unit according to an embodiment of the present disclosure;

fig. 2 is a discharge timing diagram of an lcd panel according to an embodiment of the present disclosure;

FIG. 3 is a circuit diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 4 is a timing chart of a discharge of another lcd panel according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The embodiment of the application provides a display device, which can be a mobile phone, a computer, a television, a display, a vehicle-mounted display device, a touch control integrated machine or a conference large screen and other devices needing content display, wherein the display device comprises a liquid crystal display panel.

The liquid crystal display panel comprises an Array substrate (Array), a color film substrate (CF) and a liquid crystal Layer (LC), wherein the liquid crystal layer is filled between the Array substrate and the color film substrate after the Array substrate and the color film substrate are packed (Cell). The liquid crystal display panel comprises a display area (AA area for short) and a non-display area, wherein the display area is an area for displaying, and a plurality of pixel units arranged in an array are arranged in the display area; the non-display area is arranged in the peripheral area of the display area.

The array substrate is provided with a pixel circuit for controlling the display of the pixel unit in the display area, the pixel circuit comprises a plurality of grid lines and a plurality of data lines which are vertically crossed, and the array substrate further comprises a thin film transistor which is connected between the grid lines and the data lines and is arranged corresponding to the pixel unit, so that the thin film transistor is called as a pixel transistor in the text, and the pixel transistor is turned on when a second on level is input. The pixel transistors of the pixel units in the same row are connected with the same grid line, and the pixel transistors of the pixel units in the same column are connected with the same data line.

The array substrate is provided with a grid electrode driving circuit connected with the grid lines and a data driving circuit connected with the data lines in the non-display area. In the display process of the liquid crystal display panel, outputting a grid scanning signal through a grid driving circuit to scan and access each pixel unit in the pixel array line by line; the data driving circuit can convert display data to be displayed into data voltage signals, and when each row of grid lines is scanned, the data driving circuit writes the data voltage signals into the pixel circuits of the row through the data lines so as to light the pixel units of the row, and finally display of the whole display area is achieved.

The liquid crystal display panel enters a module stage (MDL) after the box is finished, and a lighting Test (Cell Test, abbreviated as CT) is required after the box is finished and before the liquid crystal display panel enters the module stage, so as to ensure that a product entering the MDL stage is normal. The lighting test inputs different timing signals into the liquid crystal display panel to make the liquid crystal display panel present different image pictures, and the display failure is detected.

The liquid crystal display panel is liable to induce and retain electric charges inside the liquid crystal display panel during the production and test processes. Especially for the array substrate manufactured by adopting an Oxide semiconductor (Oxide) process, the leakage current level of the Oxide product is generally 5 to 6 orders of magnitude lower than that of the A-Si product, and the problems of induction and residual charge are more serious. In addition, for a liquid crystal display panel with a high refresh rate (for example, greater than 120HZ), a design of matching a low Cell thickness (Cell gap) with a fast response liquid crystal is usually adopted, and the dielectric constant of the fast response liquid crystal is generally small, and the discharge capability to static electricity is also weak, so that residual charges in the liquid crystal display panel cannot be completely discharged.

The charges remained in the liquid crystal display panel act on the liquid crystal for a long time, so that the liquid crystal is easily polarized, the problem of abnormal lighting is often caused in the module test stage, and the high-lighting defective rate is about 40%. To solve this problem, a lighting time long enough to completely discharge static electricity is required in the module test stage, which seriously affects productivity.

In view of this, embodiments of the present disclosure provide a shift register unit and a gate driving circuit for a liquid crystal display panel, and a discharge timing, i.e., a discharge method, based on the gate driving circuit, for achieving sufficient and fast discharge of residual charges inside the liquid crystal display panel.

In the embodiment of the present application, the Gate driving Circuit is designed by using a Gate Driver on Array (GOA) design, that is, the Gate driving Circuit is integrated on the Array substrate of the display panel, instead of a driving chip made of an external silicon chip, so that a Gate integrated Circuit (Gate IC) part and a fan-out (Fanout) wiring space can be omitted, thereby simplifying the structure of the Array substrate. The gate driving circuit integrated on the array substrate using the GOA technology is also referred to as a GOA circuit.

The grid driving circuit comprises cascaded multi-stage shift register units, and output signals of the current-stage shift register unit are output to the previous-stage shift register unit (if any) except for outputting and driving pixel transistors of the pixel unit of the row to serve as reset signals of the previous-stage shift register unit; and also output to the next stage shift register unit (if any) as an input signal to the next stage shift register unit. In the entire gate driving circuit, the input signal of the first stage shift register unit is the frame start signal STV, and the reset signal is not output. The last stage of shift register unit is connected with a first stage of redundancy shift register unit (Dummy GOA) to realize the reset of the last stage of shift register unit. Therefore, the cascaded multi-stage shift register units are mutually influenced to generate shift pulse signals, and the pixel array is scanned line by line.

For convenience of description and illustration, the nth shift register unit is a shift register unit in a middle position of a cascade relationship, that is, the nth shift register unit is not a first shift register unit or a last shift register unit; the shift register units of the (N-1) th stage and the (N +1) th stage are both present in the gate driving circuit.

It should be noted that the transistors used in the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and the thin film transistors may be oxide semiconductor transistors. The transistors used in the embodiments of the present application are mainly switching transistors according to the role in the circuit. Since the source and the drain of the switching transistor are symmetrical, the source and the drain may be interchanged, one of the source and the drain is referred to as a first pole, the other of the source and the drain is referred to as a second pole, and the gate is referred to as a control pole.

Fig. 1 is a circuit diagram of a shift register unit according to an embodiment of the present disclosure, and as shown in fig. 1, the shift register unit includes a first output circuit, a second output circuit, a first reset circuit, a second reset circuit, a third reset circuit, a fourth reset circuit, a fifth reset circuit, and an input circuit.

The first output circuit includes a first transistor M3 and a bootstrap capacitor C1, a first electrode of the first transistor M3 is connected to the first clock signal terminal, a second electrode of the first transistor M3 is connected to the first output terminal, and a control electrode of the first transistor M3 is connected to the pull-up node PU. The first transistor M3 is turned on when the gate inputs the first on level, and the turned-on first transistor M3 connects the first clock signal terminal and the first output terminal. One end of the bootstrap capacitor C1 is connected to the pull-up node PU, and the other end is connected to the first output terminal.

The first clock signal end is used for receiving an input first clock signal CLK, and the first output end is used for outputting a grid driving signal gout (n) acted on a pixel transistor in the display area; the first output circuit is configured to control whether the first clock signal terminal and the first output terminal are turned on according to the potential of the pull-up node PU, when the potential of the pull-up node PU satisfies the first turn-on level, the first transistor M3 is turned on, and the first clock signal CLK is output to the first output terminal through the first transistor M3.

The second output circuit comprises a second transistor M11, a first pole of the second transistor M11 is connected to the first clock signal terminal, a second pole of the second transistor M11 is connected to the second output terminal, a control pole of the second transistor M11 is connected to the pull-up node PU, the second transistor M11 is turned on when the control pole inputs a first on level, and the turned-on second transistor M11 is connected to the first clock signal terminal and the second output terminal.

The second output terminal is used for outputting a cascade signal OUT _ c (N) applied to a shift register unit cascaded with the shift register unit of the current stage (nth stage), where the cascade signal OUT _ c (N) may be a reset signal applied to a shift register unit of an upper stage (N-1 st stage) or may be an input signal applied to a shift register unit of a next stage (N +1 th stage).

The second output circuit is configured to control whether the first clock signal terminal and the second output terminal are turned on according to the potential of the pull-up node PU, when the potential of the pull-up node PU meets the first turn-on level, the second transistor M11 is turned on, and the first clock signal CLK is output to the second output terminal through the second transistor M11.

As can be seen from the above description, the cascade signal OUT _ c (n) output to the cascade shift register unit and the gate driving signal gout (n) output to the display region are output through two output terminals, so that the load of the output terminals is reduced, the signal interference between the cascade signal OUT _ c (n) and the gate driving signal gout (n) is avoided, and the stability of the gate driving signal gout (n) and the cascade signal OUT _ c (n) is increased, compared with the output by only relying on one output terminal.

The first reset circuit is used for resetting the pull-up node PU under the control of a reset signal, and in the present embodiment, includes a first sub-reset circuit and a second sub-reset circuit, wherein the first sub-reset circuit includes a third transistor M5, a fourth transistor M8, a fifth transistor M12 and a sixth transistor M13.

A control electrode and a first electrode of the third transistor M5 are both connected to the first sub reset signal terminal, and a second electrode of the third transistor M5 is connected to the pull-down node PD; a first pole of the fourth transistor M8 is connected to the pull-up node PU, a second pole of the fourth transistor M8 is connected to the first voltage terminal, and a control pole of the fourth transistor M8 is connected to the pull-down node PD; a first pole of the fifth transistor M12 is connected to the second output terminal, a second pole of the fifth transistor M12 is connected to the second output terminal, and a control pole of the fifth transistor M12 is connected to the pull-down node PD; a first pole of the sixth transistor M13 is connected to the first output terminal, a second pole of the sixth transistor M13 is connected to the second voltage terminal, and a control pole of the sixth transistor M13 is connected to the pull-down node PD.

The first sub-reset signal terminal is configured to receive an input first sub-reset signal VDD, the first voltage terminal is configured to receive an input first voltage signal LVGL, and the second voltage terminal is configured to receive an input second voltage signal VGL. In a possible embodiment, the first voltage signal LVGL and the second voltage signal VGL may be the same voltage signal, that is, the first voltage terminal and the second voltage terminal are the same connection terminal.

The third transistor M5 may output the first sub reset signal VDD to the pull-down node PD after being turned on, and the first sub reset signal VDD output to the pull-down node PD is used to control turning on of the fourth transistor M8, the fifth transistor M12, and the sixth transistor M13.

The first sub reset circuit turns on the third transistor M5, the fourth transistor M8, the fifth transistor M12, and the sixth transistor M13 when the first sub reset signal VDD satisfies the first sub reset level. The fourth transistor M8 is turned on to connect the pull-up node PU to the first voltage terminal, so that the first voltage signal LVGL can be output to the pull-up node PU. The fifth transistor M12 is turned on to connect the second output terminal and the first voltage terminal, so that the first voltage signal LVGL can be output to the second output terminal. The sixth transistor M13 is turned on to connect the first output terminal and the second voltage terminal, so that the second voltage signal VGL can be output to the first output terminal.

The second sub-reset circuit includes a seventh transistor M15, a control electrode of the seventh transistor M15 is connected to the second sub-reset signal terminal, a first electrode of the seventh transistor M15 is connected to the pull-up node PU, and a second electrode of the seventh transistor M15 is connected to the first voltage terminal. The second sub-reset signal terminal is configured to receive an input second sub-reset signal T _ RST, and the first voltage terminal is configured to receive an input first voltage signal LVGL. The seventh transistor M15 is turned on when the second sub-reset signal T _ RST satisfies the second sub-reset level, and the turned-on seventh transistor M15 connects the pull-up node PU to the first voltage terminal, so that the first voltage signal LVGL may be output to the pull-up node PU.

The second reset circuit is used for resetting the first output end under the action of a next stage of gate driving signal and comprises a twelfth transistor M4, wherein the first pole of the twelfth transistor M4 is connected with the first output end, the second pole of the twelfth transistor M4 is connected with the second voltage end, and the control pole of the twelfth transistor M4 is connected with the first output end of the next cascade (N +1) shift register unit.

The twelfth transistor M4 turns on the first output terminal and the second voltage terminal of the stage when the gate of the next cascade gate driving signal Gout (n +1) is inputted to the control electrode; so that the second voltage signal VGL can be output to the first output terminal.

The third reset circuit is used for resetting the pull-up node under the action of the next cascade signal and comprises a thirteenth transistor M12, wherein the first pole of the thirteenth transistor M12 is connected with the pull-up node PU, the second pole of the thirteenth transistor M12 is connected with the first voltage end, and the control pole of the thirteenth transistor M12 is connected with the second output end of the next cascade (N +1) shift register unit.

The thirteenth transistor M12 turns on the pull-up node PU of the present stage and the first voltage terminal when the next-stage cascade signal OUT _ C (n +1) is input to the control electrode, so that the first voltage signal LVGL can be output to the pull-up node PU.

The input circuit comprises an input end and a fourteenth transistor M1, wherein a first pole and a control pole of the fourteenth transistor M1 are connected with the input end, and a second pole of the fourteenth transistor M1 is connected with the pull-up node PU; the input end is used for receiving the cascade signal OUT _ C (N-1) of the shift register unit of the previous stage (N-1), when the input end receives the cascade signal OUT _ C (N-1) of the previous stage, the fourteenth transistor M1 is conducted, and the cascade signal OUT _ C (N-1) of the previous stage is output to the pull-up node PU.

The fourth reset circuit is used for resetting the pull-down node PD under the action of the previous-stage cascade signal and comprises a fifteenth transistor M7, wherein a first pole of the fifteenth transistor M7 is connected with the pull-down node PD, a second pole of the fifteenth transistor M7 is connected with the first voltage end, and a control pole of the fifteenth transistor M7 is connected with the input end. The fifteenth transistor M7 turns on the first voltage terminal of the stage and the pull-down node PD when the next cascade signal OUT _ C (n +1) is inputted to the control electrode.

The fifth reset circuit is used for resetting the pull-down node PD under the action of the pull-up node PU, and includes a sixteenth transistor M6, a first pole of a sixteenth transistor M6 is connected to the pull-down node PD, a second pole of a sixteenth transistor M6 is connected to the first voltage terminal, and a control pole of a sixteenth transistor M6 is connected to the pull-up node PU. The sixteenth transistor M6 turns on the first voltage terminal of the present stage and the pull-down node PD according to the potential of the pull-up node PU.

In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level; the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.

The transistors are described herein by taking N-type transistors as an example, that is, the high level signal is a level signal for controlling the transistors to be turned on, and the first on level, the second on level, the first sub-reset level, the second sub-reset level and the third reset level (the next embodiment) in this document all refer to the high level signal. In addition, the specific value of the high level is subject to the actual setting value, and the value in the embodiment is only referred to.

FIG. 2 is a discharge timing diagram of an LCD panel according to an embodiment of the present invention, corresponding to the shift register unit in FIG. 1, as shown in FIG. 2, in which DB/DG/DR refers to the Cell Test R/G/B Data signal, i.e., the timing signal output to the Data lines in the display area; SW is a Cell Test Data output switch signal. In the discharging process, SW is a high level signal, and DB/DG/DR/Vcom signals are all set to be 0; SW and DB/DG/DR/Vcom in the following timing phase not separately illustrated.

In the discharge timing shown in fig. 2, at the first timing stage T0:

controlling the first clock signal CLK and the first voltage signal LVGL to output a high level signal;

at this time, neither the first output terminal gout (n) nor the second output terminal Out _ c (n) outputs, the pixel transistor in the display area is in an off state, and the residual charges in the liquid crystal display panel do not start to be released.

At a second timing stage T1:

the first clock signal CLK and the first voltage terminal LVGL maintain a high level output;

controlling the first sub reset signal VDD, the second sub reset signal T _ RST and the second voltage signal VGL to output a high level signal; the third transistor M5, the fourth transistor M8, the fifth transistor M12, the sixth transistor M13, and the seventh transistor M15 are turned on;

the first voltage signal LVGL is output to the pull-up node PU through the fourth transistor M8 and the seventh transistor M15, and the first voltage signal LVGL is output to the second output terminal through the fifth transistor M12;

the second voltage signal VGL is output to the first output terminal through the sixth transistor M13;

the first voltage signal LVGL is input to the pull-up node PU, and controls the first transistor M3 and the second transistor M11 to be turned on, and the first clock signal CLK is output to the first output terminal through the first transistor M3;

meanwhile, the twelfth transistor M4 is controlled to be turned on by the gate driving signal Gout (n +1) of the next stage of shift register unit, so that the second voltage signal VGL can be output to the first output terminal;

the gate driving signal gout (n) output by the first output terminal acts on the pixel transistor in the display area to turn on the pixel transistor, so as to discharge the residual charges in the liquid crystal display panel.

At a third timing stage T2:

controlling the output voltages of the second voltage signal VGL and the second sub-reset signal T _ RST to gradually decrease, the output voltage of the sixth transistor M13 to gradually decrease, the first sub-reset signal VDD, the first clock signal CLK and the first voltage signal LVGL to keep high-level output, the gate driving signal gout (n) to keep high-level output to the display area, and the pixel transistors of the display area to keep on-discharge state;

at a fourth timing stage T3:

and controlling the output voltages of the first sub-reset signal VDD, the first clock signal CLK and the first voltage signal LVGL to gradually decrease, gradually setting the output voltage of the first transistor M3 to 0, gradually turning off the first output terminal, and ending the discharge.

In the discharging sequence, the transistors (the first transistor M3, the sixth transistor M13, and the twelfth transistor M4) connected to the first output terminal are all controlled to be turned on, the gate driving signal gout (n) output by the first output terminal is the first clock signal CLK output to the first output terminal through the first transistor M3, and the second voltage signal VGL is output to the first output terminal through the sixth transistor M13 and the twelfth transistor M4; the number of turned-on transistors is large and the first transistor M3 has a good output capability, so that the first output terminal can output the gate driving signal gout (n) with a higher voltage to the display area, and the gate driving signal gout (n) with a higher voltage can enable the pixel transistor to be turned on more fully, released more quickly and fully, thereby saving time.

However, the embodiment of the present application is not limited thereto, and in a possible implementation, only the first transistor M3 may be controlled to be turned on, so as to output the gate driving signal gout (n) with a higher voltage to the display area by utilizing the better conduction capability of the first transistor M3 compared to the other transistors. Correspondingly, the first voltage end LVGL is controlled to output a high level, at least one of the first sub-reset circuit and the second sub-reset circuit is controlled to operate, and the first voltage signal LVGL is output to the pull-up node.

In another possible embodiment, only the first sub-reset circuit may be controlled to operate, and the first transistor M3 and the sixth transistor M13 may be turned on, so that the first clock signal CLK is output to the first output terminal through the first transistor M3, and the second voltage signal VGL is output to the first output terminal through the sixth transistor M13 and the twelfth transistor M4.

Fig. 3 is a circuit diagram of another shift register unit according to an embodiment of the present application, and as shown in fig. 3, the difference from the embodiment shown in fig. 1 is that two sets of first sub-reset circuits are provided, and another first sub-reset circuit is defined as a third sub-reset circuit.

As shown in fig. 3, the first sub-reset circuit includes a third transistor M5A, a fourth transistor M8A, a fifth transistor M12A, and a sixth transistor M13A.

A control electrode and a first electrode of the third transistor M5A are both connected to the first sub reset signal terminal, and a second electrode of the third transistor M5A is connected to the first pull-down node PD 1; a first pole of the fourth transistor M8A is connected to the pull-up node PU, a second pole of the fourth transistor M8A is connected to the first voltage terminal, and a control pole of the fourth transistor M8A is connected to the first pull-down node PD 1; a first pole of the fifth transistor M12A is connected to the second output terminal, a second pole of the fifth transistor M12A is connected to the second output terminal, and a control pole of the fifth transistor M12A is connected to the first pull-down node PD 1; a first pole of the sixth transistor M13A is connected to the first output terminal, a second pole of the sixth transistor M13A is connected to the second voltage terminal, and a control pole of the sixth transistor M13A is connected to the first pull-down node PD 1.

The first sub-reset signal terminal is configured to receive an input first sub-reset signal VDDo, the first voltage terminal is configured to receive an input first voltage signal LVGL, and the second voltage terminal is configured to receive an input second voltage signal VGL. The third transistor M5A may output the first sub reset signal VDDo to the first pull-down node PD1 after being turned on, and the first sub reset signal VDDo output to the first pull-down node PD1 is used to control the fourth transistor M8A, the fifth transistor M12A and the sixth transistor M13A to be turned on.

The first sub reset circuit turns on the third transistor M5A, the fourth transistor M8A, the fifth transistor M12A, and the sixth transistor M13A when the first sub reset signal VDD satisfies the first sub reset level. The fourth transistor M8A is turned on to connect the pull-up node PU to the first voltage terminal, so that the first voltage signal LVGL can be output to the pull-up node PU. The fifth transistor M12A is turned on to connect the second output terminal and the first voltage terminal, so that the first voltage signal LVGL can be output to the second output terminal. The sixth transistor M13A is turned on to connect the first output terminal and the second voltage terminal, so that the second voltage signal VGL can be output to the first output terminal.

The third sub-reset circuit includes an eighth transistor M5B, a ninth transistor M8B, a tenth transistor M12B, and an eleventh transistor M13B.

A control electrode and a first electrode of the eighth transistor M5B are both connected to the third sub-reset signal terminal, and a second electrode of the eighth transistor M5B is connected to the second pull-down node PD 2; a first electrode of the ninth transistor M8B is connected to the pull-up node PU, a second electrode of the ninth transistor M8B is connected to the first voltage terminal, and a control electrode of the ninth transistor M8B is connected to the second pull-down node PD 2; a first pole of the tenth transistor M12B is connected to the second output terminal, a second pole of the tenth transistor M12B is connected to the second output terminal, and a control pole of the tenth transistor M12B is connected to the second pull-down node; a first pole of the eleventh transistor M13B is connected to the first output terminal, a second pole of the eleventh transistor M13B is connected to the second voltage terminal, and a control pole of the eleventh transistor M13B is connected to the second pull-down node PD 2.

The third sub-reset signal terminal is configured to receive an input third sub-reset signal VDDe, the eighth transistor M5B may output the third sub-reset signal VDDe to the second pull-down node PD2 after being turned on, and the third sub-reset signal VDDe output to the second pull-down node PD2 is configured to control turning on the ninth transistor M8B, the tenth transistor M12B and the eleventh transistor M13B.

The third sub-reset circuit turns on the eighth transistor M5B, the ninth transistor M8B, the tenth transistor M12B, and the eleventh transistor M13B when the third sub-reset signal VDDe satisfies the third sub-reset level. The ninth transistor M8B is turned on to connect the pull-up node PU to the first voltage terminal, so that the first voltage signal LVGL can be output to the pull-up node PU. The tenth transistor M12B is turned on to connect the second output terminal and the first voltage terminal, so that the first voltage signal LVGL can be output to the second output terminal. The eleventh transistor M13B is turned on to connect the first output terminal and the second voltage terminal, so that the second voltage signal VGL can be output to the first output terminal.

In addition, the fourth reset circuit includes a fifteenth transistor M7A and a seventeenth transistor M7B, a first pole of the fifteenth transistor M7A is connected to the first pull-down node PD1, a second pole of the fifteenth transistor M7A is connected to the first voltage terminal, and a control pole of the fifteenth transistor M7A is connected to the input terminal. The fifteenth transistor M7A turns on the first voltage terminal of the stage and the first pull-down node PD1 when the next cascade signal OUT _ C (n +1) is inputted to the gate.

A first pole of the seventeenth transistor M7B is connected to the second pull-down node PD2, a second pole of the seventeenth transistor M7B is connected to the first voltage terminal, and a control pole of the seventeenth transistor M7B is connected to the input terminal. The seventeenth transistor M7B turns on the first voltage terminal of the stage and the second pull-down node PD2 when the next cascade signal OUT _ C (n +1) is inputted to the gate.

The fifth reset circuit is configured to reset the pull-down node PD under the action of the pull-up node PU, and includes a sixteenth transistor M6A and an eighteenth transistor M6B, a first pole of the sixteenth transistor M6A is connected to the first pull-down node PD1, a second pole of the sixteenth transistor M6A is connected to the first voltage terminal, and a control pole of the sixteenth transistor M6A is connected to the pull-up node PU. The sixteenth transistor M6A turns on the first voltage terminal of the stage and the first pull-down node PD1 according to the voltage level of the pull-up node PU.

A first pole of the eighteenth transistor M6B is connected to the second pull-down node PD2, a second pole of the eighteenth transistor M6B is connected to the first voltage terminal, and a control pole of the eighteenth transistor M6B is connected to the pull-up node PU. The eighteenth transistor M6B turns on the first voltage terminal of the present stage according to the potential of the pull-up node PU to be connected to the second pull-down node PD 2.

Fig. 4 is a discharge timing diagram of an lcd panel according to an embodiment of the present application, corresponding to the shift register unit in fig. 3, as shown in fig. 4,

at the first timing stage T0:

controlling the third sub reset signal VDDe, the first clock signal CLK, and the first voltage signal LVGL to output a high level signal;

at this time, the eighth transistor M5B is turned on, the third sub reset signal VDDe is output to the second pull-down node PD2, and the third sub reset signal VDDe output to the second pull-down node PD2 turns on the ninth transistor M8B, the tenth transistor M12B, and the eleventh transistor M13B.

The first voltage signal LVGL is output to the pull-up node PU through the ninth transistor M8B, and the first voltage signal LVGL is output to the second output terminal through the tenth transistor M12B;

the first voltage signal LVGL is input to the pull-up node PU, and controls the first transistor M3 and the second transistor M11 to be turned on, and the first clock signal CLK is output to the first output terminal through the first transistor M3; the gate driving signal gout (n) output by the first output terminal acts on the pixel transistor in the display area to turn on the pixel transistor, so as to discharge the residual charges in the liquid crystal display panel.

At a second timing stage T1:

the first clock signal CLK and the first voltage terminal LVGL maintain a high level output;

controlling the first sub reset signal VDDo, the second sub reset signal T _ RST and the second voltage signal VGL to output a high level signal; the third transistor M5A, the fourth transistor M8A, the fifth transistor M12A, the sixth transistor M13A, and the seventh transistor M15 are turned on;

the first voltage signal LVGL is output to the pull-up node PU through the fourth transistor M8A and the seventh transistor M15, and the first voltage signal LVGL is output to the second output terminal through the fifth transistor M12A;

the second voltage signal VGL is output to the first output terminal through the sixth transistor M13A and the eleventh transistor M13B;

the first voltage signal LVGL is input to the pull-up node PU, and controls the first transistor M3 and the second transistor M11 to be turned on, and the first clock signal CLK is output to the first output terminal through the first transistor M3; the gate driving signal gout (n) output by the first output terminal acts on the pixel transistor in the display area to turn on the pixel transistor, so as to discharge the residual charges in the liquid crystal display panel.

At a third timing stage T2:

controlling the output voltages of the second voltage signal VGL and the second sub-reset signal T _ RST to gradually decrease, the output voltages of the sixth transistor M13A and the eleventh transistor M13B to gradually decrease, the output voltages of the first sub-reset signal VDDo, the third sub-reset signal VDDe, the first clock signal CLK and the first voltage signal LVGL are kept at high level, the gate driving signal gout (n) keeps high voltage output to the display area, and the pixel transistors of the display area still keep on-discharge state;

at a fourth timing stage T3:

the output voltages of the first sub-reset signal VDDo, the third sub-reset signal VDDe, the first clock signal CLK and the first voltage signal LVGL are controlled to gradually decrease, the output voltage of the first transistor M3 gradually becomes 0, the first output terminal is gradually turned off, and the discharging is ended.

In the above embodiments, two sets of first sub-reset circuits are taken as an example for description, and it is obvious that the embodiments of the present application do not limit the number of sets of the first sub-reset circuits.

The embodiment of the present application also provides a discharging method of a display device, where the display device includes the gate driving circuit in the above embodiment, and the discharging method includes:

in a first sequence stage, inputting a first conduction level to a first voltage end and inputting a second conduction level to a first clock signal end;

in a second timing stage, a first reset level is input to the first reset signal terminal.

In an embodiment mode of the shift register unit in the gate driving circuit including the first sub-reset circuit, the discharge method includes:

in a first sequence stage, inputting a first conduction level to a first voltage end and inputting a second conduction level to a first clock signal end;

and in the second time sequence stage, inputting the first sub reset level to the first sub reset signal end and inputting the second conduction level to the second voltage end.

In an embodiment mode of a shift register unit in a gate driving circuit including a first sub-reset circuit and a second sub-reset circuit, the discharging method includes:

in a first sequence stage, inputting a first conduction level to a first voltage end and inputting a second conduction level to a first clock signal end;

and in the second time sequence stage, inputting a first sub reset level to the first sub reset signal end, inputting a second sub reset level to the second sub reset signal end, and inputting a second conduction level to the second voltage end.

In an embodiment mode that a shift register unit in a gate driving circuit comprises a first sub-reset circuit, a second sub-reset circuit and a third sub-reset circuit, the discharging method comprises the following steps:

in a first period, inputting a first conduction level to a first voltage end, inputting a second conduction level to a first clock signal end, and inputting a third sub-reset level to a third sub-reset signal end;

and in the second time sequence stage, inputting a first sub reset level to the first sub reset signal end, inputting a second sub reset level to the second sub reset signal end, and inputting a second conduction level to the second voltage end.

In the description of the embodiments of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the embodiments of the present application, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected unless explicitly stated or limited otherwise; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. Specific meanings of the above terms in the embodiments of the present application can be understood in specific cases by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application can be combined with each other as long as they do not conflict with each other.

So far, the technical solutions of the present application have been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present application is obviously not limited to these specific embodiments. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the present application, and the technical scheme after the changes or substitutions will fall into the protection scope of the present application.