阅读说明：本技术 用于调整硅化镍的电阻率的工艺整合方法 (Process integration method for adjusting resistivity of nickel silicide ) 是由 任河 于敏锐 梅裕尔·B·奈克 于 2018-06-12 设计创作，主要内容包括：本文描述在形成互连中使用的用于沉积低电阻率硅化镍层的方法和使用所述方法形成的电子装置。在一个实施方式中,一种用于沉积层的方法包括：将基板定位在处理腔室中的基板支撑件上,所述处理腔室具有设置在所述处理腔室中的镍靶材和硅靶材,所述镍靶材和硅靶材的面向基板部分各自具有从基板的面向靶材表面的在约10度与约50度之间的角度；使气体流动到处理腔室中；向镍靶材施加射频功率并且同时向硅靶材施加直流功率；分别从硅靶材和镍靶材同时地溅射硅和镍；并且在基板上沉积Ni<Sub>x</Sub>Si<Sub>1-x</Sub>层,其中x在约0.01与约0.99之间。(Methods for depositing low resistivity nickel silicide layers for use in forming interconnects and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes: positioning a substrate on a substrate support in a process chamber having a nickel target and a silicon target disposed therein, the process chamberThe substrate-facing portions of the nickel target and the silicon target each have an angle between about 10 degrees and about 50 degrees from the target-facing surface of the substrate; flowing a gas into a processing chamber; applying radio frequency power to a nickel target and simultaneously applying direct current power to a silicon target; simultaneously sputtering silicon and nickel from a silicon target material and a nickel target material, respectively; and depositing Ni on the substrate x Si 1‑x A layer, wherein x is between about 0.01 and about 0.99.)

1. A method for depositing a layer, the method comprising:

positioning a substrate on a substrate support in a process chamber having a nickel target and a silicon target disposed therein, substrate-facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from a target-facing surface of the substrate;

flowing a gas into the process chamber;

applying radio frequency power to the nickel target and simultaneously applying direct current power to the silicon target;

simultaneously sputtering silicon and nickel from the silicon target material and the nickel target material, respectively; and

depositing Ni on the substrate_xSi_1-xA layer, wherein x is between about 0.01 and about 0.99.

2. The method of claim 1, wherein the Ni_xSi_1-xThe layer has a resistance of less than about 30 μ ohm-cmAnd (4) rate.

3. The method of claim 2, wherein x is between about 0.4 and 0.6.

4. The method of claim 3, wherein the DC power is between about 800 watts and about 1200 watts.

5. The method of claim 4, wherein the radio frequency power is between about 300 watts and about 500 watts.

6. The method of claim 1, wherein the Ni_xSi_1-xThe layer has a resistivity between about 30 μ ohm-cm and about 60 μ ohm-cm.

7. The method of claim 6, wherein x is greater than about 0.6.

8. The method of claim 1, wherein the Ni_xSi_1-xThe layer has a resistivity between about 60 μ ohm-cm and about 200 μ ohm-cm.

9. The method of claim 8, wherein x is less than about 0.4.

10. A method of forming a device, comprising:

positioning a substrate on a substrate support within a processing chamber, the substrate having a plurality of features disposed thereon and a plurality of openings disposed between the plurality of features;

flowing a gas into the process chamber;

applying radio frequency power to a nickel target and simultaneously applying direct current power to a silicon target, wherein the nickel target and the silicon target are disposed in the process chamber and surfaces of the nickel target and the silicon target facing the substrate each have an angle of between about 10 degrees and about 50 degrees with the surface of the substrate facing the targets;

simultaneously sputtering silicon and nickel from the silicon target material and the nickel target material, respectively; and

depositing Ni on the substrate_xSi_1-xLayers to form a plurality of interconnects, wherein x is between about 0.01 and about 0.99.

11. An electronic device, comprising:

a patterned substrate comprising a dielectric layer and a plurality of interconnect features disposed in the dielectric layer, wherein the plurality of interconnect features comprise Ni_xSi_1-xAnd has an effective resistivity of 200 muohm-cm or less.

12. The electronic device of claim 11, wherein x is between about 0.4 and about 0.6.

13. The electronic device of claim 12, wherein one or more of the interconnect features has a width of less than about 20 nm.

14. The electronic device of claim 13, wherein one or more of the interconnect features has a height that is about 2 times or more the width.

15. The electronic device of claim 14 wherein the plurality of interconnects have an effective resistivity of less than about 30 μ ohm-cm.

Technical Field

Embodiments described herein relate generally to the field of semiconductor device manufacturing, and more particularly, to a method of forming a metal silicide interconnect using a co-sputtering Physical Vapor Deposition (PVD) process in a multi-cathode PVD chamber, and an electronic device formed using the same.

Background

As the circuit density of next generation devices increases and transistor dimensions continue to shrink, the properties of materials used for wire interconnects (wireinterconnections) begin to dominate device performance for the main performance metrics (metrics) including power consumption, resistance-capacitance (RC) delay, and reliability. Copper has been used for wire interconnects in advanced USLI and VSLI technologies for the past two decades because copper typically exhibits relatively low resistivity and, thus, high conductivity. However, as the width of the interconnect wiring (wiring) of the device shrinks to the size of the electron mean free path (eMPP) of the interconnect wiring material or less, the effective resistivity (effective resistivity) of the material increases due to unwanted sidewall electron scattering at the surface of the interconnect wiring and grain boundary interfaces of the material. Thus, the effective resistivity of copper typically used in interconnects begins to increase for copper interconnects having widths below the 39nm eMFP of copper, and increases significantly for interconnects having widths of 20nm or less. Furthermore, the barrier layer used with the copper interconnect to prevent unwanted diffusion of the copper material to the surrounding dielectric material contributes to an increased overall resistivity of the wire interconnect.

Accordingly, there is a need in the art for alternative conductor materials.

Disclosure of Invention

Embodiments described herein relate generally to methods of manufacturing semiconductor devices, and in particular, to methods of co-sputtering a nickel silicide layer onto a substrate in a multi-cathode Physical Vapor Deposition (PVD) chamber.

In one embodiment, a method for depositing a layer includes: positioning a substrate on a substrate support in a process chamber having a nickel target and a silicon target disposed therein, substrate-facing portions of the nickel target and the silicon target each having an angle between about 10 degrees and about 50 degrees from a target-facing surface of the substrate; flowing a gas into a processing chamber; applying radio frequency power to a nickel target and simultaneously applying direct current power to a silicon target; simultaneously sputtering silicon and nickel from a silicon target material and a nickel target material, respectively; and depositing Ni on the substrate_xSi_1-xA layer, wherein x is between about 0.01 and about 0.99.

In another embodiment, a method of forming an apparatus comprises: positioning a substrate on a substrate support within a processing chamber, the substrate having a plurality of features disposed thereon and a plurality of openings disposed between the plurality of features; flowing a gas into a processing chamber; applying radio frequency power to a nickel target and simultaneously applying direct current power to a silicon target, wherein the nickel target and the silicon target are disposed in a process chamber, and surfaces of the nickel target and the silicon target facing the substrate each have an angle of between about 10 degrees and about 50 degrees with a surface of the substrate facing the target; simultaneously sputtering silicon and nickel from a silicon target material and a nickel target material, respectively; and depositing Ni on the substrate_xSi_1-xLayers to form a plurality of interconnects, wherein x is between about 0.01 and about 0.09.

In another embodiment, an electronic device is characterized by a patterned substrate comprising a dielectric layer and a plurality of interconnect features disposed in the dielectric layer, wherein the plurality of interconnect features comprise Ni having an effective resistivity of about 30 μ ohm-cm or less_xSi_1-xX is between about 0.4 and about 0.6, and the one or more interconnect features have a width less than about 20nm and a height that is about 2 times the width or more.

In another embodiment, a method of depositing a layer comprising nickel and silicon comprises: positioning a substrate on a substrate support in a process chamber having a nickel target and a silicon target having an angle between about 10 degrees and about 50 degrees from a surface of the substrate support; flowing an inert gas into the processing chamber; applying radio frequency power to a nickel target and applying direct current power to a silicon target, wherein a ratio of radio frequency power to direct current power is between about 1:1 and about 1: 12; and co-sputtering Ni_xSi_1-xLayer to the substrate, Ni_xSi_1-xThe layer has a resistivity of less than about 200 μ ohm-cm, where x is between about 0.01 and 0.99.

Description of the drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

Fig. 1 shows the relationship between wire interconnect scaling (scale) to 50nm and less and the material selection for the wire interconnect.

Fig. 2A is a cross-sectional view of a multi-cathode processing chamber for practicing embodiments disclosed herein.

Fig. 2B illustrates the relative position of the target and substrate during deposition in the process chamber of fig. 2A.

Figure 2C is a schematic diagram illustrating a shield assembly disposed in a chamber lid of a processing chamber for practicing the methods disclosed herein.

Fig. 3A illustrates the resistivity of a nickel silicide layer deposited according to embodiments disclosed herein.

Fig. 3B compares the resistivity of a copper layer, an annealed cobalt layer, an annealed ruthenium layer, and a nickel silicide layer deposited according to the methods described herein.

Fig. 4 is a flow chart illustrating a method of depositing a nickel silicide layer onto a substrate according to embodiments disclosed herein.

Fig. 5A-5C illustrate the formation of a wire interconnect using the method set forth in fig. 4.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

Detailed Description

Embodiments of the present disclosure generally describe methods for depositing a nickel silicide layer onto a substrate, including over previously formed layers on the substrate, using a co-sputtering Physical Vapor Deposition (PVD) process in a multi-cathode PVD chamber, and in particular for controlling the resulting resistivity, composition, and crystal orientation of the deposited nickel silicide layer by controlling the power and power ratio applied to the nickel and silicon targets.

Fig. 1 shows the relationship between trench scaling to thicknesses of 50nm and less and material selection for wire interconnects, where scaling involves a change in the line resistivity of the selected material (wire resistivity) as the wire narrows to reach and exceed the material's electron mean free path, eMFP. In fig. 1, the interconnect wire is in a trench disposed in a dielectric material and has a width (trench CD) of 50nm and less and an aspect ratio (depth to width) of 2: 1. Fig. 1 shows the relationship between the effective resistivity of copper 105, cobalt 103 and nickel suicide 101, with a liner/barrier layer interposed between the copper, cobalt or nickel suicide and the dielectric material to prevent diffusion of copper, cobalt or nickel suicide atoms into the surrounding dielectric material.

As used herein, effective resistivity refers to the measured resistivity of a material, not the bulk resistivity (bulk resistivity) of a material. As can be seen from fig. 1, the effective resistivity of the three materials began to increase meaningfully as the width of the wire interconnect was scaled to 20nm and less, but the increase in resistivity of cobalt 103 (with an eMFP of 9.5) with decreasing trench CD was incrementally less than the increase in resistivity of copper 105, making cobalt 103 a promising material for trench CDs of 10nm and less; in fact, the effective resistivity of copper, which is less than the effective resistivity of cobalt for features in the 10nm to 50nm width range, becomes greater than the effective resistivity of cobalt at feature sizes slightly less than 10nm wide. The incremental increase in effective resistivity of nickel silicide 101 (having an eMFP of less than 10nm depending on the composition of nickel and silicon) is less than the incremental increase in effective resistivity of cobalt 103, making nickel silicide 101 a promising material for wire interconnects with trench CDs of 7nm to 8nm and less, and the effective resistivity of cobalt becomes greater than that of nickel silicide at line widths of about 6 nm.

Fig. 2A is a cross-sectional view of a multi-cathode Physical Vapor Deposition (PVD) processing chamber 200 for depositing nickel silicide onto a substrate 228 according to methods described herein. Fig. 2C is a schematic diagram illustrating a cathode shield configuration disposed in a chamber lid 240 of the process chamber 200. The cathode shield configuration shown in fig. 2C is not shown in fig. 2A, however, the methods described herein include using a cathode shield configuration, such as the cathode shield configuration shown in fig. 2C with the processing chamber 200. In this embodiment, the process chamber 200 is configured to process a single substrate, such as a substrate 228 disposed on the substrate support 226 in fig. 2A. In other embodiments, the methods described herein are for a substrate configured to process a plurality of substrates disposed on a substrate turntable.

The process chamber 200 is characterized herein by one or more sidewalls 230, a chamber lid 240, and a chamber bottom 234 defining a process volume 299. The processing volume 299 is fluidly coupled to a vacuum 209, such as one or more dedicated vacuum pumps, and has a substrate support 226 disposed in the processing volume 299. The substrate support 226 includes a shaft 224 surrounded by a substrate support bellows 222 outside the process chamber and sealingly extending through the chamber bottom 234, the shaft 224 raising or lowering the substrate support 226 to facilitate transfer of a substrate 228 to and from the process chamber 200. The substrate 228 is loaded into the processing volume 299 through a sealable opening 232 in one of the one or more sidewalls 230, which is conventionally sealed with a door or valve (not shown) during the deposition process. In some embodiments, the shaft 224 is further coupled to an actuator 220, the actuator 220 rotating the shaft 224, and thereby rotating a substrate 228 disposed on a substrate support 226 during processing; in some cases, this improves the thickness uniformity of the deposited film on the surface of the substrate 228.

The processing chamber 200 includes a plurality of cathodes 250A-250E, herein the plurality of cathodes includes five cathodes (cathodes 250D-250E are shown in fig. 2C) disposed through openings in the chamber lid 240, wherein each cathode of the plurality of cathodes 250A-250E is configured to sputter one or more materials onto the substrate 228. In this embodiment, the first cathode 250A is configured to sputter nickel from the nickel target 252 while the second cathode 250B is configured to simultaneously sputter (co-sputter) silicon from the silicon target 262 to deposit a uniform layer of nickel silicide on the surface of the substrate 228. Herein, the third cathode 250C is configured to sputter titanium from the titanium target 264 in the presence of a nitrogen-containing reactive gas (such as nitrogen or ammonia) to deposit a layer of titanium nitride on the surface of the substrate 228. In other embodiments, the third cathode 250C is configured to sputter titanium nitride from a titanium nitride target.

One or more of the plurality of cathodes 250A-250E includes a magnetic assembly 254 and a target backing plate 253, the magnetic assembly 254 disposed within a housing volume 267 defined by the cathode housing 255, the target backing plate 253 having a target, such as a nickel target 252, disposed on the target backing plate 253. The magnetic assembly 254 is coupled to a rotation shaft 256, the rotation shaft 256 is coupled to a motor 258, and the motor 258 rotates the rotation shaft 256 and, thus, the magnetic assembly 254 over the rear non-sputtering side of the target backing plate 253. Each of the plurality of cathodes 250A-250E is coupled to a power source, such as a Radio Frequency (RF) power source 263 coupled to the first cathode 250A and coupled to the third cathode 250C, or a Direct Current (DC) power source 265 coupled to the second cathode 250B. In other embodiments, the dc power supply 265 is a pulsed dc power supply. Sputtering gases and/or reactive gases are provided to the processing chamber through a gas inlet 211.

Each of the plurality of cathodes 250A-250E includes a bellows 257 and an angle adjustment mechanism (not shown) coupled to the exterior of the chamber lid 240 and to the cathode housing 255. Bellows 257 serves to maintain the vacuum condition of the processing volume 299 by preventing atmospheric air from entering the processing volume 299 and preventing process gases from leaking from the processing volume 299 to the ambient environment. The angle adjustment mechanism is used to change and then fix the position of the cathode housing 255, and thus the position of a target, such as the nickel target 252 of the first cathode 250A, disposed therein, at an angle relative to the surface of the substrate 228, as described in further detail with reference to fig. 2B.

Fig. 2B illustrates the relative position of a target 260 (such as any of a plurality of cathodes 250A-250E in the processing chamber 200) and the substrate 228 during deposition. Herein, the substrate 228 has a diameter of 300mm and the target 260 has a diameter smaller than the diameter of the substrate 228, such as less than about 300mm, such as between about 100mm and about 300 mm. During processing, the substrate 228 is moved to a processing position by raising the substrate support 226 shown in fig. 2A to a position in which the horizontal plane of the surface of the substrate 228 is spaced a vertical distance Z1 from the target 260. Vertical distance Z1 is measured from the position of the target closest to the horizontal plane of the surface of substrate 228. Herein, Z1 is between about 100mm and about 400mm, such as between about 150mm and about 350mm, such as between about 200mm and about 300mm, such as between about 225mm and about 275 mm. The plane of the surface of the target 260 is angled relative to the horizontal plane of the surface of the substrate 228 at an angle θ, where θ is between about 10 degrees and about 50 degrees, such as between about 20 degrees and about 40 degrees, between about 20 degrees and about 30 degrees, or between about 30 degrees and about 40 degrees.

Figure 2C is a schematic diagram illustrating the shield assembly 282 disposed in the chamber lid 240 of the processing chamber 200. The shield assembly 282 includes a plurality of vertical walls 285 extending between each of the plurality of cathodes 250A-250E, wherein the plurality of vertical walls 285 are coupled at a centerline and extend radially outward from the centerline. By providing a physical barrier between the plurality of upright walls 285, the plurality of upright walls 285 are positioned to prevent interference between two or more of the plurality of cathodes 250A-250E and/or mutual target contamination during processing. The interaction refers to unwanted electrical interference from one cathode power supply, such as rf power supply 263, with another cathode power supply, such as dc power supply 265, during the co-sputtering process. Mutual target contamination refers to unwanted deposition of material from one target onto another in co-sputtering and/or sequential sputtering processes.

In some embodiments, the processing chamber 200 further includes one or more cylindrical shields 280 coupled to one or more of the plurality of cathodes 250A-250E as shown in fig. 2C. In those embodiments, the one or more cylindrical shields 280 surround the cathode housing 255 and thereby surround the target material disposed in the cathode housing 255 of the one or more cathodes of the plurality of cathodes 250A-250C. The cylindrical shield 280 is configured to prevent interference and mutual target contamination by providing a physical barrier between the cathodes in the chamber. In other embodiments, the process chamber 200 includes the cylindrical shield 280 and does not include the shield assembly 282.

Fig. 3A illustrates the resistivity of a nickel silicide layer deposited according to embodiments disclosed herein. Lines 316, 317, 318, 319 each represent the ratio of power supplied to the nickel cathode to the power supplied to the silicon cathode during the co-sputtering PVD process, wherein the power supplied to the nickel cathode (such as first cathode 250A) is increased from the first power ratio represented by line 316 to the fourth power ratio represented by line 319 compared to the power supplied to the silicon cathode (such as second cathode 250B), thereby increasing the ratio of nickel to silicon in the deposited layer such that the nickel silicide layer deposited at the first power ratio 316 is a silicon rich layer and the nickel silicide layer deposited at the fourth power ratio 319 is a nickel rich layer. The resistivities of the resulting nickel silicide layers R1 through R8 deposited using the power ratios of lines 316 through 319 are shown in table 1. R1 and R5 were each deposited using a first power ratio 316, R2 and R6 were each deposited using a second power ratio 317, R3 and R7 were each deposited using a third power ratio 318, and R4 and R8 were each deposited using a fourth power ratio 319.

As shown in fig. 3, R1-R4 were all deposited at the same dc power while the rf power to the nickel target was varied; all of R4 through R8 were deposited at the same rf power while the dc power to the silicon target was varied. The effective resistivity of the material layers of ratios R1 to R8 is calculated by measuring the sheet resistance of the deposited film, measuring the thickness of the deposited film, and estimating the effective resistivity of the film from the sheet resistance and film thickness measurements. Surprisingly, the resistivity of the deposited layer does not change linearly with increasing nickel concentration, for example, while the nickel silicide composition at ratio R2 shows a significant reduction in effective resistivity compared to the nickel silicide composition at ratio R1 (which would be expected due to the higher concentration of more conductive nickel being present in the nickel silicide composition at ratio R2), the nickel silicide compositions at ratios R3 and R4 have a higher concentration of nickel than the nickel silicide composition at ratio R2, but also have an effective resistivity that increases from the nickel silicide composition at ratio R2. Also unexpected is the difference in resistivity in nickel silicide layers deposited using the same power ratio (such as the first power ratio 316), but at different radio frequency and direct current power levels, where the concentration of nickel and silicon in the nickel silicide composition at the ratios R1 and R4 are substantially the same.

While not being limited to any particular theory, it is believed that, in addition to nickel and silicon concentrations, the crystal orientation of the nickel silicide layer deposited according to the methods described herein may be controlled by adjusting the power levels applied to the nickel and silicon cathodes and thereby adjusting the corresponding power ratios to deposit the nickel silicide layer with a desired crystal orientation and/or a desired effective resistivity. Furthermore, the methods described herein may be used to deposit a nickel silicide layer having a desired crystallographic orientation without a post-deposition annealing process, or at least without a high temperature annealing process. This is beneficial in interconnect areas (interconnect levels) where high temperatures are undesirable due to the low thermal budget of low-K dielectric materials.

TABLE 1

Fig. 3B compares the effective resistivity of layers of different materials, such as copper 321, annealed cobalt 323, annealed ruthenium 324, and nickel silicide 325, where the nickel silicide 325 is deposited according to the methods described herein. The effective resistivity is measured for layer thicknesses of 25nm and less. As shown in fig. 3b, the nickel silicide 325 layer deposited according to the methods described herein continues to have a significantly lower effective resistivity than other interconnect materials at blanket film thicknesses of less than about 10nm, making nickel silicide a suitable material for interconnect widths of less than 10 nm.

Fig. 4 is a flow chart illustrating a method of depositing a nickel silicide layer onto a substrate, or onto a feature disposed on a substrate. Fig. 5A-5C illustrate the formation of a wire interconnect using the method 400 set forth in fig. 4. At activity 410, the method 400 includes positioning a substrate (such as a patterned substrate) on a substrate support in a multi-cathode processing chamber. A patterned substrate is illustrated in fig. 5A, wherein the pattern comprises a plurality of features 535 having a height H and a plurality of openings 537 having a width W disposed between the plurality of features 535. Herein, the plurality of features 535 are formed from a dielectric material, such as silicon oxide, SIN, SiOC, SIC, or a low-k polymer (such as polyamide), or a combination thereof. The width of the opening is less than about 20nm, such as less than about 15nm, less than about 10nm, less than about 8nm, less than about 7nm, such as less than about 5 nm. The height H of the plurality of features is equal to or greater than about twice the width W of the plurality of openings 537. The process chamber is maintained at a pressure of less than about 1 mtorr, such as between about 0.5 mtorr and 1 mtorr. In some embodiments, the patterned substrate further comprises a barrier layer (not shown), such as Ta, TaN, It, W, WN, or a combination of the above materials. In those embodiments, the barrier layer is disposed over the plurality of features 535 and serves as a liner in the plurality of openings 537 disposed between the plurality of features 535. In some embodiments, the barrier layer is deposited in the same processing chamber as the subsequently deposited nickel silicide layer, and thus there is no substrate breaking vacuum between depositing the barrier layer and depositing the nickel silicide layer.

At activity 410, the method 400 includes flowing a sputtering gas into the processing chamber, wherein the sputtering gas is an inert gas such as argon, helium, or nitrogen.

At activity 415, the method 400 includes applying rf power to a nickel target and forming a first sputtering plasma adjacent a surface of the nickel target. A surface of the nickel target is disposed in the process chamber at an angle of between about 10 degrees and about 50 degrees relative to a surface of a substrate support, and this is at an angle of between about 10 degrees and about 50 degrees relative to a surface of a substrate disposed on the substrate support. The radio frequency power is between about 100 watts and about 1000 watts. Herein, rf power is coupled to a backing plate having a nickel target disposed thereon. In another embodiment, rf power is coupled to a nickel target.

At activity 420, the method 400 includes applying direct current power to a silicon target and forming a second sputtering plasma adjacent a surface of the silicon target. The silicon target is disposed in the process chamber at an angle of between about 10 degrees and about 50 degrees relative to a surface of the substrate support and a surface of a substrate disposed on the substrate support. The dc power is between about 600 watts and about 1200 watts and is applied to the silicon target simultaneously with applying the rf power to the nickel target. Herein, the dc power is coupled to a backing plate having a silicon target disposed thereon. In another embodiment, a dc power is coupled to the silicon target. The silicon target material comprises amorphous silicon, polycrystalline silicon, crystalline silicon or a combination of the above materials. Herein, the ratio of the radio frequency power and the direct current power is between about 1:1 and about 1: 12.

At activity 425, method 400 includes depositing a uniform nickel silicide layer 539 (Ni) by co-sputtering material from nickel and silicon targets onto a substrate and/or features disposed on the substrate_xSi_1-xWhere x is between 0.01 and 0.99, such as between 0.1 and 0.9). Figure 5B illustrates the deposition of a nickel silicide layer 539 onto a plurality of features 535 disposed on the substrate 228. Figure 5C illustrates a plurality of interconnects 541 formed according to the methods described above, wherein portions of the nickel silicide layer 539 are removed from the surfaces of the plurality of features 535 using a suitable process, such as an etching or chemical mechanical polishing process, to form an electronic device.

The method 400 herein is useful for adjusting the resistivity and composition of the nickel silicide layer by adjusting the rf power, the dc power, and the ratio between the rf power and the dc power, by adjusting the nickel and silicon target angles, and by adjusting the pressure of the process chamber. For example, in one embodiment, method 400 is used to deposit low resistivity Ni_xSi_1-xA layer, wherein x is between about 0.4 and about 0.6, for example wherein x is about 0.5. Low resistivity Ni_xSi_1-xThe layer has a resistivity of less than about 30 μ ohm-cm at a thickness of less than about 20nm and at a full crystalline orientation, such as a resistivity between about 10 μ ohm-cm and about 30 μ ohm-cm. Depositing low resistivity Ni by co-sputtering nickel and silicon in a process chamber having a pressure between about 0.6 mTorr and about 0.7 mTorr_xSi_1-xAnd (3) a layer. The faces of the nickel and silicon targets each have an angle of between about 20 degrees and about 40 degrees relative to the surface of the substrate support and thus from the surface of a substrate disposed on the substrate support. In this embodiment, the ratio of the rf power to the dc power is between about 1:1.6 and about 1:4, wherein the rf power is between about 300 watts and about 500 watts and the dc power is between about 800 watts and about 1200 watts.

In another embodiment, the method 400 is used to deposit medium resistivity Ni_xSi_1-xA layer, wherein x is greater than about 0.6. The medium resistivity layer has a resistivity between about 30 and about 60 μ ohm-cm at a thickness of less than about 20nm, such as a resistivity between about 30 and about 50 μ ohm-cm. Depositing medium resistivity Ni by co-sputtering nickel and silicon in a process chamber having a pressure between about 0.5 mTorr and about 0.8 mTorr_xSi_1-xLayer of nickel and siliconThe targets each have an angle between about 20 degrees and about 30 degrees from a surface of the substrate support and from a surface of a substrate disposed on the substrate support. In this embodiment, the ratio of the radio frequency power to the direct current power is greater than about 1:2.4, such as greater than about 1:1.6, where greater than refers to increased radio frequency power compared to the direct current power. The radio frequency power is greater than about 500 watts, such as between about 500 watts and about 1000 watts, and the direct current power is between about 800 watts and about 1200 watts.

In another embodiment, the method 400 is used to deposit high resistivity Ni_xSi_1-xA layer, wherein x is less than about 0.4, such as less than about 0.33. High resistivity Ni_xSi_1-xThe layer has a resistivity greater than about 60 μ ohm-cm at a thickness less than about 20nm, such as a resistivity between about 60 μ ohm-cm and 200 μ ohm-cm. Depositing high resistivity Ni by co-sputtering nickel and silicon in a process chamber having a pressure between about 0.5 mTorr and about 1 mTorr_xSi_1-xAnd (3) a layer. The nickel and silicon targets each have an angle between about 30 degrees and about 40 degrees from a surface of the substrate support and from a surface of a substrate disposed on the substrate support. In this embodiment, the ratio between the radio frequency power and the direct current power is between about 1:12 and about 1:2. The rf power is between about 100 watts and about 300 watts and the dc power is between about 600 watts and about 1200 watts.

In another embodiment, the method 400 further comprises depositing a TiN passivation layer on the nickel silicide layer, wherein the TiN passivation layer is deposited in the same processing chamber as the nickel silicide layer, and thus there is no substrate break vacuum. By reacting a sputtering gas containing argon with a gas reactive with titanium (such as nitrogen, NH)₄Or a combination of the above) into a process chamber, applying radio frequency power to a titanium target, forming a sputtering plasma of a sputtering gas, and depositing a TiN passivation layer onto the nickel silicide layer to deposit a TiN layer. In another embodiment, the target comprises TiN and the sputtering gas comprises argon, helium, nitrogen, or a combination thereof.

In some embodiments, the silicon nitride layer is annealed at a temperature below about 400 ℃.

The method described above allows for the deposition of a nickel silicide layer with adjustable composition (nickel and silicon concentration), crystal orientation, and resistivity by adjusting the processing parameters of a multi-cathode processing chamber. With adjustable resistivity, nickel silicide layers deposited according to embodiments disclosed herein may be used in applications requiring medium or high resistivity, such as devices requiring embedded resistance (such as sheet or line resistance). Furthermore, a low resistivity nickel silicide layer formed according to embodiments described herein is suitable for use as an interconnect in the less than 20nm regime of eMPF as nickel silicide and thus for the effective resistivity of the interconnect, allowing scaling of line widths and other conductor feature widths to dimensions smaller than currently available from other known materials.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.