Method for fabricating semiconductor structure on semiconductor wafer
阅读说明:本技术 在半导体晶片上制作半导体结构的方法 (Method for fabricating semiconductor structure on semiconductor wafer ) 是由 张峰溢 李甫哲 陈界得 徐庆斌 于 2018-07-10 设计创作,主要内容包括:本发明公开一种在半导体晶片上制作半导体结构的方法。首先提供一半导体晶片,具有一第一区域、一第二区域和一晶边区域。在第一区域和第二区域内分别形成一第一半导体结构和一第二半导体结构。接着对半导体晶片进行一晶边等离子体处理制作工艺,仅仅在晶边区域内形成一阻挡层。再进行一硅化金属制作工艺,在第一区域和第二区域内形成一硅化金属层。(The invention discloses a method for manufacturing a semiconductor structure on a semiconductor wafer. First, a semiconductor chip having a first region, a second region and a chip edge region is provided. A first semiconductor structure and a second semiconductor structure are formed in the first region and the second region, respectively. Then, a wafer edge plasma processing manufacturing process is carried out on the semiconductor wafer, and a barrier layer is formed only in the wafer edge area. And performing a metal silicide manufacturing process to form a metal silicide layer in the first region and the second region.)
1. A method of fabricating a semiconductor structure on a semiconductor wafer, comprising:
providing a semiconductor wafer, wherein the semiconductor wafer is provided with a first area, a second area and a wafer edge area;
forming a first semiconductor structure and a second semiconductor structure in the first region and the second region, respectively;
carrying out a crystal edge plasma processing manufacturing process on the semiconductor wafer, and forming a barrier layer only in the crystal edge region; and
and performing a metal silicide manufacturing process to form metal silicide layers in the first region and the second region.
2. The method of claim 1, wherein the first area is a memory area and the second area is a periphery circuit area.
3. The method of claim 2, wherein the first semiconductor structure comprises a storage node contact structure of a memory cell and the second semiconductor structure comprises a source or drain contact structure of a transistor.
4. The method of claim 2, wherein the barrier layer is a silicon dioxide layer.
5. The method of claim 1, wherein the silicon dioxide layer is formed by oxidizing a silicon surface of the edge region during the edge plasma processing fabrication process.
6. The method of claim 1, wherein during the edge plasma processing, the semiconductor wafer is placed in an edge etcher that is configured with a Plasma Exclusion Zone (PEZ) ring.
7. The method of claim 1, wherein the barrier layer comprises silicon oxynitride, silicon oxycarbide, silicon nitride, or silicon carbide.
8. The method of claim 1, wherein said metal silicide fabrication process comprises:
forming a metal film on the barrier layer in the first region and the second region and the edge region;
performing a thermal process to form the silicide layer only in the first region and the second region; and
removing the unreacted metal film from the barrier layer in the first region, the second region and the edge region.
9. The method of claim 1, wherein the metal silicide layer comprises cobalt silicide or nickel silicide.
10. The method of claim 1, wherein after completing said metal silicide fabrication process to form said metal silicide layer in said first region and said second region, said method further comprises:
depositing a conductive layer only in the first region and the second region; and
patterning the conductive layer to form a storage node pad in the first region and a contact plug and a M in the second region0A metal layer, and a silicon surface is exposed in the edge region.
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure, such as a storage node contact structure and/or a contact plug, on a semiconductor wafer.
Background
In semiconductor fabrication processes, particularly in the former stage, it is often necessary to perform a so-called metal silicide (silicidation) process to reduce contact resistance by forming a metal silicide layer on a silicon surface.
However, in the conventional manufacturing method, a silicide layer is formed on the edge region of the silicon wafer, and the silicide layer formed on the edge region or by-products generated in the subsequent etching process are likely to be peeled off in the reaction chamber of an etching machine (e.g., an etching machine for etching tungsten metal), which causes a contamination problem of the etching machine and affects the reliability or yield of the manufacturing process.
Accordingly, there is still a need in the art for an improved method for overcoming the above-mentioned deficiencies and drawbacks of the prior art.
Disclosure of Invention
The present invention is directed to an improved method for fabricating a semiconductor structure on a semiconductor wafer, which can prevent a silicide layer from being formed on a wafer edge region of the silicon wafer during a silicide fabrication process, thereby solving the problem of contamination of an etching machine and improving the reliability or yield of the fabrication process.
According to one embodiment of the present invention, a method of fabricating a semiconductor structure on a semiconductor substrate is provided. First, a semiconductor chip having a first region, a second region and a chip edge region is provided. A first semiconductor structure and a second semiconductor structure are formed in the first region and the second region, respectively. Then, a wafer edge plasma processing manufacturing process is carried out on the semiconductor wafer, and a barrier layer is formed only in the wafer edge area. And performing a metal silicide manufacturing process to form a metal silicide layer in the first region and the second region. For example, the barrier layer may be a silicon dioxide layer.
The first region may be a memory region, and the second region may be a peripheral circuit region. The first semiconductor structure includes a storage node contact structure of a memory cell, and the second semiconductor structure includes a source or drain contact structure of a transistor.
According to the invention, before the silicide manufacturing process is carried out, the barrier layer is only formed in the edge region BR of the semiconductor wafer by the edge plasma processing manufacturing process, so that a silicide layer is prevented from being formed in the edge region BR in the silicide manufacturing process, therefore, the pollution problem of an etching machine can be solved, and the reliability or yield of the manufacturing process is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. However, the following preferred embodiments and the accompanying drawings are only for reference and illustration purposes and are not intended to limit the present invention.
Drawings
FIG. 1 is a top view of a semiconductor wafer;
FIG. 2 is a schematic cross-sectional view of the semiconductor wafer of FIG. 1;
FIGS. 3-9 are schematic cross-sectional views illustrating a method of fabricating a semiconductor structure on a semiconductor wafer according to one embodiment of the invention;
fig. 10 is a schematic diagram of a wafer edge plasma processing process performed on a semiconductor wafer.
Description of the main elements
10 first semiconductor structure
11 bit line structure
20 second semiconductor structure
21 transistor
100 semiconductor wafer
101 semiconductor substrate
101a silicon surface
102 element isolation region
111 polysilicon layer
112 tungsten metal layer
113 upper cover layer
121 source or drain region
210 gate structure
211 polycrystalline silicon layer
212 tungsten metal layer
213 Top cover layer
214 spacer
215 contact etch stop layer
300 dielectric layer
310 storage node contact hole
311 storage node contact structure
320 source or drain contact structure
410 barrier layer
412 metal film
420 silicide metal layer
426 conductive layer
430 pattern transfer stack layer
431 silicon nitride layer
432 organic dielectric layer
433 silicon-containing hard mask bottom anti-reflective coating layer
440 photoresist pattern
440a opening
500 crystal edge etching machine
510 upper metal piece
510a gas line
511 PEZ Ring
512 upper electrode
520 chip seat
Lower PEZ Ring 521
522 lower electrode
550 reaction chamber
Central region of CR
First region of CR-1
Second region of CR-2
BR crystal edge region
SC storage node pad
CP contact plug
M0Metal layer
Detailed Description
In the following, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the embodiments may be practiced. The following examples are described in sufficient detail to enable those skilled in the art to practice them.
Of course, other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the embodiments described herein. The following detailed description is, therefore, not to be taken in a limiting sense, and the embodiments included therein are defined by the appended claims.
Referring to fig. 1 and fig. 2, fig. 1 is a top view of a semiconductor wafer, and fig. 2 is a cross-sectional view of the semiconductor wafer of fig. 1. As shown in fig. 1 and 2, the
Referring to fig. 3 to 9, cross-sectional views of a method for fabricating a semiconductor structure on a semiconductor wafer according to an embodiment of the invention are shown, wherein the same reference numerals are used for the same regions, elements and material layers. As shown in FIG. 3, a
According to the embodiment of the invention, a plurality of memory cells or a memory cell array can be formed in the memory area, and a transistor structure of a peripheral circuit can be formed in the peripheral circuit area. For simplicity of illustration, only a single memory cell and a single transistor structure are shown.
As shown in fig. 3, a
A storage
According to an embodiment of the present invention, the
Since the
As shown in fig. 4, an edge plasma process is then performed on the
Referring now to FIG. 10, therein is shown a schematic view of a wafer edge plasma processing process performed on a semiconductor wafer. In performing the edge plasma processing process, the
According to the embodiment of the present invention, the
According to the embodiment of the present invention, the wafer edge plasma processing process may utilize oxygen plasma, and the gas supplied through the
As shown in fig. 5 and 6, a metal silicide process is then performed.
First, as shown in FIG. 5, a
Then, as shown in fig. 6, a thermal process, such as a Rapid Thermal Process (RTP), is performed to make the
Next, the
Next, as shown in fig. 7 to 9, after the
As shown in fig. 7, a
As shown in FIG. 8, a
As shown in FIG. 9, an anisotropic dry etching process is then performed to pattern the
In the invention, before the silicide manufacturing process is carried out, the
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.
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