阅读说明：本技术 一种任意脉宽的脉冲调制器 (Pulse modulator with any pulse width ) 是由 何激扬 于 2021-06-21 设计创作，主要内容包括：本发明提供了一种任意脉宽的脉冲调制器,包括同步信号时序生成电路、高边驱动电路、低边驱动电路、供电电源、功率脉冲生成电路、MOSFET高边开关、MOSFET低边开关；供电电源采用BUCK电路模式；BUCK电路的主电路为低边驱动电路供电,BUCK电路的耦合次级为高边驱动电路供电；高边驱动电路供电采用“浮地”连续供电方式,脉冲宽度任意变化,从ns级脉冲宽度直至连续供电；低边驱动电路与高边驱动电路通过BUCK电路的电感加副绕组做为隔离,并形成低边驱动电路先上电、高边驱动电路后上电的上电时序。本发明脉冲调制器实现了在没有电压跌落条件下的任意脉冲宽度调制,且输出电压高、输出电流大、效率高。(The invention provides a pulse modulator with any pulse width, which comprises a synchronous signal time sequence generating circuit, a high-side driving circuit, a low-side driving circuit, a power supply, a power pulse generating circuit, an MOSFET high-side switch and an MOSFET low-side switch, wherein the synchronous signal time sequence generating circuit is connected with the high-side driving circuit; the power supply adopts a BUCK circuit mode; the main circuit of the BUCK circuit supplies power to the low-side drive circuit, and the coupling secondary of the BUCK circuit supplies power to the high-side drive circuit; the high-side driving circuit adopts a 'floating ground' continuous power supply mode for power supply, the pulse width is randomly changed from ns-level pulse width to continuous power supply; the low-side driving circuit and the high-side driving circuit are isolated by the inductance and the auxiliary winding of the BUCK circuit, and a power-on time sequence that the low-side driving circuit is powered on first and the high-side driving circuit is powered on later is formed. The pulse modulator realizes random pulse width modulation under the condition of no voltage drop, and has high output voltage, large output current and high efficiency.)

1. A pulse modulator of arbitrary pulse width, comprising: the synchronous signal timing sequence generating circuit comprises a synchronous signal timing sequence generating circuit, a high-side driving circuit, a low-side driving circuit, a power supply, a power pulse generating circuit, a MOSFET high-side switch and a MOSFET low-side switch;

the synchronous signal time sequence generating circuit is respectively connected with the high-side driving circuit and the low-side driving circuit in series; the high-side driving circuit is connected with the low-side driving circuit in parallel; the high-side driving circuit is connected with the MOSFET high-side switch in series, and the low-side driving circuit is connected with the MOSFET low-side switch in series;

the power supply adopts a mode of a BUCK circuit; the main circuit of the BUCK circuit supplies power to the low-side driving circuit, and the coupling secondary of the BUCK circuit supplies power to the high-side driving circuit;

the high-side driving circuit is powered by a 'floating ground' continuous power supply mode, the pulse width is randomly changed from ns-level pulse width to continuous power supply;

the low-side driving circuit and the high-side driving circuit are isolated by the inductance and the secondary winding of the BUCK circuit, and a power-on time sequence that the low-side driving circuit is powered on first and the high-side driving circuit is powered on later is formed.

2. The pulse modulator according to claim 1, wherein the synchronizing signal timing generating circuit forms a control signal of the high side driving circuit and a control signal of the low side driving circuit, and controls the MOSFET high side switch and the MOSFET low side switch to be turned on and off in a time-sharing manner to output the large-current pulse voltage train.

3. The pulse modulator according to claim 2, wherein the synchronous signal timing generation circuit forms a control signal of the high side driving circuit and a control signal of the low side driving circuit with a phase difference to avoid simultaneous conduction of the MOSFET high side switch and the MOSFET low side switch due to the switching speed of the fet.

4. The pulse modulator according to claim 1, wherein the BUCK circuit switches on and off the voltage applied to the inductor by the input voltage through the PWM signal to convert the high voltage into the low voltage auxiliary power supply, and the output voltage is stabilized through a PWM duty ratio formed by the feedback circuit.

5. The pulse modulator of claim 1, wherein the synchronization signal timing generation circuit comprises a TTL pulse generator.

6. A pulse modulator according to claim 1, characterized in that the output current of the power pulse generating circuit reaches 100A, the rising and falling edge speed of the output current reaches 20 ns.

7. The pulse modulator of claim 1, further comprising an energy storage capacitor.

Technical Field

The invention relates to the technical field of electronic reconnaissance T/R, in particular to a pulse modulator with any pulse width.

Background

In the electronic systems such as radar, electronic countermeasure, communication and the like formed by T/R components, in order to ensure the radio frequency isolation degree of a transmitter and a receiver, a power source pulse modulator of the transmitter is required to be used so as to ensure that the transmitter is completely turned off (powered off) when the system is in a receiving working mode, thereby improving the receiving sensitivity of the receiver.

Taking a radar system as an example, the existing radar system has working modes of a long-distance target and a short-distance target, and has narrow pulses (short-distance targets) such as a fire control radar for identifying enemies and a wide pulse (long-distance target) reconnaissance radar and continuous wave radars such as a Doppler radar and the like. It is desirable that the T/R module power supply be capable of being modulated to any pulse width and be capable of operating in a continuous power mode (pulse width is infinitely long). And a sufficiently large output current is required due to the increase of the radar power.

Currently, the following 3 circuit structures are generally adopted to implement power supply pulse modulation:

1. the pulse output circuit adopts a P-type MOSFET on the high side and an N-type MOSFET on the low side, and the P-type MOSFET is responsible for conduction and N-type discharge. However, the P-type MOSFET has a drawback of large on-resistance. The scheme has the defects of large on-resistance, large voltage drop, low efficiency, high temperature rise and the like, but can realize power supply modulation of any pulse width. This solution has serious technical drawbacks and has been rarely used.

2. The pulse output circuit adopts an N-type MOSFET framework on both the high side and the low side, and the on-resistance of the N-type MOSFET is far lower than that of the P-type MOSFET, so that the defect of an P, N-type structure is avoided, but the high side drive needs to be suspended, and a bootstrap circuit provides a high side drive power supply. There are situations where wide pulse modulation cannot be achieved, and even more so, where continuous wave modes of operation cannot be achieved.

3. Based on the scheme 2, the high side adopts a charge pump mode to supply power, but because the voltage of the charge pump is the voltage doubling characteristic and the output current is very small, high-voltage pulse modulation and large-current pulse modulation cannot be realized.

The above 3 modulation modes all have certain defects and cannot meet the system requirements.

Disclosure of Invention

In view of this, the present invention aims to provide a power supply pulse modulator with a pulse width capable of being set arbitrarily, which is used for a radar pulse feed system to complete pulse modulation of a direct current power supply of a transmitter power amplifier of a radar T/R assembly such as a phased array. The high-side drive feed adopts a micro isolation power supply to replace a bootstrap feed mode, and realizes the pulse modulation of any pulse width large-current power supply from nanosecond narrow pulse to continuous wave.

The invention provides a pulse modulator with any pulse width, comprising: the synchronous signal timing sequence generating circuit comprises a synchronous signal timing sequence generating circuit, a high-side driving circuit, a low-side driving circuit, a power supply, a power pulse generating circuit, a MOSFET high-side switch and a MOSFET low-side switch;

the synchronous signal time sequence generating circuit is respectively connected with the high-side driving circuit and the low-side driving circuit in series; the high-side driving circuit is connected with the low-side driving circuit in parallel; the high-side driving circuit is connected with the MOSFET high-side switch in series, and the low-side driving circuit is connected with the MOSFET low-side switch in series;

the power supply adopts a mode of a BUCK circuit;

the main circuit of the BUCK circuit supplies power to the low-side driving circuit, and the coupling secondary of the BUCK circuit supplies power to the high-side driving circuit;

the high-side driving circuit is powered by a floating ground continuous power supply mode instead of a bootstrap circuit, and the pulse width is randomly changed from ns-level pulse width to continuous power supply.

The low-side driving circuit and the high-side driving circuit are isolated by the inductance and the auxiliary winding of the BUCK circuit, and a power-on time sequence that the low-side driving circuit is powered on first and the high-side driving circuit is powered on later is formed, so that the reliability is improved.

Further, the output current of the power pulse generation circuit reaches 100A.

Further, the rising edge and falling edge speeds of the output current reach 20 ns.

Further, the synchronous signal time sequence generating circuit forms a control signal of the high-side driving circuit and a control signal of the low-side driving circuit, and controls the MOSFET high-side switch and the MOSFET low-side switch to be switched on and off in a time-sharing mode so as to output a large-current pulse voltage string;

specifically, the gate drive circuits of the MOSFET high side switch and the MOSFET low side switch form drive signals of large drive currents.

Furthermore, a control signal of the high-side driving circuit and a control signal of the low-side driving circuit formed by the synchronous signal time sequence generating circuit have phase difference, so that simultaneous conduction of the MOSFET high-side switch and the MOSFET low-side switch caused by switching speed of a field effect tube is avoided;

specifically, the synchronous signal timing generation circuit forms a time difference between a control signal of the high-side driving circuit and a control signal of the low-side driving circuit through the RC delay circuit so as to avoid simultaneous conduction of the MOSFET high-side switch and the MOSFET low-side switch caused by the switching speed of the field effect transistor.

Furthermore, the BUCK circuit controls the on-off of the voltage applied to the inductor by the input voltage through the PWM signal to convert the high voltage into the low-voltage auxiliary power supply, and the output voltage stabilization is realized through the PWM duty ratio formed by the feedback circuit, so that the stable operation of the system is ensured.

Further, the synchronizing signal timing generation circuit includes a TTL pulse generator.

Further, the pulse modulator also comprises an energy storage capacitor.

Compared with the prior art, the invention has the beneficial effects that:

the pulse modulator realizes any pulse width modulation under the condition of no voltage drop, and has high output voltage, large output current and high efficiency; and has great significance for standardization, miniaturization and simplification of system debugging.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.

In the drawings:

FIG. 1 is a schematic circuit diagram of a pulse modulator of any pulse width according to an embodiment of the present invention;

FIG. 2 is a schematic circuit diagram of a high side driver circuit and a low side driver circuit according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of a synchronizing signal timing generation circuit according to an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of the BUCK circuit according to the embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, and third may be used in this disclosure to describe various information, this information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present disclosure. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

An embodiment of the present invention provides a pulse modulator with any pulse width, as shown in fig. 1, including: the synchronous signal timing sequence generating circuit comprises a synchronous signal timing sequence generating circuit, a high-side driving circuit, a low-side driving circuit, a power supply, a power pulse generating circuit, a MOSFET high-side switch and a MOSFET low-side switch;

the synchronous signal time sequence generating circuit is respectively connected with the high-side driving circuit and the low-side driving circuit in series; the high-side driving circuit is connected with the low-side driving circuit in parallel; the high-side driving circuit is connected with the MOSFET high-side switch in series, and the low-side driving circuit is connected with the MOSFET low-side switch in series;

the power supply adopts a mode of a BUCK circuit;

the main circuit of the BUCK circuit supplies power to the low-side driving circuit, and the coupling secondary of the BUCK circuit supplies power to the high-side driving circuit;

the high-side driving circuit is powered by a floating ground continuous power supply mode instead of a bootstrap circuit, and the pulse width is randomly changed from ns-level pulse width to continuous power supply;

in this embodiment, the high-side driving circuit adopts a micro isolation power supply to replace a bootstrap feeding mode, so that any pulse width large-current power supply pulse modulation from ns-level narrow pulses to continuous waves is realized.

The low-side driving circuit and the high-side driving circuit are isolated by the inductance and the auxiliary winding of the BUCK circuit, and a power-on time sequence that the low-side driving circuit is powered on first and the high-side driving circuit is powered on later is formed so as to improve the reliability;

in order to meet the requirement of miniaturization, a power supply of a high-side drive circuit cannot adopt a traditional isolation power supply mode such as single-ended flyback. Therefore, the embodiment adopts a BUCK circuit mode, a coupling secondary winding is added on an inductance magnetic core in the BUCK circuit, an isolated secondary output is formed through diode rectification, and the LDO is used as a secondary voltage stabilizer. The BUCK main circuit is used as a power supply of the low-side driving circuit, the coupling secondary circuit is used as a power supply of the high-side driving circuit, and the topological structure simultaneously realizes a power-on time sequence when the circuit is powered on, namely the low-side driving circuit is powered on (discharged) firstly, and the high-side driving circuit is powered on (output) later, so that the reliability of the circuit is ensured.

The output current of the power pulse generation circuit reaches 100A; the speed of the rising edge and the falling edge of the output current reaches 20 ns;

because of using the high-side N-type MOSFET, the output current can reach 100A, the speed of the rising edge and the falling edge can reach 20ns, the device is completely suitable for short-distance and long-distance target detection, and the mode conversion of the continuous wave radar can be realized by the same device;

in this embodiment, the gate of the MOSFET is driven with a larger current to increase the on and off speed of the MOSFET.

ComputingRequired drive current I of MOSFET_g：

The model of the switch tube is as follows: PSMN8R7-100YSF

The main parameters are as follows: r_DS(25℃)＝7.2mΩ；R_DS(100℃)＝10.7mΩ；C_iss(max)＝2758pF(V_DS＝50V) C_oss(TYP)＝532pF(V_DS＝50V)C_rss(max)＝17pF(V_DS＝50V)R_g＝0.8Ω；

To eliminate Miller oscillation, a gate current limiting resistor R 'is externally connected'_g3.3 omega total grid current limiting resistor R_g4.1 Ω, gate drive current

Rising edge and falling edge time:

the drivers of the high-side driving circuit and the low-side driving circuit adopt UCC27200 and drive current 3A, so that the driving requirements can be met;

the high-side driving circuit and the low-side driving circuit of the present embodiment are shown in fig. 2.

The synchronous signal time sequence generating circuit forms a control signal of the high-side driving circuit and a control signal of the low-side driving circuit, and controls the MOSFET high-side switch and the MOSFET low-side switch to be switched on and switched off in a time-sharing manner so as to output a large-current pulse voltage string;

specifically, the gate drive circuits of the MOSFET high side switch and the MOSFET low side switch form drive signals of large drive currents.

The control signal of the high-side driving circuit and the control signal of the low-side driving circuit formed by the synchronous signal time sequence generating circuit have phase difference, so that the MOSFET high-side switch and the MOSFET low-side switch are prevented from being simultaneously conducted due to the switching speed of a field effect tube;

specifically, the synchronous signal timing sequence generating circuit forms a time difference between a control signal of the high-side driving circuit and a control signal of the low-side driving circuit through an RC delay circuit so as to avoid simultaneous conduction of the MOSFET high-side switch and the MOSFET low-side switch caused by the switching speed of the field effect transistor;

the synchronizing signal timing generating circuit of the present embodiment is shown in fig. 3.

The BUCK circuit controls the on-off of the voltage applied to the inductor by the input voltage through the PWM signal to convert the high voltage into the low-voltage auxiliary power supply, and outputs the regulated voltage through the PWM duty ratio formed by the feedback circuit to ensure the stable operation of the system;

the BUCK circuit of the present embodiment is shown in FIG. 4.

The synchronizing signal timing generation circuit comprises a TTL pulse generator.

The pulse modulator also includes an energy storage capacitor.

Compared with the prior art, the invention has the beneficial effects that:

the pulse modulator realizes any pulse width modulation under the condition of no voltage drop, and has high output voltage, large output current and high efficiency; and has great significance for standardization, miniaturization and simplification of system debugging.

So far, the technical solutions of the present invention have been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the invention, a person skilled in the art can make the same changes or substitutions on the related technical features, and the technical solutions after the changes or substitutions will fall within the protection scope of the invention.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention; various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, substitution and improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.