阅读说明：本技术 超宽带高增益低噪声放大器 (Ultra-wideband high-gain low-noise amplifier ) 是由 李振荣 王思敏 刘博宇 程夏禹 庄奕琪 于 2019-09-30 设计创作，主要内容包括：本发明公开了一种超宽带高增益低噪声放大器,包括输入匹配级、增益放大级和输出匹配级三级级联结构。输入匹配级电路,包括第一晶体管M<Sub>1</Sub>、第一电容C<Sub>1</Sub>、第一负载电阻R<Sub>L1</Sub>、第一补偿电感L<Sub>1</Sub>、第二补偿电感L<Sub>2</Sub>以及源极负反馈电感L<Sub>S</Sub>,构成共栅极结构；增益放大级电路,包括第二晶体管M<Sub>2</Sub>、第三晶体管M<Sub>3</Sub>、第二负载电阻R<Sub>L2</Sub>、第三补偿电感L<Sub>3</Sub>以及第四补偿电感L<Sub>4</Sub>,构成共源共栅结构；输出匹配级电路,由第四晶体管M<Sub>4</Sub>、第三负载电阻R<Sub>L3</Sub>、第五补偿电感L<Sub>5</Sub>以及第二隔直电容C<Sub>2</Sub>,构成共源极结构。本发明在3-11GHz频带范围输入输出匹配性能良好、有平坦且高的增益,可用于无线通信系统前端接收机芯片中。(The invention discloses an ultra-wideband high-gain low-noise amplifier which comprises an input matching stage, a gain amplification stage and an output matching stage, wherein the input matching stage, the gain amplification stage and the output matching stage are in a three-stage cascade structure. An input matching stage circuit including a first transistor M 1 A first capacitor C 1 A first load resistor R L1 A first compensation inductance L 1 A second compensation inductance L 2 And source degeneration inductance L S Forming a common gate structure; a gain amplifier stage circuit including a second transistor M 2 A third transistor M 3 A second load resistor R L2 A third compensation inductance L 3 And a fourth compensation inductance L 4 Forming a cascode structure; an output matching stage circuit composed of a fourth transistor M 4 A third load resistor R L3 The fifth compensation inductance L 5 And a second DC blocking capacitor C 2 And a common source structure is formed. The invention has good input and output matching performance in the frequency band range of 3-11GHz, has flat and high gain, and can be used in a front-end receiver chip of a wireless communication system.)

1. The utility model provides an ultra wide band high gain low noise amplifier, includes the tertiary cascade structure of input matching stage circuit, gain amplifier stage circuit and output matching stage circuit which characterized in that:

the input matching stage circuit comprises a first transistor M₁A first capacitor C₁A first load resistor R_L1A first compensation inductance L₁A second compensation inductance L₂And source degeneration inductance L_S(ii) a First transistor M₁With its gate connected to a first DC bias voltage V_bs1The source electrode of which passes through a first DC blocking capacitor C₁Connecting input signal, and connecting source negative feedback inductor L between source and ground_SThe drains of which are respectively connected with a second compensation inductor L₂And a first load resistor R_L1One terminal of (1), a first load resistance R_L1Is connected with a first compensation inductor L₁One terminal of (1), a first compensation inductance L₁The other end of the grid electrode is connected with a power supply voltage VDD to form a common grid electrode structure;

the gain amplifier stage circuit comprises a second transistor M₂A third transistor M₃A second load resistor R_L2A third compensation inductance L₃And a fourth compensation inductance L₄(ii) a Second transistor M₂The grid of the first compensating inductor is connected with the second compensating inductor L₂Its source is connected to ground and its drain is connected to the third transistor M₃A source electrode of (a); third transistor M₃The grid of the grid is connected with a second DC bias voltage V_bs2The drains of which are respectively connected with a fourth compensation inductor L₄And a second load resistor R_L2One terminal of (1), a second load resistor R_L2Is connected with a third compensation inductor L₃At one end of (1)Three-compensation inductance L₃The other end of the power supply is connected with a power supply voltage VDD to form a cascode structure;

the output matching stage circuit comprises a fourth transistor M₄A third load resistor R_L3The fifth compensation inductance L₅And a second DC blocking capacitor C₂(ii) a Fourth transistor M₄The grid of the first compensation inductor is connected with a fourth compensation inductor L₄The source of the other end of the first resistor is connected to ground, and the drain of the other end of the first resistor is connected to a third load resistor R_L3And a second dc blocking capacitor C₂One end of (C), a second DC blocking capacitor C₂The other end of the third load resistor R is connected with a signal output end_L3Is connected with a fifth compensation inductor L₅One terminal of (1), a fifth compensation inductance L₅The other end of the first switch is connected with a power supply voltage VDD to form a common source structure.

2. The amplifier of claim 1, wherein: first blocking capacitor C₁And a second DC blocking capacitor C₂The DC blocking capacitors are all DC blocking capacitors, the size of each DC blocking capacitor is adjusted and determined around 10pF, and the DC blocking capacitors are used for isolating the influence of DC at the input node and the output node on the circuit.

3. The amplifier of claim 1, wherein: first compensation inductance L₁The size of the second compensation inductor L is adjusted and determined within the range of 600-900 pn₂The size is adjusted and determined within the range of 1.4-1.9 n and is used for offsetting the first transistor M₁The influence of the parasitic capacitance at the output node of the drain electrode on the circuit gain improves the high-frequency gain of the input matching stage circuit.

4. The amplifier of claim 1, wherein: third compensation inductance L₃The size of the fourth compensation inductor L is adjusted and determined within the range of 600-900 pn₄The size is adjusted and determined within the range of 1.4-1.9 n and is used for offsetting the third transistor M₃The influence of the parasitic capacitance at the drain output node on the circuit gain improves the high-frequency gain of the gain amplifier stage circuit.

5. The amplifier of claim 1, wherein: fifth compensation inductance L₅The size is adjusted and determined within the range of 600-900 pn and is used for offsetting the fourth transistor M₄The influence of the parasitic capacitance at the output node of the drain electrode on the output impedance ensures that the output matching stage circuit keeps good output matching performance in a wider frequency band, and simultaneously improves the high-frequency gain of the output matching stage circuit.

6. The amplifier of claim 1, wherein: first transistor M₁A second transistor M₂A third transistor M₃And a fourth transistor M₄Are all N-type metal-oxide-semiconductor field effect transistors.

7. The amplifier of claim 1, wherein: source electrode negative feedback inductance L_SA first transistor M₁The first transistor M is used for providing input impedance₁Transconductance g of_m1The size is adjusted around 20 mS.

8. The amplifier of claim 1, wherein: third load resistor R_L3The fifth compensation inductance L₅A fourth transistor M₄A source-drain resistance and a parasitic capacitance at the output node for providing an output impedance, a third load resistance R_L3Is adjusted to be determined around 50 ohms.

9. The amplifier of claim 1, wherein: each component is realized by adopting a CMOS (complementary metal oxide semiconductor) process with the characteristic size of 55nm, and the power supply voltage VDD is realized by adopting 1.2V.

Technical Field

The invention belongs to the technical field of microelectronic devices, and particularly relates to an ultra-wideband low-noise amplifier which can be used in a front-end receiver chip of a wireless communication system.

Background

The low noise amplifier is a first module at the front end of a receiver in a wireless communication system, and is mainly used for amplifying a weak signal received by an antenna and then transmitting the weak signal to a rear-stage module of the receiver for processing. The performance of the lna has a significant impact on the overall receiver circuit, and therefore the lna should have a low noise figure and good gain. In recent decades, with the rapid development of wireless communication, a low noise amplifier is required to not only consider the amplification processing of signals in an operating frequency band, but also cover a plurality of frequency bands, and meet the requirements of input and output matching, high gain, low noise and the like in an ultra wide band range. With the popularity of mobile electronic devices, low noise amplifiers are also required to have lower power consumption. It is difficult for an ultra-wideband low noise amplifier to meet these performance criteria in the ultra-wideband frequency range.

Referring to fig. 1, a conventional ultra-wideband low noise amplifier includes a three-stage circuit, wherein a first stage circuit adopts a common gate structure and is formed by a first transistor M₁A first inductor L_SAnd a first load resistor R₁Forming; the second stage circuit adopts a cascode structure and is composed of a second transistor M₂A third transistor M₃A second inductor L₁And a second load resistor R₂Forming; the third stage circuit adopts a source follower structure as a buffer stage and is composed of a fourth transistor M₄And a current source I_SAnd (4) forming. At high frequency, the parasitic capacitance at the output node of the circuit cannot be ignored, which can cause the gain of the ultra-wideband low-noise amplifier circuit to be reduced at high frequency, and the gain flatness value of the circuit is increased.Although the source follower structure has good broadband output matching characteristics, the noise is increased, and the front-stage gain is reduced, so that the gain of the ultra-wideband low-noise amplifier circuit in the whole working frequency band is not high.

Disclosure of Invention

The invention aims to provide an ultra-wideband high-gain low-noise amplifier aiming at the defects of the prior art, and the ultra-wideband high-gain low-noise amplifier can improve the circuit gain and reduce the gain flatness value without increasing the power consumption.

In order to achieve the above object, the ultra-wideband low noise amplifier of the present invention includes a three-level cascade structure of an input matching stage circuit, a gain amplifier stage circuit, and an output matching stage circuit, and is characterized in that:

the input matching stage circuit comprises a first transistor M₁A first capacitor C₁A first load resistor R_L1A first compensation inductance L₁A second compensation inductance L₂And source degeneration inductance L_S(ii) a First transistor M₁With its gate connected to a first DC bias voltage V_bs1The source electrode of which passes through a first DC blocking capacitor C₁Connecting input signal, and connecting source negative feedback inductor L between source and ground_SThe drains of which are respectively connected with a second compensation inductor L₂And a first load resistor R_L1One terminal of (1), a first load resistance R_L1Is connected with a first compensation inductor L₁One terminal of (1), a first compensation inductance L₁The other end of the grid electrode is connected with a power supply voltage VDD to form a common grid electrode structure;

the gain amplifier stage circuit comprises a second transistor M₂A third transistor M₃A second load resistor R_L2A third compensation inductance L₃And a fourth compensation inductance L₄(ii) a Second transistor M₂The grid of the first compensating inductor is connected with the second compensating inductor L₂Its source is connected to ground and its drain is connected to the third transistor M₃A source electrode of (a); third transistor M₃The grid of the grid is connected with a second DC bias voltage V_bs2The drains of which are respectively connected with a fourth compensation inductor L₄And a second load resistor R_L2One terminal of (1), a second load resistor R_L2Is connected with a third compensation inductor L₃One terminal of (1), a third compensation inductance L₃The other end of the power supply is connected with a power supply voltage VDD to form a cascode structure;

the output matching stage circuit comprises a fourth transistor M₄A third load resistor R_L3The fifth compensation inductance L₅And a second DC blocking capacitor C₂(ii) a Fourth transistor M₄The grid of the first compensation inductor is connected with a fourth compensation inductor L₄The source of the other end of the first resistor is connected to ground, and the drain of the other end of the first resistor is connected to a third load resistor R_L3And a second dc blocking capacitor C₂One end of (C), a second DC blocking capacitor C₂The other end of the third load resistor R is connected with a signal output end_L3Is connected with a fifth compensation inductor L₅One terminal of (1), a fifth compensation inductance L₅The other end of the first switch is connected with a power supply voltage VDD to form a common source structure.

Compared with the prior art, the invention has the following advantages:

because the inductance compensation technology is adopted in the three-level cascade circuit, the gain reduction caused by the parasitic capacitance at the output node of each level of circuit when the high frequency is compensated is realized, the gain is flattened, and the bandwidth is expanded;

the output matching stage circuit adopts a common source structure, can realize good output matching in a wide frequency band, and simultaneously improves the gain in the whole frequency band.

Drawings

FIG. 1 is a circuit topology structure diagram of a prior art ultra-wideband low noise amplifier;

FIG. 2 is a circuit topology structure diagram of the ultra-wideband low noise amplifier of the present invention;

FIG. 3 is a diagram of input matching simulation results of the present invention;

FIG. 4 is a diagram of the output matching simulation results of the present invention;

FIG. 5 is a graph of power gain simulation results of the present invention;

FIG. 6 is a graph of the simulation results of the noise figure of the present invention.

Detailed Description

The following describes the embodiments of the present invention in further detail with reference to the accompanying drawings.

Referring to fig. 2, the ultra-wideband low noise amplifier of the present embodiment includes a three-stage cascade circuit structure of an input matching stage, a gain amplification stage, and an output matching stage. The input matching stage circuit adopts a common-gate structure and can meet good input impedance matching at high frequency; the gain amplifier stage circuit adopts a cascode structure, has large output impedance and can generate large gain; the output matching stage circuit adopts a common source structure, so that good output impedance matching can be realized in a wide frequency band, and meanwhile, the circuit gain is improved. The circuit signal is input from the input matching stage circuit, amplified through the gain amplifier stage circuit, and finally output from the output matching stage circuit.

The input matching stage circuit comprises a first transistor M₁A first capacitor C₁A first load resistor R_L1A first compensation inductance L₁A second compensation inductance L₂And source degeneration inductance L_S(ii) a First transistor M₁With its gate connected to a first DC bias voltage V_bs1The source electrode of which passes through a first DC blocking capacitor C₁Connected with input signal, and having drain electrodes connected with second compensation inductors L₂And a first load resistor R_L1A source negative feedback inductor L is connected between the source and the ground_SWherein the first DC blocking capacitor C₁The direct current signal at the input end can be isolated, and the influence of the direct current signal at the input end on the ultra-wideband low-noise amplifier circuit is prevented; source electrode negative feedback inductance L_SFor providing an input impedance; a first load resistor R_L1Is connected with a first compensation inductor L₁One terminal of (1), a first compensation inductance L₁The other end of the first compensation inductor L is connected with a power supply voltage VDD to form a common grid structure₁And a second compensation inductance L₂For counteracting the first transistor M₁The influence of the parasitic capacitance at the output node of the drain electrode on the circuit gain improves the high-frequency gain of the input matching stage circuit and expands the gain bandwidth.

The gain amplifier stage circuit comprises a second transistor M₂A third transistor M₃A second load resistor R_L2A third compensation inductance L₃And a fourth compensation inductance L₄(ii) a Second transistor M₂The grid of the first compensating inductor is connected with the second compensating inductor L₂Its source is connected to ground and its drain is connected to the third transistor M₃A source electrode of (a); third transistor M₃The grid of the grid is connected with a second DC bias voltage V_bs2The drains of which are respectively connected with a fourth compensation inductor L₄And a second load resistor R_L2Wherein the third transistor M3 provides good input-output reverse isolation and high gain, the second transistor M2 and the third transistor M3 share current, and power consumption is reduced while providing high gain; a second load resistor R_L2Is connected with a third compensation inductor L₃One terminal of (1), a third compensation inductance L₃The other end of the first compensation inductor is connected with a power supply voltage VDD to form a cascode structure, wherein the third compensation inductor L₃And a fourth compensation inductance L₄For counteracting the third transistor M₃The influence of the parasitic capacitance at the output node of the drain electrode on the circuit gain improves the high-frequency gain of the input matching stage circuit and expands the gain bandwidth.

The output matching stage circuit comprises a fourth transistor M₄A third load resistor R_L3The fifth compensation inductance L₅And a second DC blocking capacitor C₂(ii) a Fourth transistor M₄The grid of the first compensation inductor is connected with a fourth compensation inductor L₄The source of the other end of the first resistor is connected to ground, and the drain of the other end of the first resistor is connected to a third load resistor R_L3And a second dc blocking capacitor C₂One end of (C), a second DC blocking capacitor C₂The other end of the first blocking capacitor C is connected with a signal output end, wherein the second blocking capacitor C₂The direct current signal at the output end can be isolated, and the influence of the direct current signal at the output end on the circuit can be prevented; third load resistor R_L3Is connected with a fifth compensation inductor L₅One terminal of (1), a fifth compensation inductance L₅Is connected with a power supply voltage VDD to form a common source structure, wherein a third load resistor R_L3For providing an output impedance, a fifth compensation inductance L₅For counteracting the fourth transistor M₄The influence of the parasitic capacitance at the output node of the drain electrode on the output impedance is reduced, the absolute value of the imaginary part of the output impedance is reduced, the output matching stage circuit is ensured to keep good output matching performance in a wider frequency band, and meanwhile, the high-frequency gain of the output matching stage circuit is improved.

The working principle of this example is as follows:

the circuit signal passes through the first blocking capacitor C₁Coupled to a first transistor M in the input matching stage circuit₁Source stage through the first transistor M₁Drain, second transistor M in the slave gain amplifier stage circuit₂Gate input through a third transistor M₃Drain electrode, fourth transistor M in slave output amplifier stage circuit₄Gate input, finally through a fourth transistor M₄Drain electrode passing through the second DC blocking capacitor C₂And (6) outputting. Wherein the first blocking capacitor C₁A second DC blocking capacitor C₂Too large or too small values of (c) affect the frequency characteristics of the circuit, and therefore the magnitude thereof is adjusted around 10 pF.

Since the first stage input matching stage circuit is of common gate structure, the first transistor M₁Has a transconductance of g_m1Parasitic capacitance of gate to source is C_gs1Source drain resistance is r_O2The internal resistance of the signal source is R_SThe resistance value is usually 50 ohm, the input impedance Z of the circuit_inComprises the following steps:

where, j is an imaginary unit, and ω is an angular frequency.

At low frequency, the source degeneration inductance L_SThe inductive reactance value is small, at which time the input impedance Z is small_inThe size is mainly determined by a source electrode negative feedback inductor L_SDetermining; with increasing frequency, the source negative feedback inductance L_SThe inductance value gradually increases, the first transistor M₁Transconductance g of_m1>>sC_gs1At this time, the input impedance Z_inIs approximately equal to the first transistor M₁Transconductance g of_m1Reciprocal of (3), input impedance when the input impedance is optimally matchedanti-Z_inIs 50 ohms, i.e. the first transistor M₁Transconductance g of_m1The size can be adjusted around 20 mS.

Considering parasitic capacitance C at output node of input matching stage circuit_L1The influence on the circuit is that the gain of the input matching stage circuit is:

wherein the content of the first and second substances,

Z_out1＝[(1+g_m1r_O1)(R_S||sL_S)+r_O1]||(R_L1+sL₁)，<3>

is composed of<2>It can be seen that the first compensation inductance L₁A second compensation inductance L₂The parasitic capacitance C at the output node of the input matching stage circuit is counteracted_L1The influence on the circuit expands the bandwidth of the circuit and improves the high-frequency gain of the circuit at the same time. Due to the parasitic capacitance C at the output node of the input matching stage circuit_L1The value of (a) is in the range of 20 to 30fF, so that the first compensation inductance L₁The size of the second compensation inductor L is adjusted and determined within the range of 600-900 pn₂The size is adjusted and determined within the range of 1.4-1.9 n.

Because the second-stage gain amplification stage circuit adopts a cascode structure, the second transistor M of the second-stage gain amplification stage circuit₂Has a transconductance of g_m2Source drain resistance is r_O2A third transistor M₃Has a transconductance of g_m3Source drain resistance is r_O3Considering the parasitic capacitance C at the output node of the gain amplifier stage_L2Then, the gain of the stage circuit is:

wherein the content of the first and second substances,

is composed of<4>It can be seen that the third compensation inductance L₃And a fourth compensation inductor L₄Offset byParasitic capacitance C at the output node of the gain amplifier stage circuit_L2The influence on the circuit expands the bandwidth of the circuit and improves the high-frequency gain of the circuit at the same time. Due to parasitic capacitance C at output node of gain amplifier stage circuit_L2The value of (d) is in the range of 20-30 fF, so that the third compensation inductance L₃The size of the fourth compensation inductor L is adjusted and determined within the range of 600-900 pn₄The size is adjusted and determined within the range of 1.4-1.9 n.

Because the third stage output matching stage circuit adopts a common source structure, the fourth transistor M of the third stage output matching stage circuit₄Has a transconductance of g_m4Source drain resistance is r_O4Considering the parasitic capacitance C at the output node of the output matching stage circuit_L2The output impedance Z of the whole circuit_outComprises the following steps:

Z_out＝r_O4||(R_L3+sL₅)||C_L3，<6>

is composed of<6>It can be seen that the fifth compensation inductance L₅The parasitic capacitance C at the output node of the output matching stage circuit is counteracted_L2The influence on the circuit expands the bandwidth of the circuit and improves the high-frequency gain of the circuit at the same time. Due to the parasitic capacitance C at the output node of the output matching stage circuit_L3Is in the range of 20-30 fF, so that the fifth compensation inductance L₅The size is adjusted and determined within the range of 600-900 pn.

According to the fourth transistor M₄Source-drain resistance r_O4Usually large, with a load impedance (R)_L3+sL₅) The impedance obtained after parallel connection is substantially equal to the load impedance (R)_L3+sL₅) The real part of the output impedance is approximately equal to the third load resistance R_L3When the output impedance reaches the best match, the output impedance Z_outIs 50 ohms, the third load resistance R is therefore_L3The value of the third-stage output matching stage circuit can be adjusted and determined around 50 omega, and the gain of the third-stage output matching stage circuit is as follows:

|A₃|＝g_m4Z_out，<7>

due to the output impedance Z_outIs 50 ohm, the fourth transistor M₄Transconductance g of_m4A value of greater than 2The output matching stage has a gain of more than 1 at 0 mS.

The gain of the whole circuit is the superposition of the gains of the three stages of circuits, and finally the overall gain | A | of the circuit is as follows:

|A|＝|A₁|·|A₂|·|A₃|<8>

the effects of the invention can be further illustrated by the following simulations:

1. simulation conditions

In the frequency band range of 3-11GHz, a 55nm CMOS process model is adopted for the circuit shown in the figure 2, and a Cadence simulation tool is used for simulating the circuit under the condition that the power supply voltage VDD is 1.2V.

2. Emulated content

Simulation 1, which simulates the input matching of the circuit of the present invention under the above conditions, shows the result in fig. 3, and it can be seen from fig. 3 that the circuit of the present invention has a good input matching effect.

Simulation 2, which simulates the output matching of the circuit of the present invention under the above conditions, shows the result in fig. 4, and it can be seen from fig. 4 that the circuit of the present invention has a good output matching effect.

Simulation 3, which is to simulate the power gain of the circuit of the present invention under the above conditions, the result is shown in fig. 5, and it can be seen from fig. 5 that the gain of the circuit of the present invention is 18.2 to 19.1dB in the frequency band of 3 to 11GHz, a higher gain can be achieved in the ultra-wideband range, and the gain flatness value is lower.

And 4, simulating the noise of the circuit of the invention under the conditions, wherein the result is shown in fig. 6, and as can be seen from fig. 6, the noise coefficient of the circuit of the invention is 2.9-3.3 dB in a frequency band of 3-11GHz, and the circuit of the invention meets the requirement of low noise in an ultra-wide frequency band.

And simulation 5, wherein the power consumption of the circuit is simulated under the conditions, and the power consumption is only 9.5 mW.

Simulation results show that the invention has advantages over the prior art in input and output matching, gain, noise, power consumption and bandwidth.

While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.