阅读说明：本技术 级联ldo稳压器 (Cascade LDO voltage stabilizer ) 是由 杜定坤 J·B·弗莱彻 于 2018-05-23 设计创作，主要内容包括：公开了一种稳压器。该稳压器为级联的,包括第一级和第二级。第一级可以是包括由第一PMOS晶体管实现的源极跟随器的无电容器的第一级,其中第一PMOS晶体管在其相应栅极端子上接收第一参考电压。第一级被耦接以接收来自外部电压源的第一电压,并向第二级提供第二电压。第二级可直接且唯一地耦接到第一级,其中耦接到第一级输出的一个不具有电容器或连接。第二级可在输出节点上提供输出电压,其中输出电压小于第二电压。(A voltage regulator is disclosed. The voltage regulator is cascaded and comprises a first stage and a second stage. The first stage may be a capacitor-less first stage including a source follower implemented by a first PMOS transistor, wherein the first PMOS transistor receives a first reference voltage on its respective gate terminal. The first stage is coupled to receive a first voltage from an external voltage source and to provide a second voltage to the second stage. The second stage may be directly and exclusively coupled to the first stage, with one coupled to the first stage output having no capacitors or connections. The second stage may provide an output voltage on the output node, where the output voltage is less than the second voltage.)

1. A circuit, comprising:

a voltage regulator, wherein the voltage regulator comprises:

a first stage, wherein the first stage is a capacitor-less first stage and includes a source follower implemented using a first P-type metal oxide semiconductor (PMOS) transistor, wherein a gate terminal of the first PMOS transistor is coupled to receive a first reference voltage, wherein the first stage is coupled to receive a first voltage from an external voltage source and is configured to output a second voltage less than the first voltage on an intermediate node; and

a second stage coupled to receive the second voltage from the first stage, wherein the first stage is configured to provide the second voltage directly and exclusively to the second stage via the intermediate node, wherein the second stage is configured to output a third voltage to a load circuit on an output node.

2. The circuit of claim 1, wherein the first stage further comprises a common-source amplifier implemented using a second PMOS transistor, wherein the first PMOS transistor comprises a load on the common-source amplifier.

3. The circuit of claim 2, further comprising a common-gate amplifier implemented using NMOS transistors coupled to both the first PMOS transistor and the second PMOS transistor, wherein the common-gate amplifier is configured to drive a voltage substantially equal to the second voltage to a gate terminal of the second PMOS transistor.

4. The circuit of claim 2, wherein the second stage comprises an amplifier having an inverting input and a non-inverting input, wherein the non-inverting input of the amplifier is coupled to receive a second reference voltage, and wherein amplifier comprises a supply voltage input coupled to receive the second voltage.

5. The circuit of claim 4, wherein an output of the amplifier is coupled to a gate terminal of an NMOS transistor.

6. The circuit of claim 5, further comprising a current mirror coupled to the drain terminal of the NMOS transistor, the current mirror comprising a third PMOS transistor and a fourth PMOS transistor, wherein respective gate terminals of the third PMOS transistor and the fourth PMOS transistor are coupled to the drain terminal of the NMOS transistor, and wherein a source terminal of the fourth PMOS transistor is coupled to the output node.

7. The circuit of claim 4, further comprising a voltage divider coupled between the output node and a reference node, wherein the amplifier is coupled to receive a divided voltage from the voltage divider on its inverting input.

8. The circuit of claim 1, wherein the first stage comprises a first series regulator, and wherein the second stage comprises a second series regulator.

9. A method, the method comprising:

receiving a first voltage at a first stage of a voltage regulator;

providing a second voltage from the first stage that is less than the first voltage, wherein the first stage is capacitor-less and includes a source follower implemented using a first P-type metal oxide semiconductor (PMOS) transistor and a common source amplifier implemented using a second PMOS transistor;

receiving the second voltage at a second stage of the voltage regulator, wherein the first stage is coupled to provide the second voltage directly and exclusively to the second stage via an intermediate node; and

providing a third voltage on an output node of the second stage of the voltage regulator, the third voltage being less than the second voltage.

10. The method of claim 9, further comprising the source follower acting as a load on the common-source amplifier.

11. The method of claim 9, further comprising a common-gate amplifier coupled to the source follower and the common-source amplifier, wherein common-gate amplifier is implemented using a first NMOS transistor, and wherein the common-gate amplifier is configured to drive a voltage substantially equal to the second voltage to a gate terminal of the second PMOS transistor.

12. The method of claim 11, further comprising:

providing a first reference voltage to a gate terminal of the first PMOS transistor; and

providing a bias voltage to a gate terminal of the first NMOS transistor.

13. The method of claim 12, further comprising:

providing the second voltage to a supply voltage input of an amplifier in the second stage, the amplifier having an inverting input and a non-inverting input;

providing a second reference voltage to the non-inverting input of the amplifier;

the amplifier drives an output voltage onto a gate terminal of a second NMOS transistor.

14. The method of claim 13, further comprising:

the second NMOS transistor provides a current source to a current mirror circuit, the current mirror circuit comprising a third PMOS transistor and a fourth PMOS transistor;

outputting the third voltage on the output node, the output node coupled to a drain terminal of the fourth PMOS transistor; and

providing a divided voltage to the inverting input of the amplifier from a voltage divider coupled to the output node.

15. A voltage regulator, comprising:

a first stage, wherein the first stage comprises a source follower implemented using a first P-type metal-oxide-semiconductor (PMOS) transistor and a common-source amplifier implemented using a second PMOS transistor, wherein the first PMOS transistor and the second PMOS transistor are each coupled to an intermediate node, wherein the first stage is a capacitor-less first stage; and

a second stage, wherein the first stage is configured to provide an intermediate voltage directly and exclusively to the second stage via the intermediate node, wherein the second stage is configured to provide an output voltage to a load circuit on an output node.

16. The voltage regulator of claim 15, wherein the first stage is coupled to receive a supply voltage from a voltage source external to the voltage regulator, wherein the second stage is configured to receive the intermediate voltage at the intermediate node, the intermediate voltage having a value less than the supply voltage, and wherein the second stage is configured to provide the output voltage having a value less than the intermediate voltage.

17. The voltage regulator of claim 15, wherein the first stage further comprises a common-gate amplifier coupled to drive a voltage having substantially the same value as the intermediate voltage to the gate terminal of the second PMOS transistor.

18. The voltage regulator of claim 15, wherein the second stage comprises an operational amplifier having a supply voltage input coupled to receive the intermediate voltage from the intermediate node.

19. The voltage regulator of claim 15, wherein the second stage comprises a current mirror circuit comprising a third PMOS transistor and a fourth PMOS transistor, wherein each of the third PMOS transistor and the fourth PMOS transistor has a respective source terminal coupled to the intermediate node, and wherein a drain terminal of the fourth PMOS transistor is coupled to the output node.

20. The voltage regulator of claim 15, wherein the voltage regulator implements a Low Dropout (LDO) voltage regulator, wherein the first stage comprises a first series regulator and the second stage comprises a second series regulator.

Technical Field

The present disclosure relates to electronic circuits, and more particularly to voltage regulator circuits.

Background

Voltage regulators are commonly used in a variety of circuits to provide a desired voltage to a particular circuit. To this end, a variety of voltage regulator circuits are available to meet various applications. Linear voltage regulators are used in many different applications where the available supply voltage exceeds a suitable value for the circuit to be supplied. Thus, the linear regulator may output a voltage less than the received supply voltage.

Some linear regulators may be implemented in stages. Each stage may facilitate generation of an output voltage based on a provided input voltage (e.g., from an external source). The stages may be coupled to each other with a capacitor coupled to the output of each stage. These capacitors can stabilize the voltage output by each stage. In a voltage regulator implemented on an Integrated Circuit (IC), the output of a given regulator stage may have external connections for coupling to capacitors implemented external to the IC (e.g., on a printed circuit board or PCB).

Disclosure of Invention

A voltage regulator is disclosed. In one embodiment, the voltage regulator is cascaded and includes a first stage and a second stage. The first stage may be a capacitor-less first stage including a source follower implemented by a first P-type metal oxide semiconductor (PMOS) transistor, wherein the first PMOS transistor receives a first reference voltage on its respective gate terminal. The first stage is coupled to receive a first voltage from an external voltage source and to provide a second voltage to the second stage. The second stage may be directly and exclusively coupled to the first stage through an intermediate node through which the second voltage is output, wherein the one coupled to the first stage output has no capacitor or connection. The second stage may provide an output voltage on the output node, where the output voltage is less than the second voltage.

In one embodiment, the first stage includes a common source amplifier implemented using PMOS transistors in addition to PMOS based source followers. The first stage may also include a common-gate amplifier coupled to drive a voltage substantially equal to the second voltage to a gate terminal of a PMOS transistor implementing a common-source amplifier. The common-source amplifier and the source follower are both coupled to an intermediate node.

In various embodiments, the second stage may include an operational amplifier configured to drive the gate of the transistor and a current mirror implemented using PMOS transistors. The current mirror may mirror the current consumed by the transistor coupled to the amplifier output. The second stage may output an output voltage on the output node that is less than the second voltage.

Each stage may help provide a portion of the overall Power Supply Rejection Ratio (PSRR) for the voltage regulator. The first stage may be more loosely regulated than the second stage.

Drawings

The following detailed description makes reference to the accompanying drawings, which are now briefly described.

FIG. 1 is a block diagram of one embodiment of an Integrated Circuit (IC) including a voltage regulator and a functional circuit block.

Fig. 2 is a schematic diagram of one embodiment of a voltage regulator.

FIG. 3 is a flow chart illustrating one embodiment of a method for operating a voltage regulator.

FIG. 4 is a block diagram of one embodiment of an exemplary system.

While the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the scope of the claims to the particular form disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure of the present application as defined by the appended claims.

The present disclosure includes references to "one embodiment," a particular embodiment, "" some embodiments, "" various embodiments, "or" an embodiment. The appearances of the phrases "in one embodiment," "in a particular embodiment," "in some embodiments," "in various embodiments," or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

Within this disclosure, different entities (which may be referred to variously as "units," "circuits," other components, etc.) may be described or claimed as "configured to" perform one or more tasks or operations. This expression-an [ entity ] configured to [ perform one or more tasks ] -is used herein to refer to a structure (i.e., a physical thing, such as an electronic circuit). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even though the structure is not currently being operated on. "an integral distribution circuit configured to distribute integrals to multiple processor cores" is intended to cover, for example, an integrated circuit having circuitry that performs this function during operation, even if the integrated circuit concerned is not currently being used (e.g., a power supply is not connected to it). Thus, an entity described or stated as "configured to" perform a task refers to physical things such as devices, circuits, memories storing executable program instructions, etc. that are used to perform the task. This phrase is not used herein to refer to intangible matter.

The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function, although it may be "configurable" to perform that function after programming.

The expression in the appended claims that an architecture "configured to" perform one or more tasks is expressly intended to refer to that claim elementIs not limited toReference 35 u.s.c. § 112 (f). Thus, no claim in the filed application is intended to be construed as having a device-plus-function element. If the applicant wanted to refer to segment 112(f) during the application process, it would use "for" [ perform function]"means" structures are used to describe claim elements.

As used herein, the term "based on" is used to describe one or more factors that affect the determination. This term does not exclude that there may be additional factors that may influence the determination. That is, the determination may be based on specified factors only or on specified factors and other unspecified factors. Consider the phrase "determine a based on B. This phrase specifies that B is a factor used to determine a or that B affects a determination. This phrase does not exclude that the determination of a may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which a is determined based on B only. As used herein, the phrase "based on" is synonymous with the phrase "based, at least in part, on".

As used herein, the phrase "responsive to" describes one or more factors that trigger an effect. The phrase does not exclude the possibility that other factors may affect or otherwise trigger an effect. That is, the effect may be responsive to only these factors, or may be responsive to specified factors as well as other unspecified factors. Consider the phrase "perform a in response to B. The phrase specifies that B is the factor that triggers the performance of a. The phrase does not exclude that performing a may also be responsive to some other factor, such as C. The phrase is also intended to encompass embodiments in which a is performed only in response to B.

As used herein, the terms "first," "second," and the like, serve as labels for terms following them, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless otherwise specified. For example, in a register file having eight registers, the terms "first register" and "second register" may be used to refer to any two of the eight registers, rather than, for example, only logical registers 0 and 1.

The term "or" as used in the claims is used as an inclusive or, rather than an exclusive or. For example, the phrase "at least one of x, y, or z" means any of x, y, and z, and any combination thereof.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments. However, it will be recognized by one of ordinary skill in the art that aspects of the disclosed embodiments may be practiced without these specific details. In some instances, well-known circuits, structures, signals, computer program instructions, and techniques have not been shown in detail in order not to obscure the disclosed embodiments.

Detailed Description

Turning now to fig. 1, a simplified block diagram of one embodiment of an Integrated Circuit (IC) is shown. It should be noted that this simplified embodiment is shown for illustrative purposes, and is not intended to be limiting. Furthermore, other types of circuits (e.g., power management circuits) may also be implemented on IC 10 and may be coupled to and interact with the circuits/units illustrated herein.

IC 10 in the illustrated embodiment includes a voltage regulator 20 and a functional circuit block 11. The functional circuit block may be one of one or more circuit blocks that perform various functions of the IC 10. In this particular example, functional circuit block 11 is coupled to receive power via voltage regulator 20. Specifically, the supply voltage VLDO is supplied as a supply voltage to the functional circuit block 11, which serves as a load of the voltage regulator 20.

In the illustrated embodiment, voltage regulator 20 receives supply voltage Vext from a source external to IC 10. Embodiments are possible and contemplated in which regulator 20 receives power from another source implemented on IC 10.

As discussed further below, regulator 20 is a two-stage cascaded linear regulator. In addition, regulator 20 in the illustrated embodiment may operate as a series regulator, and more specifically, each stage may function as a series regulator. The first and second stages may also each be responsible for providing a portion of the total Power Supply Rejection Ratio (PSRR) of regulator 20 (e.g., the ability to reject changes in output voltage VLDO). In some embodiments, the first stage of regulator 20 may be loosely regulated (e.g., a loose voltage tolerance), while the second stage may be more tightly regulated (e.g., a tighter voltage tolerance). Furthermore, the first stage may be a capacitor-less first stage, where there is no connection of a capacitor at its output. Typically, in a multi-stage voltage regulator, external connections are provided for coupling to capacitors, where the capacitors are implemented external to the IC (e.g., on a printed circuit board or PCB). However, the first stage of regulator 20 does not include any connection for a capacitor and does not include any other circuitry to provide voltage directly to the second stage. Thus, no additional circuit paths, external pins or other connections are required, as the intermediate node is fully coupled between the first stage and the second stage.

Fig. 2 is a schematic diagram of one embodiment of regulator 20. In the illustrated embodiment, voltage regulator 20 includes two stages as previously described coupled to each other via an intermediate node as labeled in the figures. Regulator 20 in the illustrated embodiment is a Low Dropout (LDO) regulator.

The first stage ("stage 1") of regulator 20 in the illustrated embodiment includes a source follower implemented with PMOS transistor MP1, a common-source amplifier implemented with PMOS transistor MP2, and a common-gate amplifier implemented with NMOS transistor MN 1. The transistor MP1 in the illustrated embodiment is coupled to receive a first reference voltage VRef1 on its gate terminal. Meanwhile, transistor MN1 in the illustrated embodiment is coupled to receive a bias voltage Vb on its gate terminal. The first reference voltage and the bias voltage may each be generated by other voltage generation circuitry (not shown) implemented on IC 10.

In addition to the above, the first stage of regulator 20 includes two bias current sources Ib1 and Ib 2. These current sources may be implemented in any suitable manner.

During operation, MP2 acts as the previously mentioned common source amplifier with MP1 as its load. The gate terminal of MP2 is partially driven by MN1, to which its drain terminal is coupled. More specifically, MP1 and MN1 can effectively transfer the voltage Vdd _ Mid on the intermediate node to the gate terminal of MP 2. MP1 may effectively convert a reference voltage received on its gate terminal (VRef1) to an intermediate voltage Vdd _ Mid, which voltage (or substantially equal value) is driven to the gate terminal of MP 2. Thus, MP1 and MP2 both work in concert to drive Vdd _ Mid at the intermediate node. In addition, the first stage of regulator 20 may operate as a series regulator, allowing for operation of MP 2. This arrangement may allow for high gain in the first stage of regulator 20.

The use of PMOS transistors as shown in the first stage, as opposed to NMOS transistors, may provide significant advantages. For example, the use of PMOS transistors in the source follower and in the common-source amplifier may make it easier to meet voltage headroom requirements (e.g., due to the gate and drain voltages required for PMOS devices). Furthermore, the unique combination of a PMOS-based common-source amplifier and a PMOS-based source follower may allow the circuit to more efficiently regulate the intermediate voltage (e.g., Vdd _ Mid as shown in fig. 2).

The second stage of regulator 20 includes an amplifier a1 that includes a supply voltage input coupled to receive an intermediate voltage Vdd _ Mid from an intermediate node. Amplifier a1 is also coupled to receive a second reference voltage (VRef2, which may be provided from a reference voltage generation circuit not shown here) on its non-inverting input. On its inverting input, a1 is coupled to receive a voltage Vdiv provided by a voltage divider comprising resistors R1 and R2 and configured to divide the output voltage VLDO. Amplifier a1 may drive the gate terminal of MN2 based on the difference between voltages VRef2 and Vdiv. Thus, Vdiv provides feedback to amplifier a1, which may drive its output based on the difference between the desired voltage and the actual voltage.

The output of amplifier a1 is coupled to the gate terminal of NMOS transistor MN 2. The transistor MN2 can consume current by a current mirror implemented with PMOS transistors MP3 and MP 4. Transistor MP3 is diode coupled between the intermediate node and the drain terminal of MN 2. The current is mirrored by MP4 through MP3 and MN2, the source-drain path of which is coupled between the intermediate node and an output node ('Out') at which the output voltage VLDO of regulator 20 is provided. The arrangement of MP4 between the intermediate node and the output node results in a series regulator topology for the second stage of regulator 20.

The output voltage from the regulator 20 may be provided to a load circuit, such as the functional circuit block 11 shown in fig. 1. In fig. 2, the load is represented by a capacitor CL and a current source IL.

As described above, each stage of voltage regulator 20 provides a portion of the overall PSRR. Additional key specifications of regulator 20 may depend primarily on the second stage. These specifications include noise limitation, load regulation and DC accuracy of the output voltage. Generally, for these specifications, the second stage may be adjusted more tightly than the first stage.

FIG. 3 is a flow chart illustrating one embodiment of a method for operating a voltage regulator. Method 300 may be used with an embodiment of voltage regulator 20 as described above. Other embodiments of the voltage regulator may also be capable of performing the method 300 and, thus, may be considered to fall within the scope of the present disclosure.

Method 300 begins by providing a voltage to a first stage of a voltage regulator (block 305). The voltage regulator may be a two-stage LDO regulator, each stage arranged as a series regulator. The voltage may be an externally generated voltage. For example, if the voltage regulator is implemented on an IC, the voltage source may be other circuitry on the same die (e.g., an on-chip power supply) or external to the IC.

The first stage may generate an intermediate voltage using a PMOS based source follower and a PMOS based common-source amplifier implemented therein (block 310). The first stage of the regulator may include an arrangement of PMOS devices as shown in fig. 2 to generate an intermediate voltage at an intermediate node coupled between the two devices (and to the second stage). The intermediate voltage may be less than a voltage provided to the first stage from an external source. Furthermore, the intermediate node may be coupled only between the first stage and the second stage, without connection to the capacitor (internal or external to the circuit) provided by that node.

The second stage may receive the intermediate voltage and generate an output voltage of the regulator circuit (block 315). In one embodiment, the second stage may include a PMOS based current mirror, such as shown in fig. 2. However, other second level embodiments are possible and contemplated. The output voltage provided by the second stage may be less than the intermediate voltage received thereby.

Turning next to fig. 4, a block diagram of one embodiment of a system 150 is shown. In the illustrated embodiment, the system 150 includes at least one instance of the integrated circuit 10 coupled to an external memory 158. The integrated circuit 10 may include a memory controller coupled to an external memory 158. The integrated circuit 10 is coupled to one or more peripherals 154 and an external memory 158. A power supply 156 is also provided that supplies a supply voltage to integrated circuit 10 and one or more supply voltages to memory 158 and/or peripherals 154. In some embodiments, more than one instance of integrated circuit 10 may be included (and more than one external memory 158 may also be included).

Peripheral devices 154 may include any desired circuitry depending on the type of system 150. For example, in one embodiment, system 150 may be a mobile device (e.g., a Personal Digital Assistant (PDA), smartphone, etc.), and peripheral device 154 may include devices for various types of wireless communication, such as WiFi, bluetooth, cellular, global positioning system, etc. Peripheral devices 154 may also include additional storage, including RAM storage, solid state storage, or magnetic disk storage. Peripheral devices 154 may include user interface devices such as a display screen, including a touch display screen or multi-touch display screen, a keyboard or other input device, a microphone, a speaker, and so forth. In other embodiments, the system 150 may be any type of computing system (e.g., desktop personal computer, laptop, workstation, tablet, etc.).

The external memory 158 may include any type of memory. For example, the external memory 158 may be SRAM, Dynamic Ram (DRAM) (such as Synchronous DRAM (SDRAM)), double data rate (DDR, DDR2, DDR3, LPDDR1, LPDDR2, etc.) SDRAM, RAMBUS DRAM, or the like. The external memory 158 may include one or more memory modules, such as single in-line memory modules (SIMMs), dual in-line memory modules (DIMMs), etc., to which the memory device is mounted.

Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.