阅读说明：本技术 切换边界模式交错功率转换器的数字控制 (Digital control of switched boundary mode interleaved power converters ) 是由 S·M·班达拉卡 A·杜梅斯 于 2018-08-07 设计创作，主要内容包括：本发明公开了一种电路布置,信号处理器和交错切换边界模式功率转换的方法。该电路布置包括用于从电源接收输入电压的至少一个输入端；用于向负载提供输出电压的输出端；第一交错电路,该第一交错电路包括第一储能设备和第一可控切换设备；一个或多个辅助交错电路,一个或多个辅助交错电路各自包括辅助储能设备,和辅助可控切换设备；和信号处理器,该信号处理器连接到所述可控切换设备。该信号处理器包括被配置用于第一可控切换设备的循环零电流切换操作的第一切换循环控制器；以及被配置用于辅助可控切换设备的循环零电流切换操作的一个或多个辅助切换循环控制器。该信号处理器被配置为在给定切换循环中控制辅助可控切换设备中的每一个辅助可控切换设备的导通时间段以对应于第一可控切换设备的导通时间段。该信号处理器还被配置为控制第一切换控制器和一个或多个辅助切换控制器的导通时间段之间的相位,使得在给定的切换循环内分布导通时间段以减小输入端处的总电流纹波。(The invention discloses a circuit arrangement, a signal processor and a method of interleaved switched boundary mode power conversion. The circuit arrangement comprises at least one input for receiving an input voltage from a power supply; an output for providing an output voltage to a load; a first interleaving circuit comprising a first energy storage device and a first controllable switching device; one or more auxiliary interleaving circuits, each of the one or more auxiliary interleaving circuits comprising an auxiliary energy storage device, and an auxiliary controllable switching device; and a signal processor connected to the controllable switching device. The signal processor comprises a first switching cycle controller configured for a cyclic zero current switching operation of a first controllable switching device; and one or more auxiliary switching cycle controllers configured to assist in a cyclic zero current switching operation of the controllable switching device. The signal processor is configured to control the conduction period of each of the auxiliary controllable switching devices in a given switching cycle to correspond to the conduction period of the first controllable switching device. The signal processor is further configured to control a phase between the conduction periods of the first switching controller and the one or more auxiliary switching controllers such that the conduction periods are distributed within a given switching cycle to reduce the overall current ripple at the input.)

1. A circuit arrangement for interleaved switched boundary mode power conversion, comprising at least:

an input for receiving an input voltage from a power source;

an output for providing an output voltage to a load;

a first interleaving circuit, the first interleaving circuit comprising:

a first energy storage device; and

a first controllable switching device;

one or more auxiliary interleaving circuits, each of the one or more auxiliary interleaving circuits comprising:

an auxiliary energy storage device; and

an auxiliary controllable switching device;

the circuit arrangement further comprises a signal processor connected to the controllable switching device; the signal processor comprises

A first switching cycle controller configured for a cyclic zero current switching operation of the first controllable switching device; and

one or more auxiliary switching cycle controllers configured for cyclic zero current switching operation of the auxiliary controllable switching device, wherein

The signal processor is configured to control the conduction period of each of the secondary controllable switching devices to correspond to the conduction period of the first controllable switching device in a given switching cycle; and wherein

The signal processor is further configured to control a phase between the conduction periods of the first switching controller and the one or more auxiliary switching controllers such that the conduction periods are distributed within a given switching cycle to reduce the total current ripple at the input.

2. The circuit arrangement according to claim 1, wherein the signal processor is configured during zero-current switching to control the switching device at least one zero-current point of the associated energy storage device.

3. The circuit arrangement according to claim 2, wherein the signal processor is configured to control the switching device from an off-state to an on-state at the at least one zero-current point.

4. The circuit arrangement according to one of the preceding claims, wherein the signal processor is configured to control a phase of at least one of the auxiliary controllable switching devices with respect to the on-period of the first controllable switching device to correspond to

5. The circuit arrangement according to one of the preceding claims, wherein the signal processor is configured to control the on-periods to correspond to each other in each switching cycle.

6. The circuit arrangement according to one of the preceding claims, wherein the signal processor is configured to control the phase between the on-periods of the first switching controller and the one or more auxiliary switching controllers in each switching cycle.

7. Circuit arrangement according to one of the preceding claims, wherein each switching cycle controller is configured for PWM operation of the associated controllable switching device.

8. Circuit arrangement according to one of the preceding claims, wherein the signal processor comprises a delay module configured such that the at least one switching point is delayed by a predetermined delay time.

9. Circuit arrangement according to one of the preceding claims, wherein each interleaving circuit comprises a tank current sensor which is connected with the signal processor to determine at least one zero current point of the associated energy storage device.

10. The circuit arrangement according to one of the preceding claims, wherein the signal processor is configured to determine the on-period of the first controllable switching device in dependence on one or more of an input voltage, an output voltage and a reference output voltage.

11. The circuit arrangement according to one of the preceding claims, wherein the signal processor is configured to determine a switching cycle period of the first interleaving circuit from a previous switching cycle.

12. Circuit arrangement according to one of the preceding claims, wherein

The first switching cycle controller is configured for PWM operation, wherein the first controllable switching device is set to a conducting state at a zero current point of the first energy storage device; and wherein

The one or more auxiliary switching cycle controllers are configured to have

13. Circuit arrangement according to one of the preceding claims, wherein

The first switching cycle controller is configured for PWM operation, wherein the first controllable switching device is set to a conducting state at a zero current point of the first energy storage device; wherein two subsequent zero-current points define a switching cycle period of the first interleaving circuit; and wherein

The signal processor comprises a PWM module configured to trigger an intermediate PWM cycle at an on-state transition of the first controllable switching device and make a phase-state transition at half the switching cycle period of the first interleaving circuit; and wherein

One of the auxiliary switching cycle controllers is configured for PWM operation, wherein an associated controllable switching device is set to an on-state at a phase state transition of the intermediate PWM cycle.

14. The circuit arrangement according to one of the preceding claims, wherein the signal processor is further configured to receive input voltage and output voltage information and to determine the at least one zero current point from the input voltage and output voltage information.

15. The circuit arrangement according to one of the preceding claims, wherein the signal processor further comprises a limiter configured to provide maximum on-time information to the PWM module.

16. Circuit arrangement according to one of the preceding claims, wherein the circuit arrangement is a boost converter.

17. Circuit arrangement according to one of the preceding claims, further comprising a rectifying circuit to correct the AC input voltage.

18. A signal processor for use in a circuit arrangement as claimed in any preceding claim.

19. A method of interleaved switching boundary mode power conversion, the method comprising operation of the circuit arrangement of any of claims 1-17.

20. A machine-readable medium comprising content configured to cause a signal processor to perform the method of claim 19.

Technical Field

The present disclosure relates to power converters, and more particularly, to control of interleaved boundary mode power converters.

Background

Power converters, and in particular switched mode power converters, are used in a variety of applications to provide AC/DC and DC/DC conversion. For example, switched mode power converters (also known as Switched Mode Power Supplies (SMPS)) are widely used in computer and mobile phone power supply units to provide the necessary operating voltage from a typical 120V/240VAC power supply.

Typical items of interest when designing power converters relate to conversion efficiency and cost. It should be apparent that power losses should be minimized to increase the overall efficiency of the converter and also to reduce the generation of heat that may be difficult to dissipate depending on the design and respective application.

It is known to operate a switched mode power converter in boundary conduction mode or short "boundary mode" (BCM). Unlike continuous operation in CCM (continuous conduction mode), in boundary conduction mode it is intended to operate the switches of the power converter when no or no substantial current flows through the switches. This mode of operation reduces switching losses and also allows the use of lower cost components, such as lower cost boost diodes, in a boost switching mode power converter arrangement, since there are no reverse recovery losses. Furthermore, BCM also allows Power Factor Correction (PFC) considering that the input current follows the input voltage waveform.

A side effect of BCM is that the converter inherently uses a variable switching frequency. The frequency depends primarily on the output voltage selected, the instantaneous value of the input voltage, the parameters of the energy storage used (e.g., inductance or capacitance), and the output power delivered to the load. The lowest frequency occurs at the peak of the sinusoidal line voltage.

When higher currents are to be converted, interleaved power converters are used. These types of power converters include multiple stages/circuits that are typically arranged in parallel with each other. In the context of the present invention, the term "interleaved" refers to a plurality of circuits operating out of phase. For example, in an interleaved power converter with two stages, the stages are typically operated 180 degrees out of phase, i.e., half of the switching cycles are out of phase. Interleaved power converters have the advantage of causing less input current variation/ripple and thus less electromagnetic interference problems.

A problem with operating an interleaved power converter in boundary conduction mode is that the switching frequency is high and variable, with frequency variations in each cycle. Even if two adjacent switching cycles do not have the same cycle period T, because the input voltage is varying. Therefore, it is complicated to maintain the above-described phase shift between a plurality of stages.

Disclosure of Invention

Therefore, there is an object to provide an efficient circuit arrangement and method for interleaved switched mode power conversion, which allows operation in boundary conduction mode.

This object is solved by a circuit arrangement, a signal processor and a method for interleaved switched boundary mode power conversion. The dependent claims and the following description contain various embodiments of the invention.

In one aspect, a circuit arrangement for interleaved switched boundary mode power conversion is provided that includes at least an input for receiving an input voltage from a power source, an output for providing an output voltage to a load, a first interleaving circuit, one or more auxiliary interleaving circuits, and a signal processor. According to this aspect, the first interleaving circuit comprises at least a first energy storage device and a first controllable switching device. The one or more auxiliary interleaving circuits each comprise at least an auxiliary energy storage device and an auxiliary controllable switching device. A signal processor connected to the controllable switching devices and comprising at least a first switching cycle controller configured for a cyclic/recurring zero current switching operation of the first controllable switching device; and one or more auxiliary switching cycle controllers configured for cyclic/recurring zero current switching operations of the auxiliary controllable switching device.

The signal processor is configured to control the conduction period of each of the auxiliary controllable switching devices to correspond to the conduction period of the first controllable switching device in a given switching cycle, and to control the phase between the conduction periods of the first switching controller and the one or more auxiliary switching controllers such that the conduction periods are distributed within the given switching cycle to reduce the overall current ripple at the input.

The basic idea of the invention is to allow operating an interleaved switching mode power converter in boundary conduction mode. As the inventors believe, in this particular type of power converter, in addition to maintaining the phase requirements for interleaved operation, zero current switching must also be provided to allow boundary conduction mode operation. In order to meet these requirements with an efficient circuit arrangement, the present invention proposes to control the switching device to operate with a corresponding or "matched" conduction period in a given switching cycle.

Drawings

The above and other objects, features and advantages of the present invention will become apparent from the following discussion of various embodiments. In the drawings, there is shown in the drawings,

fig. 1 shows a schematic block diagram of an embodiment of a circuit arrangement for switching Boundary Conduction Mode (BCM) power conversion;

FIG. 2 illustrates inductor current in an exemplary schematic PWM switching cycle_ILA schematic representation of (a);

FIG. 3 shows the voltage at the AC input V_INInterleaving circuit ILC during the whole cycle of_NA graphical representation of the operation of;

FIG. 4 shows a timing diagram of an interleaved operation of the circuit arrangement of FIG. 1;

FIG. 5 illustrates another embodiment of a circuit arrangement for interleaved switching boundary mode power conversion;

FIG. 6 shows a timing diagram of the operation of the digital signal processor in a phase update mode;

FIG. 7 shows a block diagram of an embodiment of a digital signal processor configured for PWM synchronization mode;

FIG. 8 shows a timing diagram of the embodiment of FIG. 7;

FIG. 9 shows a schematic block diagram of another embodiment of a digital signal processor;

FIG. 10 shows a schematic block diagram of another embodiment of a digital signal processor; and is

Fig. 11 shows a more detailed schematic block diagram of the embodiment of fig. 10.

Detailed Description

The technical features described in the present patent application may be used to construct various embodiments of circuit arrangements and integrated circuit devices. Some embodiments of the invention are discussed to enable those skilled in the art to make and use the invention.

As previously discussed, and in one aspect, a circuit arrangement for interleaved switched boundary mode power conversion is provided that includes at least an input for receiving an input voltage from a power source, an output for providing an output voltage to a load, a first interleaving circuit, one or more auxiliary interleaving circuits, and a signal processor.

According to this aspect, the first interleaving circuit comprises at least a first energy storage device and a first controllable switching device. The one or more auxiliary interleaving circuits each comprise at least an auxiliary energy storage device and an auxiliary controllable switching device. A signal processor connected to the controllable switching devices and comprising at least a first switching cycle controller configured for a cyclic/recurring zero current switching operation of the first controllable switching device; and one or more auxiliary switching cycle controllers configured for cyclic/recurring zero current switching operations of the auxiliary controllable switching device.

The signal processor is configured to control the conduction period of each of the auxiliary controllable switching devices to correspond to the conduction period of the first controllable switching device in a given switching cycle, and to control the phase between the conduction periods of the first switching controller and the one or more auxiliary switching controllers such that the conduction periods are distributed within the given switching cycle to reduce the overall current ripple at the input.

In the context of the present discussion, the term "switched boundary mode power conversion" is understood to be switched mode power conversion in Boundary Conduction Mode (BCM). The respective converter circuit comprises at least an energy storage device and a switching device for temporarily storing input energy and then discharging this energy to the output at a different voltage.

In some embodiments, the value of the energy storage device, such as an inductor, may be selected to be larger than the total resistance in the circuit. The resistance (R) may be in the form of an inductor resistance, a switching device resistance, a filter resistance, a board trace resistance, or the like. In some embodiments, the inductor current follows a path based on the final value of the current during the on-time, such as If ^ e (-t/ζ), where If ═ Vin/R, and ζ ═ L/R. If ζ is large, the inductor current will appear as a straight line. One way to increase the zeta value is to reduce the resistance (R) value by using efficient switches and inductors. During the off time, the load resistance contributes to R, among other resistances. In some embodiments, the value of L may be set by input voltage, load range, and switching frequency limits.

In BCM, a new switching cycle is initiated when the current through the energy storage device is restored to zero (at Continuous Conduction (CCM) and Discontinuous Conduction Mode (DCM) boundaries).

Interleaved power conversion and corresponding interleaved power converter are understood to use a plurality of stages, hereinafter referred to as "interleaving circuits", which operate out of phase. For example, in an interleaved power converter with two interleaved circuits, the circuits typically operate 180 degrees out of phase. In the context of the present invention, an "interleaving circuit" comprises at least an energy storage device and a controllable switching device. Typically, the interleaved circuits are connected in parallel with each other.

In the context of the present invention, an "energy storage device" is understood to be a device for storing electrical energy at least temporarily. For example, the energy storage device may include one or more inductors/inductances and/or one or more capacitors/capacitances.

In the context of the present invention, a "controllable switching device" may be of any suitable type to control the current. The switching devices may include, for example, one or more semiconductor switches, such as bipolar transistors, field effect transistors, MOSFETs, IGBTs, SiC, GAN, and the like.

According to the present aspect, the circuit arrangement comprises a signal processor. In this context, a signal processor is understood to be a device which allows cyclic control of the switching device, for example according to Pulse Width Modulation (PWM), at a frequency in the kHz range. In some examples, the signal processor is configured to control the switches in the PWM at a frequency of approximately 500 kHz. In some implementations, the signal processor is a Digital Signal Processor (DSP), such as a DSP having a PWM unit, an ADC, and the like. The DSP architecture facilitates faster execution of instructions for zero current point detection.

The signal processor according to the present aspect comprises at least a first switching cycle controller and one or more auxiliary switching cycle controllers configured for zero current switching. In this context, "zero current switching" is understood to mean controlling the switching device when no or only a small current, e.g. less than 100 μ Α, flows. As will be apparent, zero current switching specifically involves control from an off state (i.e. a non-conducting state) to an on state (i.e. a conducting state of the switching device when no or only a small current flows) of the switching device, given that the circuit arrangement is configured for boundary conduction mode operation.

In the context of the present description, a "zero current point" of the energy storage device is understood as a point in time at which the energy storage device is fully discharged after a charge/discharge cycle (also referred to herein as a "switching cycle").

The "intermediate cycle" time corresponds to half the switching cycle period and is thus the point in time in each switching cycle that is equally spaced between two subsequent zero current points of the energy storage device.

According to this aspect, the signal processor is configured to control the conduction period of each of the secondary controllable switching devices in a given switching cycle to correspond to the conduction period of the first controllable switching device. Thus, the time periods of the switching cycles during which each of the switching devices is controlled to be conductive are at least substantially matched, i.e. substantially identical. In this context, the term "substantially" is understood to include slight deviations in the on-period of a few nanoseconds. The deviation of the switching time periods of the plurality of interleaved circuits may be in the range of about 100 nanoseconds.

In this context, a "switching cycle" is understood as meaning that the combined time of the respective controllable switching devices is set to be conductive (i.e. in the on-state) and the controllable switching devices are subsequently set to be non-conductive, i.e. in the off-state. In the case of PWM control, the switching cycle corresponds to a PWM cycle time T.

According to this aspect, the signal processor is further configured to control the phase between the conduction periods of the first switching controller and the one or more auxiliary switching controllers such that the conduction periods are distributed within a given switching cycle.

As will be apparent, this will "equalize" the current inputs, reducing the overall current ripple at the inputs and thus reducing the effects of electromagnetic interference.

In some embodiments, the conduction periods are evenly distributed within a given switching cycle, which provides a particularly beneficial reduction in overall current ripple. It should be noted, however, that any distribution of the conduction periods, i.e. avoiding conduction periods with all controllable switching devices at the same time, will reduce the overall current ripple.

In some embodiments, the phase between the on periods is set to correspond to ((N-1))/N x 360, where N is the total number of interleaved circuits and N is the index number of the corresponding auxiliary interleaved circuit. Thus, for a given auxiliary interleaving circuit n, the corresponding phase can be determined as

For example, given a total of N-3 interleaving circuits, the phase of the first auxiliary interleaving circuit, i.e., circuit N-2, is 120 degrees, while the phase of the second auxiliary interleaving circuit (i.e., circuit N-3) is 240 degrees. It should be noted that the term "phase" in this context relates to a delay, compared to time, the controllable switching device of the respective auxiliary interleaving circuit being set to an on-state and the controllable switching device of the first interleaving circuit being set to an on-state. The angular phase is defined within a switching cycle (e.g., in PWM, a PWM cycle having a time T).

Reference will now be made to the drawings, wherein reference numerals will be given to various elements of the embodiments and wherein additional embodiments will be discussed.

Specific references to components, modules, units, devices, sections, portions, process steps, and other elements are not intended to be limiting. Further, it should be understood that when referring to alternative drawings, like parts have the same or similar reference numerals. It should also be noted that the figures are schematic and are intended to provide guidance to the reader in the field, and are not necessarily drawn to scale. Rather, the various drawing scales, aspect ratios, and numbers of components shown in the figures may be intentionally varied to make certain features or relationships easier to understand.

Fig. 1 shows a schematic block diagram of an embodiment of a circuit arrangement for switched Boundary Conduction Mode (BCM) power conversion (i.e., in this embodiment, a switched mode boost converter circuit 1).

The boost converter circuit 1 comprises an input or input stage 2, which is providedIs placed for connection to a typical power supply connection, for example, at 110V, 60Hz or 240V, 50 Hz. A bridge rectifier 3 is provided at the input 2 to obtain a positive half wave. The sound pressure converter circuit 1 further comprises a first interleaving circuit ILC₁And a plurality of auxiliary interleaving circuits ILC₂… to ILC_NConnected in parallel with each other and each comprising an inductor L_NMOSFET switching device S_NAnd a flyback diode D_NEnergy storage device of the type in which the index N refers to the corresponding interleaving circuit ILC₁、ILC₂… to ILC_N. As will be apparent from fig. 1, the boost converter circuit 1 may comprise any number of interleaving circuits ILC greater than one, depending on the respective application, and in particular depending on the total current to be delivered to the load 11. The boost converter circuit 1 further comprises means for operating a MOSFET switching device S₁、S₂、…、S_NGate G of₁、G₂、…、G_NAn output capacitor 7, an output 8 and a digital signal processor (DSP; not shown in fig. 1), as described below.

The general operation of the circuit 1 corresponds to the general operation of a typical boost converter. For clarity, the function of an interleaving circuit ILC is discussed first, followed by the interleaving operation.

When the corresponding MOSFET S_NIn the on state, the pair circuit ILC_NInductor L of_NAnd (6) charging. Once inductor L_NIs charged, MOSFET S_NIt switches to the off state so that the only residual current path passes through the flyback diode D_NAnd a load 11, the load 11 being shown as a resistor in fig. 1. The voltage increases taking into account the increase in current from the inductor 4 and the input terminal 2. When MOSFETS_NIn the off state, during the on state, is stored in the inductor L_NThrough diode D_NIs discharged into the load resistor 11.

In typical BCM operation, when the current i through the inductor 4 is_LNReturning to zero, a new switching period of the PWM is initiated. FIG. 2 shows an exemplary schematic PWM switching cycle of inductor current i_LTo illustrate (a). Rising current slope is typicallyMay correspond to V_INL and the falling current slope may generally correspond to

As can be seen from the bottom of FIG. 2, the PWM control signal is applied to the MOSFET S_N. When the PWM signal is high, the MOSFET S_NIs conductive and the inductor L_NCurrent I in_LNAnd (4) increasing. This period of time is described herein as the ton time. Once the inductor L is reached_NThe PWM signal is controlled low and the MOSFET 5 is set to non-conducting. Current I_LNGradually decreases until the inductor L_NAnd (4) completely discharging. This time period is described herein as the toff time. Both ton and ton are switching cycles T, i.e. in this embodiment, PWM/switching cycles T.

When the inductor L_NWhen fully discharged, i.e., at a time "zero current point" in a PWM cycle, the next PWM cycle begins. The PWM signal is controlled high and MOSFET S accordingly_NIs switched to be conductive.

As previously discussed, consider MOSFET S when no substantial current flows_NFrom the off state to the on state, the BCM avoids switching losses, which is referred to herein as "zero current switching".

FIG. 3 shows the voltage at the AC input V_INInterleaving circuit ILC during the whole cycle of_NIllustration of the operation of (a). As will be apparent from the figure, according to fig. 3 shown as V_PWMOf the inductor L in each half cycle of the input voltage_NIs charged and discharged a plurality of times. Converter circuit 1 and more precisely each interleaving circuit ILC_NOperating at different switching frequencies, which depend mainly on the required output reference voltage V_O,refInput voltage V_INInstantaneous value of (d), inductance value of inductor 4 and delivery to load R _L11, output power.

The operating frequency varies as the input current follows a sinusoidal input voltage waveform, as shown in fig. 3. The lowest frequency occurs at positiveAt the peak of the chordal input, i.e., the line voltage. As will be apparent from fig. 3, and due to I_LIs substantially triangular, so that the average value in each PWM period is equal to the input voltage V_INAnd (4) in proportion. Thus, providing a sine V_INIn the case of (1), the input current I of the circuit_INFollowing V with high accuracy_INAnd a sinusoidal input current is drawn from the power supply. Therefore, operating the converter 1 in BCM is ideal for Power Factor Correction (PFC).

Although fig. 2 and 3 show the interleaving circuit ILC_NBut fig. 4 shows a timing diagram of the interleaved operation of circuit arrangement 1 with an exemplary total number of interleaved circuits N-4. As will be apparent from fig. 4, the interleaving circuit ILC_NI.e. the circuit ILC_NCorresponding MOSFET S_NGate G of_NOut of phase operation to reduce current ripple Δ i at input 2_INThe current ripple is significantly less than Δ i_LI.e. interleaving circuit ILC_NOf an interleaving circuit i_LThe maximum difference/span of.

In the present embodiment, each auxiliary interleave circuit ILC_NWith respect to the first interleaving circuit ILC₁Offset of

Where N is the total number of interleaved circuits and N is the index number of the corresponding auxiliary interleaved circuit. In the example of FIG. 4, ILC₂Showing a phase shift of 90 deg., ILC₃Shows a phase shift of 180 deg., and ILC₄A 270 ° phase shift is shown to evenly "equalize" or distribute the current drawn from input 2 within a given switching cycle T, thereby reducing the effects of electromagnetic interference (EMI) and thus allowing for smaller and more cost-effective EMI filters.

Fig. 5 shows another embodiment of a circuit arrangement 51 for interleaved switching boundary mode power conversion. The circuit arrangement 51 corresponds to the circuit arrangement 1 with the following exceptions. First, the circuit arrangement 51 comprises only the first interleaving circuit ILC₁And a second interleaving circuit ILC₂I.e. a two-stage arrangement. It should be noted that fig. 5 shows only two stages for clarity. Of course, more than two stages are possible in respective alternative embodiments.

Except for the inductor L_NMOSFET switching device S_NAnd a flyback diode D_NIn addition, each interleaving circuit includes a current sensor ZCD_NThe current sensor comprises an inductor L inductively coupled to the corresponding inductor_NAnd associated comparator IZCD_N. Current sensor ZCD_NIs connected to the digital signal processor 52 to allow zero current switching operation. Two further comparators I are provided_CH1And I_CH2To be determined by the corresponding MOSFET S₁And S₂The current of (2). Further comparators 53 and 54 are arranged to determine the input voltage V, respectively_INAnd V_OUT. In this embodiment, the DSP 52 is a dsPIC33EP series type available from Microchip technology, Inc. of Chandler, Arizona, USA.

The digital signal processor 52 may operate in different modes of operation. Hereinafter, an exemplary "phase update mode" is discussed with reference to the timing diagram of fig. 6.

In this embodiment, the digital signal processor 52 determines two MOSFETs S₁And S₂The parameters of PWM operation of (1). The DSP 52 accordingly includes at least two internal PWM drive modules configured to be in a current reset mode.

Specifically, the current sensor ZCD_NProviding a momentary time in each PWM cycle wherein the respective inductor L is traversed_NReaches zero, which acts as a current reset trigger to restart a new PWM cycle in current reset mode operation.

Two desired MOSFETs S₁And S₂According to the current voltage V at the output 8 and the comparator 53_OUTAnd a reference voltage V_O,REFIs determined and the reference voltage is predefined by the manufacturer or user of DSP 52 in the internal memory of DSP 52. V_O,REFCorresponding to the desired voltage at the output terminal 8 to be applied to the load 11. It should be noted that，MOSFET S₁Is set to correspond to the MOSFET S in each PWM cycle₂The on-time of (c).

In addition to the above, the total PWM cycle time T is determined by the aforementioned PWM cycle. While this provides a one-cycle delay in the cycle time T, the resulting error is quite small even in view of the frequency variation of the switching operation, as discussed above with reference to fig. 3. To determine the PWM cycle time T, the DSP 52 is programmed to determine the PWM cycle time T provided to the MOSFET S₁I.e., the PWM signal applied to the first interleaving circuit, is the elapsed time between the last two rising edges of the PWM signal. Alternatively, if the "input capture" pin of the DSP 52 is present with the respective type of DSP 52 used, the PWM cycle may be sampled using the "input capture" pin of the DSP 52.

Referring to the timing diagram of FIG. 6 and as shown, two interleaved circuits and more precisely MOSFETs S₁And S₂Are operated using PWM signals. In FIG. 6, "PWM 1" means applied to MOSFET S₁And "PWM 2" means applied to MOSFET S₂The PWM signal of (1). I is₁And I₂Are respectively flowed through the inductors L₁And L₂The current of (2).

In each PWM switching cycle, both MOSFETs are driven with the same on-time, which allows zero current switching, thereby operating in BCM mode. For full interleave operation, PWM2 is phase shifted by half the PWM cycle, T/2, compared to PWM 1. The phase of the PWM2 is set at the beginning of each switching cycle of the PWM 1. The calibration/updating of the zero-current instant and the cycle time T is done at the end of each cycle, provided that there are any differences in the instants of zero-current instant and phase, which can occur during short transient conditions.

FIG. 6 shows the resulting currents I for multiple inductors₁And I₂. As the inventors have determined, the different inductances between different interleaved circuits have only a negligible effect on timing, so that slight variations in inductance have only a small effect on timing when operating as discussed herein. It should be noted, however, that the current is drawn in a given stageThe power shared is inversely proportional to the value of the stage inductance, such that in some embodiments, the same inductance is used in all of the interleaved circuits.

As previously described with reference to timing diagram 6, the interleaved BCM operation discussed requires setting the phase of the auxiliary interleaving circuit in each PWM cycle, specifically taking into account the switching frequency variation in boundary conduction mode. Considering that some commercially available digital signal processors do not allow for phase updates when operating in the current reset mode, a corresponding further embodiment for the operation of the digital signal processor 52 of fig. 5 is discussed below with reference to the block diagram of fig. 7 and the timing diagram of fig. 8 (also referred to as "PWM sync mode"). The two modes of operation of the digital signal processor 52, namely the operations discussed above with reference to fig. 6 and the operations described below with reference to fig. 7 and 8, may be implemented in software and/or hardware, wherein the software may be included in an internal memory (not shown) of the digital signal processor 52. While the DSP 52 may include software for both modes of operation so that the desired mode may be set during operation, this is of course sufficient depending on the capabilities of the type of DSP used in providing one mode of operation.

It will be apparent from fig. 7 that the current implementation uses two "intermediate" PWM blocks, PWMa and PWMb, to obtain a control for the auxiliary interleaving circuit and MOSFET S₂PWM 2. It should be noted that all PWM modules according to this embodiment operate in a current reset mode.

The PWM1 is generated as previously discussed with reference to FIG. 6, i.e., by ZCD based on a zero current point₁And (4) determining. Comparator circuit CMP based on detected zero current point₁A pulse is generated to start or restart (reset) the PWM cycle of signal PWM 1. Two MOSFETs S are desired corresponding to the aforementioned operation mode₁And S₂Is determined by the present voltage V at the output 8 and the comparator 53_OUTAnd a reference voltage V_REFTo be determined. The total PWM cycle time T is determined by the aforementioned PWM cycle, as discussed. It should be noted that all comparator circuits CMP_NAre peripheral devices to the DSP.

Relative to the generation of PWM2According to zero-current sensor ZCD₂Determined zero current point of determined auxiliary interleaving circuit and comparison circuit CMP₂The corresponding start or restart pulse generated generates an intermediate PWMb signal. The PWMb signal thus initiates a new cycle at the determined zero current point and thus determines the instant of the zero current point. The PWMb signal is provided to a further PWM module for generating PWMa. The PWM module also receives CMP₁The signal and the determined PWM cycle time T. CMP using zero current point corresponding to first interleaving circuit₁The pulse starts or restarts PWMa. PWMa is programmed to have a duty cycle T/2, i.e., half the PWM cycle time of the first interleaving circuit. PWMb is used to cut off PWMa at the zero current point of the auxiliary interleaving circuit as shown in the timing diagram of fig. 8.

The PWMa signal is provided to a fourth PWM module of the DSP 52 to use the falling edge of PWMa to assist the MOSFET S of the interleaving circuit₂The PWM2 is provided to trigger the start or restart of the PWMb cycle. The on-time of PWMb is set to correspond to the on-time of PWMa.

In this embodiment, the comparator CMP₁And CMP₂It also allows the addition of a switch MOSFET S₁And S₂The control delay of (2). Such delays can be used to look at typical parasitic capacitances, particularly for the MOSFET S₁And S₂Taking into account the parasitic capacitance of the MOSFETs in this case₁And S₂Will pass through the MOSFET S₁And S₂The true zero moment of the discharge, inductor may not be ideal for switching. To counteract this loss, a delay may be introduced. The delay time is predefined based on the parasitic capacitance value. Typical delay times are between 100 nanoseconds and 400 nanoseconds. It should be noted that MOSFET S is considered₁And S₂The delay switching point is still considered herein as the zero current point, with a relatively small delay introduced in the switching of (c).

Fig. 9 shows a schematic block diagram of a digital signal processor 92 for a total of N interleaving circuits ILC according to the aforementioned operating mode_NTo operate. Of course, in this case, the digital letterNumber processor 72 includes a corresponding number of PWM drive modules.

Fig. 10 shows another embodiment of the digital signal processor 102 in a schematic block diagram. As can be seen from the figure, the present embodiment uses a voltage V_IN、V_OUTAnd V_REFTo control PWM operation without requiring current measurement. Thus, the current sensor ZCD may be omitted herein_NThereby reducing the cost and size of the overall arrangement.

The use corresponds to V_INAnd V_OUTAnd a predefined reference voltage V, again provided by an internal memory (not shown) of the digital signal processor 102_O,REFThe digital signal processor 102 calculates a zero current point, i.e. a point in time, in each PWM cycle, where the inductor current i_LNRespectively, to zero.

In this embodiment, the signal processor 102 is a dsPIC33EP family type digital signal processor.

Fig. 11 shows a more detailed schematic block diagram of the embodiment of fig. 10.

First (corresponding to V)_IN) And second (corresponding to V)_OUT) The voltage signals are received at and then sampled by respective comparators 54 and 53 (see fig. 5). Obtaining a predefined voltage reference V from a memory 40_O,REF。

The signal processor 102 is configured to operate when the duty cycle of the PWM is below 50% (i.e., when V is_IN>V _OUT2 to V_IN,PEAKTime) samples the voltage signal at T/2. This provides an average value of the period corresponding to the input voltage. Most of the power transfer occurs during this time interval. Since the duty cycle and frequency are low in this case, there is enough time to calculate the next zero current point and switching period.

For the remainder of the input voltage half-wave, the sampling frequency is higher towards the zero current point and there is not enough time to calculate if the sampling is done at T/2. Conversely, for a duty cycle equal to or higher than 50%, the signal processor 9 is configured to sample the voltage signal near the beginning of the cycle (e.g. after a small delay of 100ns for switching the transient to extinction). Since the input voltage is small compared to its peak value, the difference between the value sampled at start-up and T/2 is insignificant.

These two voltage signals are supplied to operational amplifiers 41a, 41b for signal conditioning and then to analog-to-digital (ADC) circuits 42a, 42 b. The two ADC circuits 42a, 42b convert the voltage signals into digital information and into a signal having Vmin: 0V and Vmax: 3.3V 12 bit type.

The signal processor 102 also includes a plurality of modules to PWM the PWM module_NProviding a total PWM cycle time T and an on time ton. As shown in the upper part of fig. 11, the subtraction module 43 and the division module 44 will

To the multiplication module 45. The upper path as shown in fig. 11 is the high frequency execution path used to calculate the PWM period value, operating at a maximum frequency of 500kHz in this embodiment.

In the lower part of FIG. 11, the on-time T of PWM_{Conduction of}From V_OUT(i.e. current output voltage) and a predefined reference voltage V_O,REFAnd (4) calculating. The summing node 46 outputs a current to a voltage V_OUTAnd "set point" V_O,REFA comparison is made. The resulting error signal is provided to a filter/compensator 47 that operates at a relatively low frequency (e.g., 10Hz) to remove the error signal that is typically present at the output voltage V_OUTOf the second harmonic component.

The filtered error signal is provided to a limiter 48. The limiter 48 provides safety, especially in the event of a load-side short circuit. During short-circuiting on the output/load side, the MOSFET S_NTends to increase. The limiter 48 will limit the maximum on-time ton and thus the maximum power fed to the output. Thus, a short circuit condition can be safely handled. If both the input voltage and the on-time are within limits, no over-power condition occurs.

Multiplier 45 receives the correspondingly processed error signal as a turn-on time ton and accordingly will

Is provided to the delay 49 and subsequently to the PWM module PWM1 as a total PWM cycle time T. The phases of the remaining PWM modules are calculated based on the PWM cycle time through the respective phase shift module 54.

Also directly to PWM module PWM_NProviding T conduction. Using T and Tturn-on, each PWM module can apply the appropriate PWM timing settings to the MOSFET S_NOf the corresponding gate G_N. Taking into account that the calculation is based on V_OUTAnd V_INThe zero current point in each PWM cycle is reliably determined.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the present invention is not limited to the disclosed embodiments. For example, it is possible to operate the invention in an embodiment wherein:

using a capacitor as energy storage device instead of or in addition to the inductor 4;

an EMI (electromagnetic interference) filter is included and designed to pass lower frequency components and attenuate higher frequency components;

the filter/compensator 47 is a 2P2Z or PID controller; and/or

Instead of a current sensor ZCD comprising a coupled inductor_NCurrent sensor ZCD_NIncluding CT or hall effect sensors, or sense resistors for inductor current measurement and/or diode current measurement.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor, module or other unit may fulfill the functions of several items recited in the claims.

The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims shall not be construed as limiting the scope.

Appendix

Embodiments of the present disclosure include microcontrollers, systems, integrated circuit devices, and methods for digitally controlling an interleaved boundary pattern. Such PFCs may be implemented by any suitable combination of analog circuitry, digital circuitry, instructions executed by a processor, or a combination thereof. Embodiments of the present disclosure may also be implemented in a power supply or a controller for a power supply.

Fig. 1 is a diagram of an exemplary circuit for implementing staggered boundary mode Power Factor Correction (PFC) control.

Boundary mode PFCs may include variable frequency topologies where the switching frequency varies over an Alternating Current (AC) line cycle. The variable frequency may be due to zero inductor current PWM switching. The frequency may depend primarily on the input voltage, the output load, and the inductor value. Whenever two or more stages of the boost converter in the PFC circuit are interleaved, the input current ripple current may be lowest when the phase difference between the two switching waveforms is 180 degrees. If the phase is not controlled, it may result in a ripple current that is higher than that of a single stage because the respective ripple currents may add up. Thus, embodiments of the present disclosure may achieve zero current switching and phase difference in the switching cycle with variations in input, output, and power component values.

The input current ripple may depend on the relationship between the switching waveforms. Embodiments of the present disclosure may be configured to find a single instantaneous value in each switching cycle, where the inductor current is zero and the phase is also 180 degrees relative to the other switching waveform. To achieve this, the frequency of the two stages may be the same in each switching cycle within an AC line cycle. The switching frequency may depend on the value of the inductor, assuming the design of the two (or more) stages is the same. The value of the inductor may vary and depends on tolerances. However, if a constant on-time is provided to both stages, their period can be fixed independent of the inductor value, ignoring small variations in the input voltage due to phase differences. However, current sharing may be inversely proportional to the value of their inductance value. Thus, embodiments of the present disclosure compare the output voltage to a reference to generate an error. The error is passed through a digital filter to obtain a turn-on time ton, which may depend on the input voltage and the output load value. The filter can provide an appropriate value of on-time to meet the output voltage within tolerance and the input current follows the input voltage for high power factor. To achieve both zero current and phase requirements, the start of a new PWM cycle may be triggered by a signal generated from both the zero current and phase signals. The zero current signal may be generated by a current sensing circuit or calculation, while the phase signal may be generated by a calculation or by a measurement from a previous cycle. One of the several stages becomes the primary stage and only meets the zero current requirement. There may be no condition for selecting the primary level. The remaining stages may generate trigger signals based on the main period and their own zero current signals. Thus, a minimum input ripple current can be achieved with an interleaved converter.

In fig. 1, in an interleaved multi-stage boundary mode PFC, the EMI filter may attenuate high frequency components near the zero crossings of the input voltage waveform. This can lead to a prolonged zero current condition near the zero crossing, resulting in distortion of the current waveform. In the case of a high power factor, the input current waveform may be the same as the waveform of the input voltage. Near zero crossing, the input voltage and input current levels may be very low. The input current level may increase with the input voltage and be highest near the peak of the input voltage.

The PFC may include two or more identical boost converter sections. The boost converter may include an inductor, a switch, and a diode. The boost converter may convert an AC input voltage to a DC output voltage. Boundary mode operation may have the advantage of higher efficiency and power factor. One drawback of this topology is the variation of the switching frequency in the line cycle. The frequency is highest towards the zero crossings of the AC line cycle and the frequency is lowest at the peak.

In one implementation, a new PWM switching cycle may be synchronized with zero inductor current. The zero inductor current transient may be sensed using, for example, a current sensor or a coupled inductor, or determined by calculation. Whenever there are more than one stage, the input current ripple may be a function of the phase difference between the switching waveforms of the different stages. When the phase difference between them is 360/N, the input currents may cancel each other and provide low wave ripple. This affects the size of the input EMI filter. A smaller filter may be sufficient to provide the required attenuation for passing the THD requirements.

As shown in fig. 1, the input to the circuit is, for example, 110V at 60Hz or 230V at 50 Hz. The input voltage may be rectified using a bridge rectifier. Furthermore, the input voltage may then be fed to one of the boosting circuits. Given, for example, N boost stages or converters, each boost stage may be designed to handle P/N of power with sufficient clearance. The input and output capacitors may be common to all of the voltage boosting stages and may be block or distributed.

Fig. 3 illustrates basic input and output waveforms according to an embodiment of the present disclosure.

The dsPIC may be configured to sample the input voltage and the output voltage simultaneously using two ADCs and control the gate waveforms of the switches. The zero switching transient for each stage can be determined by using coupled inductor or inductor current sensing or by appropriate calculations. A comparator within the dsPIC receives the sense signal.

Fig. 9 illustrates an interleaving algorithm running within a dsPIC according to an embodiment of the present disclosure. The dsPIC may use a digital filter and the difference between the reference output voltage and the actual output voltage to calculate the on-time. The bandwidth of the output voltage can be kept low to prevent distortion of the input current. This can result in a constant on-time for a given input voltage and output load over an AC line cycle. The gating pulse of the switch (implemented as, for example, a MOSFET) is "high" during the on time and "low" during the off time. When the inductor current through reaches zero, the Pulse Width Modulation (PWM) cycle can be restarted. The primary stage (PWM 1) restarts the PWM cycle each time the inductor current reaches zero. The only other constraint may be a maximum time period that is activated whenever a zero current signal does not arrive within a given time. For the remaining stages, a phase difference with respect to the main stage of 360/N may be required, except for zero current. This may be achieved by using the T1 time of the main stage and multiplying it by the appropriate phase delay to obtain the individual time periods. The first slave stage requires T1 x 360/N phase delays, while the nth stage would require T1 x (N-1)/N phase delays. The calculation of the delay may be done by the dsPIC to obtain the phase signal. The actual or processing of the zero current and phase signals may be performed by logic gates within the dsPIC or a fault signal and additional PWM signals may be used to truncate a given slave PWM.

Fig. 10 shows a second algorithm in which the signal is computed by the dsPIC during the phase shift period, according to an embodiment of the present disclosure. The dsPIC may calculate the period of the main stage based on the on-time and the input and output voltages. In this approach, there may be no external zero current signal.

Fig. 4 shows an individual gate signal for N-4 in accordance with an embodiment of the present disclosure. Inductor current ripple and input current ripple are also shown. With an appropriate phase difference between the gate signals, the input current ripple is significantly reduced. This, along with zero current switching, allows the PFC to have a small EMI filter and high efficiency, high power factor, operation.