Semiconductor memory device with a plurality of memory cells
阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 长泽和也 石井宪弘 河原清治 于 2019-03-01 设计创作，主要内容包括：实施方式提供一种能够在谋求大容量化的同时谋求修复性的提高的半导体存储装置。实施方式的半导体存储装置具备壳体、第1刚性基板、第2刚性基板、及连接基板。所述第1刚性基板收容于所述壳体,安装有控制器。所述第2刚性基板收容于所述壳体并与所述第1刚性基板至少局部相向,安装有半导体存储部件。所述连接基板具有固定于所述第1刚性基板的表面的第1端部和固定于所述第2刚性基板的表面的第2端部,且至少一部分具有挠性而以弯曲的姿势配置于所述壳体内。(The embodiment provides semiconductor memory device capable of increasing capacity and improving repairability, comprising a case, a 1 st rigid substrate, a 2 nd rigid substrate, and a connection substrate, wherein the 1 st rigid substrate is accommodated in the case, a controller is installed on the 1 st rigid substrate, the 2 nd rigid substrate is accommodated in the case, at least partially faces the 1 st rigid substrate, and a semiconductor memory component is installed on the 2 nd rigid substrate, the connection substrate has a 1 st end fixed on the surface of the 1 st rigid substrate and a 2 nd end fixed on the surface of the 2 nd rigid substrate, and at least part of the connection substrate has flexibility and is arranged in the case in a bending posture.)
A semiconductor memory device of the type 1 or , comprising:
a housing;
a 1 st rigid substrate accommodated in the housing and mounted with a controller;
a 2 nd rigid board which is accommodated in the housing, at least partially faces the 1 st rigid board, and on which a 1 st semiconductor memory device controlled by the controller is mounted; and
and a 1 st connection board having a 1 st end fixed to a surface of the 1 st rigid board and a 2 nd end fixed to a surface of the 2 nd rigid board, wherein at least part is flexible and is disposed in the case in a bent posture.
2. The semiconductor memory device according to claim 1,
a 1 st end portion of the 1 st connection substrate is fixed to the 1 st rigid substrate by a plurality of 1 st solder portions,
the 2 nd end portion of the 1 st connection substrate is fixed to the 2 nd rigid substrate by a plurality of 2 nd solder portions.
3. The semiconductor memory device according to claim 1,
further provided with:
a 3 rd rigid board accommodated in the case, located at side opposite to the 1 st rigid board with respect to the 2 nd rigid board, and mounted with a 2 nd semiconductor memory component controlled by the controller, and
and a 2 nd connection board having a 1 st end fixed to a surface of the 1 st rigid board and a 2 nd end fixed to a surface of the 3 rd rigid board, wherein at least part is flexible and is disposed in the case in a bent posture.
4. The semiconductor memory device according to claim 1,
the 1 st rigid substrate has a 1 st surface facing the 2 nd rigid substrate,
the 1 st end of the 1 st connection substrate is fixed to the 1 st surface of the 1 st rigid substrate.
5. The semiconductor memory device according to claim 4,
the 2 nd rigid substrate has a 2 nd surface facing the 1 st rigid substrate,
the 2 nd end of the 1 st connection substrate is fixed to the 2 nd surface of the 2 nd rigid substrate.
6. The semiconductor memory device according to claim 4,
the connector further includes a support member disposed between the 1 st rigid board and the 2 nd rigid board and contacting a 1 st end portion of the 1 st connection board from an opposite side to the 1 st rigid board.
7. The semiconductor memory device according to claim 1,
the 1 st connection board has a plurality of signal lines and a planar ground layer, and the ground layer is positioned on the outer peripheral side of the 1 st connection board with respect to the plurality of signal lines in a bent posture of the 1 st connection board, and covers at least portions of the plurality of signal lines.
8. The semiconductor memory device according to claim 1,
the 1 st end portion of the 1 st connection substrate is fixed to the 1 st rigid substrate by a plurality of solder balls.
9. The semiconductor memory device according to claim 8,
the 1 st rigid substrate has a plurality of pads to which the plurality of solder balls are connected,
the plurality of pads include a plurality of 1 st pads arranged in a 1 st column and a plurality of 2 nd pads arranged in a 2 nd column farther from an edge of the 1 st rigid substrate than the 1 st column,
the 1 st end portion of the 1 st connection substrate is connected to the 1 st pads and the 2 nd pads via the solder balls.
10. The semiconductor memory device according to claim 9,
the plurality of pads further includes a plurality of 3 rd pads disposed in a 3 rd column further from an edge of the 1 st rigid substrate than the 2 nd column,
the 1 st end portion of the 1 st connection substrate is connected to the 1 st pads, the 2 nd pads, and the 3 rd pads via the solder balls.
11. The semiconductor memory device according to claim 9,
the plurality of 1 st pads include 1 or more 1 st pads larger than each of the plurality of 2 nd pads.
12. The semiconductor memory device according to claim 9,
each of the plurality of 1 st pads is larger than each of the plurality of 2 nd pads.
13. The semiconductor memory device according to claim 9,
the plurality of 2 nd pads are arranged at positions shifted from the plurality of 1 st pads in the direction in which the plurality of 1 st pads are arranged.
14. The semiconductor memory device according to claim 9,
the plurality of 2 nd pads are arranged at positions alternating with the plurality of 1 st pads in the direction in which the plurality of 1 st pads are arranged.
15. The semiconductor memory device according to claim 9,
the 1 st connection substrate has a plurality of pads facing the pads of the 1 st rigid substrate and a light-transmissive insulating member covering the plurality of pads,
each of the plurality of pads of the 1 st connection substrate is smaller than each of the plurality of pads of the 1 st rigid substrate.
16. The semiconductor memory device according to claim 15,
the 1 st land board includes a plurality of signal lines and a planar ground layer, the ground layer being positioned on an outer peripheral side of the 1 st land board with respect to the plurality of signal lines in a bent posture of the 1 st land board and covering at least portions of the plurality of signal lines,
the plurality of pads of the 1 st connection substrate have a plurality of signal pads facing the plurality of 2 nd pads and electrically connected to the plurality of signal lines, and a plurality of ground pads facing the plurality of 1 st pads and electrically connected to the ground layer,
at least 1 signal line included in the plurality of signal lines extends through a position overlapping with 1 ground pad included in the plurality of ground pads in the thickness direction of the 1 st connection substrate.
Technical Field
Embodiments of the present invention relate to a semiconductor memory device.
Background
A semiconductor memory device in which a plurality of substrates are connected by a connector is known.
Disclosure of Invention
Drawings
Fig. 1 is a perspective view showing a semiconductor memory device according to
Fig. 2 is a cross-sectional view of the semiconductor memory device shown in fig. 1 taken along the line F2-F2.
Fig. 3 is a cross-sectional view showing the portion of the semiconductor memory device according to
Fig. 4 is a plan view showing the 1 st rigid substrate, the 2 nd rigid substrate, and the 1 st flexible substrate of
Fig. 5 is a plan view showing a connection portion between the 1 st rigid board and the 2 nd rigid board of
FIG. 6 is a cross-sectional view of the 1 st rigid substrate shown in FIG. 5 taken along line F6-F6.
Fig. 7 is a cross-sectional view showing the 1 st rigid substrate, the 2 nd rigid substrate, and the 1 st flexible substrate of
Fig. 8 is a cross-sectional view showing the 2 nd layer of the 1 st flexible substrate of
Fig. 9 is a cross-sectional view showing the 1 st layer of the 1 st flexible substrate of
Fig. 10 is a cross-sectional view showing the 1 st and 2 nd layers of the 1 st flexible substrate according to
Fig. 11 is a cross-sectional view of the 1 st, 2 nd, and1 st rigid substrates shown in fig. 4, taken along the line F11-F11.
Fig. 12 is a cross-sectional view taken along the line F12-F12 of the portion of the semiconductor memory device shown in fig. 2.
Fig. 13 is an enlarged plan view of a connection portion between the 1 st rigid board and the 2 nd rigid board according to
Fig. 14 is an enlarged plan view of a connection portion between the 1 st rigid board and the 2 nd rigid board according to
Fig. 15 is a cross-sectional view showing the portion of the semiconductor memory device according to
Fig. 16 is a cross-sectional view showing the portion of the semiconductor memory device according to
Fig. 17 is a cross-sectional view showing the 1 st rigid substrate, the 2 nd rigid substrate, and a plurality of flexible substrates according to
Fig. 18 is a perspective view showing the portion configuration of the semiconductor memory device according to embodiment 7.
Fig. 19 is a perspective view showing the portion configuration of the semiconductor memory device according to embodiment 8.
Fig. 20 is a plan view showing the portion configuration of the semiconductor memory device according to embodiment 9.
Fig. 21 is a sectional view showing a semiconductor memory device according to
The embodiment provides semiconductor memory devices capable of increasing capacity and improving repairability.
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