阅读说明：本技术 功率晶体管控制信号门控 (Power transistor control signal control ) 是由 S·夏尔马 T·普尔巴里奇 V·希诺瓦 D·M·金策 于 2019-07-19 设计创作，主要内容包括：本公开涉及功率晶体管控制信号门控。公开了一种半桥电路。所述电路包含根据一或多个控制信号选择性地导电的低侧电源开关和高侧电源开关。所述电路还包含经配置以控制所述低侧电源开关的导电状态的低侧电源开关驱动器和经配置以控制所述高侧电源开关的导电状态的高侧电源开关驱动器。所述电路还包含：控制器,其经配置以产生所述一或多个控制信号；高侧回转检测电路,其经配置以在所述开关节点处的电压增大时防止所述高侧电源开关驱动器致使所述高侧电源开关导电；以及低侧回转检测电路,其经配置以在所述开关节点处的电压减小时防止所述低侧电源开关驱动器致使所述低侧电源开关导电。(The circuit also includes a controller configured to generate the or more control signals, a high-side slew detection circuit configured to prevent the high-side power switch driver from rendering the high-side power switch conductive when a voltage at the switch node increases, and a low-side slew detection circuit configured to prevent the low-side power switch driver from rendering the low-side power switch conductive when a voltage at the switch node decreases.)

1, a half-bridge GaN circuit, comprising:

a switch node;

a low side power switch connected to the switch node and configured to selectively conduct according to or a plurality of control signals;

a high-side power switch connected to the switch node and configured to selectively conduct according to the or more control signals;

a low side power switch driver configured to control a conduction state of the low side power switch based on or more of the control signals;

a high-side power switch driver configured to control a conduction state of the high-side power switch based on or more of the control signals;

a controller configured to generate the or more control signals, and

a high-side slew detection circuit configured to prevent the high-side power switch driver from causing the high-side power switch to conduct when a voltage at the switch node increases,

wherein the high side slew detection circuit comprises:

a capacitor connected to a drain of the high-side power switch and to a sense node;

a clamp circuit connected to the sense node and a source of the high-side power switch and configured to prevent a voltage at the sense node from becoming less than a minimum voltage and becoming greater than a maximum voltage;

a bias circuit connected to the sense node; and

an output circuit having an input terminal connected to the sense node, wherein the output circuit is configured to generate a high-side slew-end signal based on the voltage at the sense node and a voltage at the source of the high-side power switch,

wherein the capacitor and the bias circuit are configured to generate the voltage at the corresponding sense node regardless of whether a voltage difference between a voltage at the drain of the high-side power switch and the voltage at the source of the high-side power switch is reduced, and

wherein the biasing circuit is configured to bias the sensing node to a voltage that causes the output circuit to generate the high-side slew end signal that indicates that the difference between the voltage at the drain of the high-side power switch and the voltage at the source of the high-side power switch is not decreasing.

2. The half-bridge GaN circuit of claim 1, wherein the low side power switch driver is configured to render the low side power switch non-conductive in response to the low side signal from the controller indicating that the low side power switch is non-conductive or the low side slew-end signal indicating the voltage reduction at the switch node.

3. The half-bridge GaN circuit of claim 1 or 2, wherein the low side power switch driver is configured to cause the low side power switch to conduct in response to the low side signal from the controller indicating that the low side power switch is conducting and the low side slew end signal indicating that the voltage at the switch node is not decreasing.

4. The half-bridge GaN circuit of any of claims , wherein the high-side power switch driver is configured to receive a high-side control signal from the controller, receive the high-side slew-end signal from the high-side slew detection circuit, and control the conductive state of the high-side power switch based on both the high-side control signal and the high-side slew-end signal.

5. The half-bridge GaN circuit of any of claims , wherein, in response to a decrease in the difference between the voltage at the drain of the high-side power switch and the voltage at the source of the high-side power switch, the capacitor and the biasing circuit are cooperatively configured to drive the sense node to a voltage that causes the output circuit to generate the high-side slewing end signal indicative of the decrease in the difference between the voltage at the drain of the high-side power switch and the voltage at the source of the high-side power switch.

6. The half-bridge GaN circuit of any of claims , wherein, in response to a decrease in a difference between the voltage at the drain of the low-side power switch and the voltage at the source of the low-side power switch, the capacitor and the biasing circuit are cooperatively configured to drive the sense node to a voltage that causes the output circuit to generate the low-side slewing end signal indicative of the decrease in the difference between the voltage at the drain of the low-side power switch and the voltage at the source of the low-side power switch.

7. The half bridge GaN circuit of any of claims 1 or 2, wherein the output circuit includes a signal path and a second signal path, wherein the path is configured to cause the low side slewing end signal to indicate that the voltage difference is not decreasing and to cause the low side slewing end signal to indicate that the voltage difference is decreasing, wherein the path is configured to cause the low side slewing end signal to indicate that the voltage difference is not decreasing more quickly than the path causes the low side slewing end signal to indicate that the voltage difference is decreasing, wherein the second path is configured to cause the low side slewing end signal to indicate that the voltage difference is decreasing and to cause the low side slewing end signal to indicate that the voltage difference is not decreasing, and wherein the second path is configured to cause the low side slewing end signal to indicate that the voltage difference is not decreasing more quickly than the path causes the low side slewing end signal to indicate that the voltage difference is not decreasing.

8. The half-bridge GaN circuit of any of claims , wherein the capacitor comprises:

a transistor structure, comprising:

a source electrode;

a gate electrode electrically connected to the source electrode;

a drain electrode; and

a field plate electrode is provided on the substrate,

wherein the drain electrode serves as the th plate electrode of the capacitor and the field plate electrode serves as the second plate electrode of the capacitor.

A revolution detecting circuit of kinds, comprising:

a capacitor connected to the th input and to the sensing node;

a clamp circuit connected to the sense node and a second input and configured to prevent a voltage at the sense node from becoming less than a minimum voltage and becoming greater than a maximum voltage;

a bias circuit connected to the sense node and the second input; and

an output circuit having an input terminal connected to the sense node, wherein the output circuit is configured to generate a slew-end signal based on the voltage at the sense node and a voltage at the second input,

wherein the capacitor and the bias circuit are configured to generate the voltage at the corresponding sense node regardless of whether a voltage difference between a voltage at the th input and the voltage at the second input decreases,

wherein the biasing circuit is configured to bias the sense node to a voltage that causes the output circuit to generate a slew end signal that indicates that the difference between the voltage at the th input and the voltage at the second input does not decrease, and

wherein, in response to the difference between the voltage at the th input and the voltage at the second input decreasing, the capacitor and the bias circuit are cooperatively configured to drive the sense node to a voltage that causes the output circuit to generate the slew-end signal indicative of the decrease in the difference between the voltage at the th input and the voltage at the second input.

10. The slew detection circuit of claim 9, wherein the output circuit comprises an th signal path and a second signal path, wherein the th path is configured to cause the slew end signal to indicate that the voltage difference is not decreasing and to cause the slew end signal to indicate that the voltage difference is decreasing, wherein the th path is configured to cause the slew end signal to indicate that the voltage difference is not decreasing more quickly than the th path causes the slew end signal to indicate that the voltage difference is decreasing, wherein the second path is configured to cause the slew end signal to indicate that the voltage difference is decreasing and to cause the slew end signal to indicate that the voltage difference is not decreasing, and wherein the second path is configured to cause the slew end signal to indicate that the voltage difference is decreasing more quickly than the th path causes the slew end signal to indicate that the voltage difference is not decreasing.

11. The slew detection circuit of claim 9 or 10 where the capacitor comprises:

a transistor structure, comprising:

a source electrode;

a gate electrode electrically connected to the source electrode;

a drain electrode; and

a field plate electrode is provided on the substrate,

wherein the drain electrode serves as the th plate electrode of the capacitor and the field plate electrode serves as the second plate electrode of the capacitor.

12, a half-bridge GaN circuit, comprising:

a switch node;

a low side power switch connected to the switch node and configured to selectively conduct according to or a plurality of control signals;

a high-side power switch connected to the switch node and configured to selectively conduct according to the or more control signals;

a low side power switch driver configured to control a conduction state of the low side power switch based on or more of the control signals;

a high-side power switch driver configured to control a conduction state of the high-side power switch based on or more of the control signals;

a controller configured to generate the or more control signals, and

a low side slew detection circuit configured to prevent the low side power switch driver from causing the low side power switch to conduct when a voltage at the switch node decreases,

wherein the low side slew detection circuit comprises:

a capacitor connected to a drain of the low side power switch and a sense node;

a clamp circuit connected to the sense node and a source of the low side power switch and configured to prevent a voltage at the sense node from becoming less than a minimum voltage and becoming greater than a maximum voltage;

a bias circuit connected to the sense node; and

an output circuit having an input terminal connected to the sense node, wherein the output circuit is configured to generate a low side slew end signal based on the voltage at the sense node and a voltage at the source of the low side power switch,

wherein the capacitor and the bias circuit are configured to generate the voltage at the corresponding sense node regardless of whether a voltage difference between a voltage at the drain of the low side power switch and the voltage at the source of the low side power switch is reduced, and

wherein the biasing circuit is configured to bias the sensing node to a voltage that causes the output circuit to generate the low side slew end signal indicating that the difference between the voltage at the drain of the low side power switch and the voltage at the source of the low side power switch is not decreasing.

13. The half-bridge GaN circuit of claim 12, wherein the low side power switch driver is configured to receive a low side control signal from the controller, receive a low side slew end signal from the low side slew detection circuit, and control the conduction state of the low side power switch based on both the low side control signal and the low side slew end signal.

Technical Field

The present disclosure relates generally to power conversion circuits, and in particular to power conversion circuits utilizing or multiple GaN-based semiconductor devices.

Background

Electronic devices such as computers, servers, and televisions use or more power conversion circuits to convert forms of electrical energy to another forms of electrical energy some power conversion circuits convert high DC voltages to lower DC voltages using a circuit topology known as half-bridge converters.

Disclosure of Invention

inventive aspects are half-bridge GaN circuits including a switch node, a low-side power switch connected to the switch node and configured to selectively conduct according to or more control signals, a high-side power switch connected to the switch node and configured to selectively conduct according to the or more control signals, and a low-side power switch driver configured to control a conduction state of the low-side power switch based on or more of the control signals, the circuit also including a high-side power switch driver configured to control a conduction state of the high-side power switch based on or more of the control signals, a controller configured to generate the or more control signals, a high-side slew detection circuit configured to prevent the high-side power switch driver from causing the high-side power switch to conduct when a voltage at the switch node increases, and a low-side slew detection circuit configured to prevent the low-side power switch driver from causing the low-side power switch to conduct when a voltage at the switch node decreases.

In embodiments, the low side power switch driver is configured to receive a low side control signal from the controller, receive a low side slew end signal from the low side slew detection circuit, and control a conduction state of the low side power switch based on both the low side control signal and the low side slew end signal.

In embodiments, the low side power switch driver is configured to render the low side power switch non-conductive in response to the low side signal from the controller indicating that the low side power switch is non-conductive or the low side slew-end signal indicating a decrease in voltage at the switch node.

In embodiments, the low side power switch driver is configured to cause the low side power switch to conduct in response to the low side signal from the controller indicating that the low side power switch conducts or the low side slew terminal signal indicating a decrease in voltage at the switch node.

In embodiments, the low side power switch driver is configured to cause the low side power switch to conduct in response to a low side signal from the controller indicating that the low side power switch conducts for a duration greater than a delay threshold.

In embodiments, the high-side power switch driver is configured to receive a high-side control signal from the controller, receive a high-side slew-end signal from the high-side slew detection circuit, and control a conduction state of the high-side power switch based on both the high-side control signal and the high-side slew-end signal.

In embodiments, the high-side power switch driver is configured to render the high-side power switch non-conductive in response to the high-side signal from the controller indicating that the high-side power switch is non-conductive or the high-side slew-end signal indicating an increase in voltage at the switch node.

In embodiments, the high-side power switch driver is configured to cause the high-side power switch to conduct in response to both the high-side signal from the controller indicating that the high-side power switch conducts and the high-side slew-end signal indicating that the voltage at the switch node does not increase.

In embodiments, the high-side power switch driver is configured to cause the high-side power switch to conduct in response to a high-side signal from the controller indicating the high-side power switch to conduct for a duration greater than a delay threshold.

In embodiments, a high-side slew detection circuit includes a capacitor connected to a drain of a high-side power switch and to a sense node, a bias circuit connected to the sense node, and an output circuit having an input terminal connected to the sense node, wherein the output circuit is configured to generate a slew-end signal based on a voltage at the sense node relative to a voltage at a source of the high-side power switch, and wherein the capacitor and the bias circuit are configured to generate a voltage at the corresponding sense node regardless of whether a voltage difference between the voltage at the drain of the high-side power switch and the voltage at the source of the high-side power switch decreases.

In embodiments, the bias circuit is configured to bias the sensing node to a voltage that causes the output circuit to generate a slew-end signal indicating that the difference between the voltage at the drain of the high-side power switch and the voltage at the source of the high-side power switch is not decreasing.

In embodiments, in response to a decrease in the difference between the voltage at the drain of the high-side power switch and the voltage at the source of the high-side power switch, the capacitor and the bias circuit are cooperatively configured to drive the sense node to a voltage that causes the output circuit to generate a slew-end signal that indicates a decrease in the difference between the voltage at the drain of the high-side power switch and the voltage at the source of the high-side power switch.

In embodiments, the output circuit includes a signal path and a second signal path, wherein the path is configured to cause the slew-end signal to indicate that the voltage difference is not decreasing relatively quickly and to cause the slew-end signal to indicate that the voltage difference is decreasing relatively slowly, and wherein the second path is configured to cause the slew-end signal to indicate that the voltage difference is decreasing relatively quickly and to cause the slew-end signal to indicate that the voltage difference is not decreasing relatively slowly.

In some embodiments, the capacitor includes a transistor structure including a source electrode, a gate electrode electrically connected to the source electrode, a drain electrode, and a field plate electrode, wherein the drain electrode serves as the th plate electrode of the capacitor and the field plate electrode serves as the second plate electrode of the capacitor.

In embodiments, the low side slew detection circuit includes a capacitor connected to the drain of the low side power switch and to a sense node, a bias circuit connected to the sense node, and an output circuit having an input terminal connected to the sense node, additionally, the output circuit is configured to generate a slew end signal based on a voltage at the sense node relative to a voltage at the source of the low side power switch, wherein the capacitor and the bias circuit are configured to generate a voltage at the corresponding sense node regardless of whether a voltage difference between the voltage at the drain of the low side power switch and the voltage at the source of the low side power switch decreases.

In embodiments, the bias circuit is configured to bias the sense node to a voltage that causes the output circuit to generate a slew end signal that indicates that the difference between the voltage at the drain of the low side power switch and the voltage at the source of the low side power switch is not decreasing.

In embodiments, in response to a reduction in a difference between the voltage at the drain of the low side power switch and the voltage at the source of the low side, the capacitor and the biasing circuit are cooperatively configured to drive the sense node to a voltage that causes the output circuit to generate a slew end signal indicative of a reduction in a difference between the voltage at the drain of the low side power switch and the voltage at the source of the low side power switch.

In embodiments, the output circuit includes a signal path and a second signal path, the path being configured to cause the slew end signal to indicate that the voltage difference is not decreasing and to cause the slew end signal to indicate that the voltage difference is decreasing relatively slowly, and the second path being configured to cause the slew end signal to indicate that the voltage difference is decreasing relatively quickly and to cause the slew end signal to indicate that the voltage difference is not decreasing relatively slowly.

In some embodiments, the capacitor includes a transistor structure including a source electrode, a gate electrode electrically connected to the source electrode, a drain electrode, and a field plate electrode, wherein the drain electrode serves as the th plate electrode of the capacitor and the field plate electrode serves as the second plate electrode of the capacitor.

Another inventive aspect is slew detection circuits including a capacitor connected to a th input and a sense node, a bias circuit connected to the sense node, and an output circuit having an input terminal connected to the sense node, wherein the output circuit is configured to generate a slew end signal based on a voltage at the sense node relative to a voltage at a second input, and wherein the capacitor and the bias circuit are configured to generate a voltage at the corresponding sense node regardless of whether a voltage difference between the voltage at the th input and the voltage at the second input decreases.

In embodiments, the bias circuit is configured to bias the sense node to a voltage that causes the output circuit to generate a slew end signal that indicates that the difference between the voltage at the th input and the voltage at the second input is not decreasing.

In embodiments, in response to a decrease in the difference between the voltage at the th input and the voltage at the second input, the capacitor and the bias circuit are cooperatively configured to drive the sense node to a voltage that causes the output circuit to generate a slew-end signal indicative of a decrease in the difference between the voltage at the th input and the voltage at the second input.

In embodiments, the output circuit includes a signal path and a second signal path, wherein the path is configured to cause the slew-end signal to indicate that the voltage difference is not decreasing relatively quickly and to cause the slew-end signal to indicate that the voltage difference is decreasing relatively slowly, and wherein the second path is configured to cause the slew-end signal to indicate that the voltage difference is decreasing relatively quickly and to cause the slew-end signal to indicate that the voltage difference is not decreasing relatively slowly.

In some embodiments, the capacitor includes a transistor structure including a source electrode, a gate electrode electrically connected to the source electrode, a drain electrode, and a field plate electrode, wherein the drain electrode serves as the th plate electrode of the capacitor and the field plate electrode serves as the second plate electrode of the capacitor.

Drawings

Fig. 1 is a simplified schematic diagram of a half-bridge power conversion circuit according to an embodiment of the present invention;

FIG. 2 is a simplified schematic diagram of circuitry within the low side control circuit illustrated in FIG. 1;

FIG. 3 is a schematic diagram of the th level-shifting transistor illustrated in FIG. 1;

FIG. 4 is a schematic diagram of the level shifting driver circuit illustrated in FIG. 1;

FIG. 5 is a schematic diagram of the pedestal generator circuit illustrated in FIG. 1;

FIG. 6 is an example of waveforms within the pedestal generator illustrated in FIG. 5;

FIG. 7 is a schematic diagram of the bootstrap transistor drive circuit illustrated in FIG. 1;

FIG. 8 is a block diagram of the low side transistor drive circuit illustrated in FIG. 1;

FIG. 9 is a schematic diagram of the startup circuit illustrated in FIG. 1;

FIG. 10 is an series diode-connected GaN-based enhancement mode transistor that may be used as the diode clamp in the schematic of FIG. 9;

FIG. 11 is a schematic diagram of the UVLO circuit illustrated in FIG. 1;

FIG. 12 is a schematic diagram of the bootstrap capacitor charging circuit illustrated in FIG. 1;

FIG. 13 is a schematic diagram of an alternative bootstrap capacitor charging circuit compared to the circuit illustrated in FIG. 12;

FIG. 14 is a schematic diagram of the high side logic and control circuit illustrated in FIG. 1;

FIG. 15 is a schematic diagram of the level shifting receive circuit illustrated in FIG. 14;

FIG. 16 is a schematic diagram of the second level shifting receive circuit illustrated in FIG. 14;

FIG. 17 is a schematic diagram of the pull-up trigger circuit illustrated in FIG. 14;

FIG. 18 is a schematic diagram of the high side UVLO circuit illustrated in FIG. 14;

FIG. 19 is a schematic diagram of the high-side transistor driver circuit illustrated in FIG. 14;

FIG. 20 is a schematic diagram of the high-side reference voltage generation circuit illustrated in FIG. 14;

fig. 21 is a simplified schematic diagram of a half-bridge power conversion circuit according to another embodiment of the invention;

FIG. 22 is a simplified schematic diagram of circuitry within the low side control circuit illustrated in FIG. 21;

FIG. 23 is a schematic diagram of the level-shifting transistor illustrated in FIG. 22;

FIG. 24 is a schematic diagram of the inverter/buffer circuit illustrated in FIG. 22;

FIG. 25 is a schematic diagram of the turn-on pulse generator illustrated in FIG. 22;

FIG. 26 is a schematic diagram of the shut down pulse generator circuit illustrated in FIG. 22;

FIG. 27 is a schematic diagram of the pedestal generator circuit illustrated in FIG. 22;

fig. 28 is a schematic diagram of the low side transistor drive circuit illustrated in fig. 22;

FIG. 29 is a simplified schematic diagram of circuitry within the high side control circuit illustrated in FIG. 21;

FIG. 30 is a schematic diagram of the level shifted 1 receiver circuit illustrated in FIG. 29;

FIG. 31 is a schematic diagram of the level shifted 2 receiver circuit illustrated in FIG. 29;

FIG. 32 is a schematic diagram of the high side UVLO circuit illustrated in FIG. 29;

FIG. 33 is a schematic diagram of the high-side transistor driver circuit illustrated in FIG. 29;

FIG. 34 is a schematic diagram of an electrostatic discharge (ESD) clamp circuit according to an embodiment of the present invention;

FIG. 35 is a schematic diagram of an electrostatic discharge (ESD) clamp circuit according to an embodiment of the present invention;

fig. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention;

fig. 37 is a diagram of the electronic package of fig. 36;

fig. 38 is a schematic illustration of an alternative embodiment of a half-bridge power conversion circuit.

Fig. 39 is a waveform diagram illustrating -like operation of the circuit.

Fig. 40 is a schematic illustration of an embodiment of a driver circuit.

Fig. 41 is a schematic illustration of an embodiment of a slew detection circuit.

Fig. 42A is a schematic illustration of a clamp circuit.

Fig. 42B is a schematic illustration of the clamp circuit.

Fig. 43 is a schematic illustration of a bias circuit.

Fig. 44 is a schematic illustration of an output circuit.

Fig. 45 is a schematic illustration of an output circuit.

Fig. 46 is a schematic illustration of a pull-up circuit.

Fig. 47 is a cross-sectional view of the semiconductor device.

Detailed Description

Although the present invention is applicable to a wide variety of half-bridge circuits , some embodiments of the present invention are particularly applicable to half-bridge circuits designed to operate at high frequency and/or high efficiency with integrated driver circuits, integrated level-shifting circuits, integrated bootstrap capacitor charging circuits, integrated start-up circuits, and/or hybrid solutions using GaN and silicon devices, as described in more detail below.

Half bridge circuit No. 1

Referring now to fig. 1, in embodiments, the circuit 100 may include pairs of complementary power transistors (also referred to herein as switches) controlled by or more control circuits configured to regulate power delivered to a load in embodiments, a high-side power transistor is disposed on a high-side device along with a portion of the control circuits and a low-side power transistor is disposed on a low-side device along with a portion of the control circuits, as described in more detail below.

The integrated half-bridge power conversion circuit 100 illustrated in fig. 1 includes a low-side GaN device 103, a high-side GaN device 105, a load 107, a bootstrap capacitor 110, and other circuit elements, as illustrated and discussed in more detail below some embodiments may also have an external controller (not shown in fig. 1) that provides or multiple inputs to the circuit 100 to regulate operation of the circuit, the circuit 100 is for illustrative purposes only, and other variations and configurations are within the scope of the present disclosure.

In embodiments, the low-side GaN device 103 can have a GaN-based low-side circuit 104 including a low-side power transistor 115 with a low-side control gate 117. the low-side circuit 104 can further include an integrated low-side transistor driver 120 with an output 123 connected to the low-side transistor control gate 117. in another embodiment, the high-side GaN device 105 can have a GaN-based high-side circuit 106 including a high-side power transistor 125 with a high-side control gate 127. the high-side circuit 106 can further include an integrated high-side transistor driver 130 with an output 133 connected to the high-side transistor control gate 127.

A voltage source 135 (also referred to as a rail voltage) may be connected to a drain 137 of the high-side transistor 125, and the high-side transistor may be used to control power input into the power conversion circuit 100. the high-side transistor 125 may further have a source 140 coupled to a drain 143 of the low-side transistor 115, forming a switch node 145. the low-side transistor 115 may have a source 147 connected to ground.

In embodiments, high-side device 105 and low-side device 103 may be made of GaN-based materials.in embodiments, the GaN-based materials may include layers of GaN on layers of silicon.in further embodiments, the GaN-based materials may include, but are not limited to, layers of GaN on layers of silicon carbide, sapphire, or aluminum nitride.in embodiments, the GaN-based layers may include, but are not limited to, composite stacks of other group III nitrides, such as aluminum nitride and indium nitride, and group III nitride alloys, such as AlGaN and InGaN.in further embodiments, GaN-based low-side circuit 104 and GaN-based high-side circuit 106 may be disposed on a monolithic GaN-based device.in other embodiments, GaN-based low-side circuit 104 and GaN-based high-side circuit 106 may be disposed on a GaN-based device, and GaN-based high-side circuit 106 may be disposed on a second GaN-based device.in yet further embodiments, GaN-based low-side circuit 104 and GaN-based high-side circuit 106 may be disposed on more than two GaN-based devices.in embodiments, and any number of the GaN-based high-side circuit 104 and the GaN-based passive-circuit-containing elements.

Low side device

In embodiments, the low side device 103 may include logic, control, and level shifting circuits (low side control circuits) 150 that control switching of the low side transistor 115 and the high side transistor 125, along with other functions, as discussed in more detail below, the low side device 103 may also include a startup circuit 155, a bootstrap capacitor charging circuit 157, and a shield capacitor 160, as also discussed in more detail below.

Referring now to fig. 2, the circuitry within the low side control circuit 150 is functionally illustrated each of the circuits within the low side control circuit 150 are discussed below and shown in more detail in fig. 3-14 under conditions in embodiments, the primary function of the low side control circuit 150 may be to receive , e.g., PWM signals, or the like, or a plurality of input signals from the controller and control the operation of the low side transistor 115 and the high side transistor 125.

In embodiments, the level-shifting transistor 203 and the second level-shifting transistor 205, respectively, may be used to communicate with the high-side logic and control circuit 153 (see FIG. 1). in embodiments, the level-shifting transistor 203 may be a high-voltage enhancement mode GaN transistor in further embodiments, the level-shifting transistor 203 may be similar to the low-side transistor 115 (see FIG. 1) and the high-side transistor 125, but may be much smaller in size (e.g., the level-shifting transistor may have a gate width of tens of microns with a minimum channel length).

In other embodiments, the th level-shift transistor 203 may experience both high voltage and high current (i.e., the device may operate at a high power portion of the device safe operating area) as long as the high-side transistor 125 (see FIG. 1) is on such conditions may cause relatively high power dissipation, so embodiments may relate to design and device reliability considerations in the design of the th level-shift transistor 203, as discussed in more detail below.

In embodiments, the level-shifting transistor 203 may comprise the 0 portion of an inverter circuit having an th input and a th output, and configured to receive the th input logic signal at the rd input terminal and in response provide the th inverted output logic signal at the th output terminal, as discussed in more detail below, in further embodiments the th input and th inverted output logic signals may reference different voltage potentials. 9 embodiments the th level-shifting resistor 207 may be capable of operating with the th inverted output logic signal that references a voltage that is 13 volts higher than the reference voltage of the th input logic signal.

For example, in embodiments, the source 210 of the level-shift transistor 203 may be connected to a gate-to-source short-circuited depletion device in another embodiment, a depletion device may be fabricated by replacing the enhancement-mode gate stack with a high-voltage field plate metal stacked on top of a field dielectric layer.

In other embodiments, the level shifting resistor 207 may be replaced with a current sink the current sink may use a reference current (Iref) that may be generated by the startup circuit 155 (illustrated in FIG. 1 and discussed in more detail below). both the depletion mode transistor and current sink embodiments may result in a significant reduction in device area compared to the resistor embodiments (i.e., because a relatively small depletion mode transistor will suffice and Iref is already available from the startup circuit 155).

The second level-shifting transistor 205 may be designed similar to the level-shifting transistor 203 (e.g., in terms of voltage capability, current handling capability, thermal endurance, etc.). similar to the level-shifting transistor 203, the second level-shifting transistor 205 may also have an active current sink or resistor built in.

In embodiments, for example, when the turning off of the low-side transistor 115 produces a load current flowing through the high-side transistor 125 while the transistor is operating in the third quadrant and its gate is shorted to its source (i.e., in synchronous rectification mode), a false trigger may occur in boost operation this condition may introduce a dv/dt condition at the switch node (Vsw)145 because the switch node is at a voltage near ground when the low-side transistor 115 is turned on and then transitions to the rail voltage 135 in a relatively short period of time the resulting parasitic C dv/dt current (i.e., where the Coss of the level-shifting transistor 203 plus any other capacitance to ground) may cause the level-shifting node 305 (see fig. 3) to be pulled low, which will then turn on the high-side transistor 125. in embodiments, this condition may not be desirable because there may be no dead-time control and breakdown may occur from the high-side transistor 125 and the low-side transistor 115 being in a conductive state at the same time.

FIG. 3 illustrates embodiments showing how the th level-shifting transistor 203 may be electrically coupled to the high-side device 105. the th level-shifting transistor 203 is illustrated on the low-side device 103, along with a pull-up resistor 303 that may be on the high-side device 105 (see FIG. 1.) in embodiments, the th level-shifting transistor 203 may be used as a pull-down transistor in a resistor pull-up inverter.

In a further embodiment, when the level-shifting driver circuit 217 (see FIG. 2) supplies the th level-shifting transistor 203 with a high gate signal (L1_ DR), the th level-shifting node 305 is pulled low, which is inverted by the high-side logic and control circuit 153 (see FIG. 1). the inverted signal appears as a high-state signal that turns on the high-side transistor 137 (see FIG. 1), which then pulls the voltage at the switch node (Vsw)145 close to the rail voltage 135.

Conversely, when the level-shift driver circuit 217 (see FIG. 2) supplies a low gate signal to the level-shift transistor 203, the level-shift node 305 is pulled to a high logic state, which is inverted by the high-side logic and control circuit 153 (see FIG. 1). the inverted signal appears as a low logic state signal that turns off the high-side transistor 125.

In some embodiments , pull-up resistor 303 may alternatively be an enhancement transistor, a depletion transistor, or a reference current source element in further embodiments, pull-up resistor 303 may be coupled between the drain and positive terminals of a floating supply (e.g., a bootstrap capacitor discussed in more detail below) that references a voltage rail different from ground in yet further embodiments, there may be a th capacitance between th output terminal (LS _ NODE)305 and the switch NODE (Vsw)145 (see fig. 1), and a second capacitance between th output terminal and ground in which the th capacitance is greater than the second capacitance in yet further embodiments th capacitance may be designed such that, in response to a high dv/dt signal at switch NODE (Vsw)145 (see fig. 1), a majority of the C dv/dt current is allowed to conduct through 4 th capacitance to ensure that the voltage at the voltage tracking switch NODE (Vsw) 305, in some embodiments , shielding capacitor 160 may be implemented between the switch NODE (Vsw) 305 and the switch NODE (Vsw) to minimize the voltage at switch NODE (Vsw) 305, particularly, the shield capacitor 160. the shield capacitor 160 may be implemented between the switch NODE (Vsw) and the switch NODE (Vsw) to minimize the voltage generated in embodiments, and the switch NODE (Vsw) may be further embodiments, and be implemented to be further embodiments, e.160. the shield capacitor 160. the shield capacitor may be implemented to be further embodiments, e.160 to be coupled between the shield circuit (see switch NODE (see fig. 100).

The logic, control, and level shifting circuit 150 (see fig. 2) may have other functions and circuits such as, but not limited to, a level shifting driver circuit 217, a low side transistor drive circuit 120, a blanking pulse generator 223, a bootstrap transistor drive circuit 225, and an under-voltage lockout circuit 227, as explained in more detail in separate figures below.

Referring now to FIG. 4, the level shifting driver circuit 217 is shown in more detail in embodiments, the level shifting driver circuit 217 may include a th inverter 405 and a second inverter 410 in a sequential chain in further embodiments, because the level shifting driver circuit 217 may drive a small gate width th level shifting transistor 203, a buffer stage may not be needed.

In embodiments, level-shifting driver circuit 217 is directly driven by a pulse width modulated high-side signal (PWM _ HS) from a controller (not shown). in embodiments, (PWM _ HS) signal may be supplied by an external control circuit in embodiments, the external control circuit may be an external controller in the same package or self-packaged with high-side device 105, low-side device 103, both devices in further embodiments, level-shifting driver circuit 217 may also include logic that controls when the level-shifting driver circuit communicates with level-shifting transistor 203 (see FIG. 3). in embodiments, an optional low-side lockout signal (LS _ UVLO) may be generated by an under-voltage lockout circuit within level-shifting driver circuit 217. if (Vcc) or (Vdd) of the low-side (Vdd _ LS) becomes lower than some reference voltage or a fraction of the reference voltage, the low-side lockout circuit may be used to turn off level-shifting driver circuit 217.

In further embodiments, the level shifting driver circuit 217 may generate a breakdown protection signal for the low side transistor (STP _ LS) to prevent breakdown caused by overlapping gate signals on the low side transistor 115 and the high side transistor 125 (STP _ LS) the function of the signal may be to ensure that the low side driver circuit 120 (see fig. 2) communicates only with the gate terminal of the low side transistor 115 when the gate signal to the high side transistor 125 is low in other embodiments, the output of the inverter 405 may be used to generate a breakdown protection signal (STP _ LS) for the low side transistor 115.

In further embodiments, logic for UVLO and breakdown protection may be implemented by adding a multiple input NAND to the inverter 405, where the inputs to NAND are the (PWM _ HS), (LS _ UVLO) and (STP _ HS) signals.

Referring now to fig. 5, the blanking pulse generator 223 may be used to generate a pulse signal corresponding to the turn-off transient of the low-side transistor 115 this pulse signal may then turn on the second level-shifting transistor 205 for the duration of the pulse, which triggers the control circuitry on the high-side device 105 (see fig. 1) to prevent a false pull-down of the level-shifting node 305 voltage.

FIG. 5 illustrates a schematic diagram of embodiments of the blanking PULSE generator 223 in embodiments the low side transistor 115 GATE signal (LS _ GATE) is fed as an input to the blanking PULSE generator 223, (LS _ GATE) signal is inverted by stage inverter 505 and then sent through RC PULSE generator 510 to generate a positive PULSE in embodiments the inverted signal may be required because the PULSE corresponds to the falling edge of the (LS _ GATE) signal the capacitor 515 in the RC PULSE generator 510 circuit may be used as a high pass filter allowing dv/dt at its input to appear across resistor 520. dv/dt becomes zero once at the input to RC PULSE generator 510 then capacitor 515 may be slowly charged through resistor 520 producing a slowly decaying voltage waveform.

Referring now to fig. 6, an example waveform 600 within the pedestal generator 223 is illustrated for embodiments, trace 605 shows the falling edge of the low side GATE PULSE (LS _ GATE), trace 610 shows the rising edge of the th stage inverter 505 output, trace 615 shows the output of the RC PULSE generator 510, and trace 620 shows the resulting pedestal (B _ PULSE) signal as the output of the pedestal generator 223.

Referring now to fig. 7, bootstrap transistor drive circuit 225 is illustrated IN greater detail, bootstrap transistor drive circuit 225 includes an inverter 730, a fourth buffer 735, and a second buffer 745 bootstrap transistor drive circuit 225 may receive a (BOOTFET _ DR _ IN) signal from low side driver circuit 120, (BOOTFET _ DR _ IN) signal may be inverted relative to LS _ GATE signal bootstrap transistor drive circuit 225 may be configured to provide a GATE drive signal, referred to as (BOOTFET _ DR), to the bootstrap transistor IN bootstrap charging circuit 157 (see fig. 1), as discussed IN greater detail below, (BOOTFET _ DR) GATE drive signal may be timed to turn on the bootstrap transistor when low side transistor 115 is turned on, and, because bootstrap transistor drive circuit 225 is driven by (Vcc), the output of this circuit may have a voltage that changes from 0 volts IN a low state to Vcc IN a high state (Vcc) +6 volts.

In embodiments, the turn-on transient of the (BOOTFET _ DR) signal can be delayed by introducing a series delay resistor 705 to the input of a second buffer 745, which can be the gate of the transistor in the final buffer stage in further embodiments, the turn-off transient of the low-side transistor 115 (see FIG. 1) can be delayed by adding a series resistor to the gate of the final pull-down transistor in the low-side drive circuit 120 in embodiments or multiple capacitors can be used in the bootstrap transistor drive circuit 225 and support voltages on the order of (Vcc), which can be 20 volts, for example, depending on the design of the end-user desired summing circuit in embodiments or multiple capacitors can be made with field dielectric to GaN capacitors instead of drain to source short enhancement mode transistors.

Referring now to fig. 8, a block diagram of the low side transistor drive circuit 120 is illustrated, the low side transistor drive circuit 120 may have inverter 805, buffer 810, second inverter 815, second buffer 820, and third buffer 825 the third buffer 825 may provide the (LS _ GATE) signal to the low side transistor 115 (see fig. 1) in embodiments two inverter/buffer stages may be used because the input to the GATE of the low side transistor 115 (see fig. 1) may be synchronized with (Vin) — thus (Vin) in the high state may correspond to (Vgate) of the low side transistor 115 in the high state, and vice versa.

some embodiments may include asymmetric hysteresis using a resistor divider 840 with a transistor pull-down 850.

Other embodiments may have multiple inputs nand for the (STP _ LS) signal (breakdown protection on the low side transistor 115.) IN embodiments, the low side drive circuit 120 may receive a breakdown protection signal (STP _ LS) · (STP _ LS) signal from the level shifting driver circuit 217 for purposes that may be similar to the previously described (STP _ HS) signal. (STP _ LS) signal may ensure that the low side transistor drive circuit 120 does not communicate with the gate 117 of the low side transistor 115 (see fig. 1) when the level shifting driver circuit 217 output is IN a high state, IN other embodiments, the output of the inverter stage 805 may be used as the (STP _ HS) signal for the level shifting driver circuit 217 and as the (boototjsdr _ IN) signal for bootstrapping the transistor drive fet 225.

In embodiments, low side transistor drive circuit 120 may use a plurality of input nand of the (LS _ UVLO) signal received from UVLO circuit 227 (see fig. 2.) other embodiments may use a turn off delay resistor that may be in series with the gate of the final pull down transistor in final buffer stage 825 in embodiments the delay resistor is used to ensure that the bootstrap transistor is turned off before low side transistor 115 is turned off.

Referring now to fig. 9, the startup circuit 155 is illustrated in more detail. The startup circuit 155 may be designed with numerous functionalities, as discussed in more detail below. Primarily, the startup circuit 155 may be used to provide an internal voltage (in this case START Vcc) and to provide sufficient current to support circuits driven by (Vcc). This voltage may remain on to support the circuit until (Vcc) is charged to the voltage (V +) required from outside the rail voltage 135. The start-up circuit 155 may also provide a reference voltage (Vref) that may be independent of the start-up voltage and a reference current sink (Iref).

In embodiments, the depletion transistor 905 can act as the primary current source in the circuit, in further embodiments, the depletion transistor 905 can be formed from a metal layer disposed over a passivation layer, in embodiments, the depletion transistor 905 can use a high voltage field plate (typically inherent to any high voltage GaN technology) as the gate metal.

In further embodiments, a series of identical diode-connected enhanced low voltage transistors 910 may be in series with the depletion transistor 905. the series of identical diode-connected enhanced low voltage transistors 910 may be connected in series between the th node 911 and the second node 912. or a plurality of intermediate nodes 913 may be disposed between each of the identical diode-connected enhanced low voltage transistors 910 in series.

In further embodiments, at the bottom end of the same diode-connected enhancement mode low voltage transistor 910 in series, the current mirror 915 may be comprised of two enhancement mode low voltage transistors and used to generate a reference current sink (Iref). the current mirror transistor 920 may be diode-connected, and the second current mirror transistor 925 may have a gate connected to the gate of the current mirror transistor. the source of the current mirror transistor 920 and the source of the second current mirror transistor 925 may be coupled and tied to ground, respectively, the drain terminal of the current mirror transistor 920 may be coupled to the second junction (junction)912 and the source terminal of the second current mirror transistor 925 may serve as the current sink terminal. this stack of the current mirror 915 and the same diode-connected enhancement mode low voltage transistor 910 in series may form a device referred to as a "source follower load" to the depletion mode transistor 905.

In other embodiments, when the gate 906 of the depletion transistor 905 is tied to ground, the source 907 of the depletion transistor may assume a voltage close to (Vpinch) when current is supplied to the "source follower load". at the same time, the voltage drop across the diode-connected transistor 920 in the current mirror 915 may approach the threshold voltage (Vth) of the transistor.

For example, if the gate of the start-up transistor 930 is connected from the bottom to the third same-diode-connected enhancement-type low-voltage transistor, the gate voltage of the start-up transistor may be 3 × (Vpinch-Vth)/n + Vth — thus, the start-up voltage may be 3 × (Vpinch-Vth)/n + Vth-3 × (Vpinch-Vth)/n as a more specific example, in embodiments where (Vpinch) is 40 volts, (Vth) is 2 volts, where n is 6 and (Vstartup) is 19 volts.

In other embodiments, the startup circuit 155 may generate a reference voltage signal (Vref) — in embodiments, the circuit that generates (Vref) may be similar to the startup voltage generation circuit discussed above-a reference voltage transistor 955 may be connected between two serially connected transistors in the same diode-connected enhancement mode low voltage transistor 910-in embodiments, (Vref) ═ Vpinch-Vth)/n.

In further embodiments, a disable pull-down transistor 935 may be connected across the gate of the enable transistor 930 to the source, when the disable signal is high, the enable transistor 930 will be disabled.A pull-down resistor 940 may be connected to the gate of the disable transistor 935 to prevent false turn-on of the disable transistor in other embodiments, a diode clamp 945 may be connected between the gate and source terminals of the enable transistor 930 to ensure that the gate-to-source voltage capability of the enable transistor is not violated during circuit operation (i.e., configured as a gate over-voltage protection device). in some embodiments of 35 , the diode clamp 945 may be fabricated with a series diode-connected GaN-based enhancement mode transistor 1050, as illustrated in FIG. 10.

Referring now to fig. 11, UVLO circuit 227 is illustrated in more detail in embodiments the UVLO circuit 227 may have a differential comparator 1105, a down level shifter 1110 and an inverter 1115 in further embodiments the UVLO circuit 227 may use (Vref) and (Iref) generated by the startup circuit 155 (see fig. 9) in the differential comparator/down level shifter circuit to generate the (LS _ UVLO) signal fed into the level shift driver circuit 217 (see fig. 2) and the low side transistor driver circuit 120 in embodiments the UVLO circuit 227 may also be designed with asymmetric hysteresis in further embodiments the output of the UVLO circuit 227 may be independent of a threshold voltage.

In other embodiments, Voltages (VA)1120 and (VB)1125 may be proportional to (Vcc) or (Vdd _ LS) and (Vref), respectively, as indicated by a resistor divider ratio on each input when (VA)1120> (VB)1125, the output of the inverting terminal goes low state (Vth) in embodiments because the current source produces a source follower configuration similarly when (VA)1120< (VB)1125, the output goes high state (Vref) in embodiments, a down level shifter 1110 may be needed because the low voltage needs to shift down threshold voltages 1115 to ensure that the low input to the lower stage is below (Vth) the down shift output may be inverted by a simple pull up inverter 1115 the output of inverter is the (LS _ UVLO) signal.

Referring now to FIG. 12, the bootstrap capacitor charging circuit 157 is illustrated in more detail, in embodiments, the bootstrap diode and transistor circuit 157 may include a parallel connection of a high voltage diode-connected enhancement mode transistor 1205 and a high voltage bootstrap transistor 1210 in further embodiments, the high voltage diode-connected enhancement mode transistor 1205 and the high voltage bootstrap transistor 1210 may be designed to share the same drain finger, in embodiments, a (BOOTFET _ DR) signal may be derived from the bootstrap transistor drive circuit 225 (see FIG. 2). As discussed above, the high voltage bootstrap transistor 1210 may be turned on coincident with the turning on of the low side transistor 115 (see FIG. 1).

Referring now to fig. 13, an alternative bootstrap diode and transistor circuit 1300 may be used in place of the bootstrap diode and transistor circuit 157 discussed above in fig. 12 in the embodiment illustrated in fig. 13, the depletion mode device 1305 cascoded by the enhancement mode low voltage GaN device 1310 may be connected as illustrated in schematic 1300 in another embodiment, the gate of the depletion mode device 1305 may be connected to ground to reduce the voltage stress on the cascode enhancement mode device 1310, depending on the pinch-off voltage of the depletion mode device.

High side device

Referring now to FIG. 14, an embodiment of the high side logic and control circuit 153 is illustrated in detail, hi embodiments, the high side driver 130 receives inputs from the level shifting receiver 1410 and the high side UVLO circuit 1415 and sends an (HS _ GATE) signal to the high side transistor 125 (see FIG. 1). in yet further embodiments, the pull up trigger circuit 1425 is configured to receive an (LSHIFT _1) signal and control the pull up transistor 1435. in embodiments, the second level shifting receiver circuit 1420 is configured to control the blanking transistor 1440 both the pull up transistor 1435 and the blanking transistor 1440 may be connected in parallel with the pull up resistor 1430. each circuit within the high side logic and control circuit 153 is shown in more detail in FIGS. 16-20, discussed below and in cases.

Referring now to FIG. 15, the th level-shifting receiver 1410 is illustrated in more detail in embodiments the th level-shifting receiver 1410 may convert the (L _ SHIFT1) signal to an (LS _ HSG) signal that may be processed by the high-side transistor driver 130 (see FIG. 14) to drive the high-side transistor 125 (see FIG. 1). in further embodiments, the th level-shifting receiver 1410 may have three enhancement transistors 1505, 1510, 1515 for use in a multi-level down shifter and a plurality of diode-connected transistors 1520 that act as diode clamps, as discussed in more detail below.

In embodiments, the level shifting receiver 1410 may SHIFT the (L _ SHIFT1) signal down by 3 Vth (e.g., each enhancement mode transistor 1505, 1510, 1515 may have a gate-to-source voltage near Vth) in embodiments, the last source follower transistors (e.g., transistor 1515 in this case) may have a three-diode connected transistor clamp 1520 across their gate-to-source in further embodiments, this arrangement may be used because their source voltages may be only up to (Vdd _ HS) (i.e., because their drains are connected to Vdd _ HS) and their gate voltages may be up to V (L _ SHIFT1) -2 Vth in embodiments, therefore, in embodiments, the maximum gate-to-source voltages on the last source follower transistors 1515 may be greater than the maximum rated gate-to-source voltage of the device technology, the output of the final source follower transistor 1515 is the input to the high-side drive transistor 130 (see fig. 1) (i.e., the output is the hsg. output is the HSG signal may be used in more than in other embodiments, more than three source follower transistors 1520.

Referring now to fig. 16, a second level shifting receiver 1420 is illustrated in greater detail, in embodiments, the second level shifting receiver 1420 may have a down level shifting circuit 1605 and an inverter circuit 1610. in embodiments, the second level shifting receiver 1420 may be constructed in a similar manner to the level shifting receiver 1410 (see fig. 15), except that the second level shifting receiver may have only down level shifting circuits (e.g., enhancement transistor 1615) and a follower inverter circuit 1610. in embodiments, the down level shifting circuit 1605 may receive a (L _ SHIFT2) signal from the second level shifting transistor 205 (see fig. 2). in embodiments, the inverter circuit 1610 may be driven by a (Vboot) signal and the gate voltage of the up transistor of the inverter may be used as a (BLANK _ FET) signal to drive a blanking transistor 1440 (see fig. 14). in the embodiment, the voltage may change from 0 volts in the low state to (Vboot + 0.5) in the high state (Vboot + 0.5. the gate voltage may be included in an embodiment, with more than three other source shifting transistors connected across the source clamp transistors, and the drain clamp transistors, 1615, with more than the other clamp transistors, the source shifting transistors, the drain clamp transistors, and the receiver, the drain clamp transistors, and the drain clamp transistors, are connected to the drain clamp transistors, and the drain, and.

Referring now to FIG. 17, the pull-up trigger circuit 1425 is illustrated in greater detail in embodiments, the pull-up trigger circuit 1425 may have a th inverter 1705, a second inverter 1710, an RC pulse generator 1715, and a gate-to-source clamp 1720 in embodiments, the pull-up trigger circuit 1425 may receive as an input the (L _ SHIFT1) signal and, in response, generate a pulse upon the (L _ SHIFT1) voltage transitioning approximately to the input threshold of the th inverter 1705. the generated pulse may be used as a (PUUP LLFET) signal to drive the pull-up transistor 1435 (see FIG. 14). the second inverter 1710 may be driven by (Vboost) rather than (Vdd _ HS) because the pull-up transistor 1435 gate voltage may need to be greater than the (L _ SHIFT1) signal voltage.

Referring now to fig. 18, high side UVLO circuit 1415 is illustrated in more detail in embodiments, high side UVLO circuit 1415 may have a down level shifter 1805, a resistor pull-up inverter 1810 with asymmetric hysteresis, and a GATE to source clamp 1815 in further embodiments, the (HS _ UVLO) signal generated by high side UVLO circuit 1415 may help prevent circuit failure by turning off the (HS _ GATE) signal generated by high side driver circuit 130 (see fig. 14) when the bootstrap capacitor 110 voltage becomes below a certain threshold in embodiments, the bootstrap capacitor 110 voltage (Vboot) (i.e., floating supply voltage) is measured and in response a logic signal is generated and combined with the output signal (LS _ HSG) from level shift receiver 1410, which is then used as an input to high side GATE driver circuit 130. further in this embodiment, UVLO circuit is designed, for example, to be used when the (vsoot) voltage is reduced to a level less than the switch node (vsoot) 145, which may be used at a different threshold level than in other embodiments.

In further embodiments, the high-side UVLO circuit 1415 may shift down (Vboot) in the down level shifter 1805 and pass the signal to an inverter with asymmetric hysteresis 1810 the output of the inverter with asymmetric hysteresis 1810 may generate an (HS _ UVLO) signal that is logically combined with the output from the level shifting receiver 1410 to turn off the high-side transistor 125 (see fig. 1). in some embodiments, hysteresis may be used to reduce the number of self-triggering turn-on and turn-off events of the high-side transistor 125 (see fig. 1) that may be detrimental to the overall performance of the half-bridge circuit 100.

Referring now to FIG. 19, a high-side transistor driver 130 is illustrated in greater detail, the high-side transistor driver 130 may have a th inverter stage 1905 followed by a high-side driver stage 1910. the th inverter stage 1905 may invert the shift-down (LS _ HSG) signal received from the level-shift 1 receiver 1410 (see FIG. 15.) the shift-down signal may then be sent through the high-side driver stage 1910. the high-side driver stage 1910 may generate a (HS _ GATE) signal to drive the high-side transistor 125 (see FIG. 1.) in further embodiments, the th inverter stage 1905 may contain a dual input NOR that may ensure that the high-side transistor 125 (see FIG. 1) is turned off when (HS _ UVLO) is in a high state.

Referring now to fig. 20, a reference voltage generation circuit 2000 may be used to generate a high-side reference voltage from a supply rail, this circuit may be placed on a high-side GaN device 105 to generate an internal power supply of a reference switch node voltage 145 in embodiments, the circuit 2000 may be similar to the startup circuit 155 in fig. 9. differences in the circuit 2000 may be the addition of a source follower capacitor 2010 connected between a th node 2011 and a second node 2012 in embodiments, the source follower capacitor 2010 may be required to ensure that a good stable voltage is generated between the th node 2011 and the second node 2012 that does not fluctuate with dv/dt occurring at the switch node (Vsw) 145. in embodiments, the reference voltage capacitor 2015 may be connected between the source of the reference voltage transistor 2055 and the second node 2012 in embodiments, the drain of the reference voltage transistor 2055 may be connected to a vsoot node (Vboot) in embodiments, the reference voltage capacitor 2015 may be required to ensure that Vref (is constantly) regulated and that the high-side reference voltage transistor 145 is used as a further sink for the switch node (Vref) in the other embodiments, the switch node 145 may be used as a non-sink (Vref) in response to the switch node — h + Vref 100 embodiments, see also the switch node (Vref).

Another difference in the circuit 2000 may be the addition of a high voltage diode-connected transistor 2025 coupled between the depletion mode transistor 2005 and the same diode-connected enhancement mode low voltage transistor 2020 in series (i.e., the gate of the transistor is coupled to the source of the transistor). more specifically, the high voltage diode-connected transistor 2025 may have a source coupled to the depletion mode transistor 2005, a drain coupled to the th node 2011, and a gate coupled to its source.

In embodiments, the shield capacitor 160 (see FIG. 1) may be connected from level shift node 305 (see FIG. 3) and a second level shift node (not shown) to the switch node 145 to assist in reducing false triggering discussed above in embodiments, the larger the value of the shield capacitor 160, the less susceptible the circuit is to false triggering caused by parasitic capacitance to ground however, during turn off of the high side transistor 125, the shield capacitor 160 may be discharged through a pull up resistor 303 (see FIG. 3) connected to the level shift node 305. this may significantly slow the turn off process of the high side transistor 125. in embodiments, this consideration may be used to set an upper limit on the value of the shield capacitor 160. in further embodiments, the over voltage condition on the level shift node 305 (see FIG. 3) may be prevented by using a clamp circuit 161 (see FIG. 1) between the level shift node and the switch node 145. in Vs embodiments, the clamp circuit 161 may be comprised of a diode connected transistor, wherein the drain of the shield capacitor is connected to the second level shift node 305 (see FIG. 1) and the switch node 145 may be placed between the Vs861 and the Vss switch node 145.

Half bridge operation No. 1

The following sequence of operation of half-bridge circuit 100 is merely an example, and other sequences may be used without departing from this invention. Reference will now be made to fig. 1, 2 and 14 simultaneously.

In embodiments, the low side logic, control and level shift circuit 150 sends a high signal to the low side transistor driver 120 when the (PWM _ LS) signal from the controller is high, the low side transistor driver 120 then communicates with the low side transistor 115 through the (LS _ GATE) signal to turn it on, this sets the switch node voltage (Vsw)145 to approximately 0 volts, when the low side transistor 115 is turned on, it provides a path for the bootstrap capacitor 110 to be charged through a bootstrap charging circuit 157 that may be connected between (Vcc) and (Vboot). the charging path has a parallel combination of a high voltage bootstrap diode 1205 (see FIG. 12) and a transistor 1210 (BOOTFET _ DR) signal providing a low resistance path for charging the bootstrap capacitor 110 (see FIG. 12).

A bootstrap diode 1205 (see fig. 12) may be used to ensure that there is a path for charging the bootstrap capacitor 110 during start-up when the low-side transistor 115 GATE drive signal (LS _ GATE) is not present during this time the (PWM _ HS) signal should be low if the (PWM _ HS) signal inadvertently turns on during this time (i.e., is in a high state), then the (STP _ HS) signal generated from the low-side transistor driver 120 will prevent the high-side transistor 125 from turning on, if the (PWM _ LS) signal is turned on when the (PWM _ HS) signal is turned on, then the (STP _ LS) signal generated from the level-shifting driver circuit 217 will prevent the low-side transistor 115 from turning on, and, in some embodiments, the (LS _ UVLO) signal may prevent the low-side transistor 115 and the high-side transistor 125 from turning on when (Vcc) or (Vdd _ LS) becomes below a preset threshold voltage level.

In further embodiments, when the (PWM _ LS) signal is low, the low side GATE signal (LS _ GATE) to the low side transistor 115 is also low. During the dead time between the (PWM _ LS) signal low state to (PWM _ HS) high state transition, the inductive load will force either the high-side transistor 125 or the low-side transistor 115 to turn on in synchronous rectifier mode, depending on the direction of power flow. If the high-side transistor 125 is turned on during dead-time (e.g., during boost mode operation), the switch node (Vsw)145 voltage may rise close to (V +)135 (the rail voltage).

In embodiments, the dv/dt condition on the switch node 145(Vsw) may tend to pull the level SHIFT node (LSHIFT _1)305 (see FIG. 3) to a low state relative to the switch node (Vsw)145 due to capacitive coupling to ground, this may turn on the high-side gate drive circuit 130, resulting in unintended triggering of the high-side transistor 125. in embodiments, this may not create dead time that may damage the half-bridge circuit 100 under a breakdown condition.

In further embodiments, after the dead time, when the (PWM _ HS) signal goes to a high state, the level shift driver circuit 217 may send a high signal (via the L1_ DR signal from the level shift driver circuit 217) to the gate of the th level shift transistor 203. the high signal will pull the th level shift node (LSHIFT _1)305 (see FIG. 3) low relative to the switching node (Vsw)145, which will generate a high signal at the input of the high-side transistor 125, turning on the high-side transistor 125. the switching node voltage (Vsw)145 will remain close to (V +) 135. in embodiments, during this time, the bootstrap capacitor 110 may be discharged through the th level shift transistor 203 (which is in an on state during this time).

If high-side transistor 125 remains on for a relatively long time (i.e., a large duty cycle), bootstrap capacitor 110 voltage will drop to a low voltage that is low enough that it will prevent high-side transistor 125 from turning off when the (PWM _ HS) signal goes low in embodiments, this may occur because the maximum voltage that can be reached by the (L _ SHIFT1) signal is (Vboost) that may be too low to turn off high-side transistor 125. in embodiments, this may be prevented by high-side UVLO circuit 1415, which forcibly turns off high-side transistor 125 by sending a high input to high-side gate drive circuit 130 when (Vboost) becomes below a certain level.

In yet further embodiments, when the (PWM _ HS) signal goes low, the level SHIFT transistor 203 will also turn off (via the L1_ DR signal from the level SHIFT driver circuit 217) which will pull the th level SHIFT node (LSHIFT _1)305 (see fig. 3) to a high state, however, in some embodiments, this process may be relatively slow because the high value pull-up resistor 303 (see fig. 3) (to reduce power consumption in some embodiments) requires charging all the capacitors attached to the th level SHIFT node (L _ SHIFT1)305 (see fig. 3), the output capacitance (Coss) including the th level SHIFT transistor 213 and the shield capacitor 160, which may increase the turn-off delay of the high-side transistor 125. to reduce the turn-off delay of the high-side transistor 125, the pull-up trigger circuit 1425 may be used to sense when the th level SHIFT node (L _ SHIFT1)305 (see fig. 3) becomes higher than (Vth) when this condition is applied to the pull-up transistor (lft) in parallel with the pull-up resistor 305 (ll1435) to facilitate the pull-up SHIFT process (flt) pull-up resistor 305 (flt) pulling up resistor 305 (flt) to accelerate the pull-up resistor (flt 583).

Half bridge circuit No. 2

Referring now to fig. 21, a second embodiment of a half-bridge circuit 2100 is disclosed, the half-bridge circuit 2100 may have the same block diagram as the circuit 100 illustrated in fig. 1, however, the level-shifting transistors in the circuit 2100 may operate with a pulsed input rather than a continuous signal, as described in more detail below.

With continuing reference to fig. 21, embodiments include an integrated half-bridge power conversion circuit 2100 that uses a low-side GaN device 2103, a high-side GaN device 2105, a load 2107, a bootstrap capacitor 2110, and other circuit elements, as discussed in more detail below, some embodiments may also have an external controller (not shown in fig. 21) that provides or multiple inputs to the circuit 2100 to regulate operation of the circuit, the circuit 2100 is for illustrative purposes only, and other variations and configurations are within the scope of the present disclosure.

As further illustrated by in fig. 21, in embodiments, the integrated half-bridge power conversion circuit 2100 may include a low-side circuit disposed on a low-side GaN device 2103 that includes a low-side transistor 2115 having a low-side control gate 2117, the low-side circuit may further include an integrated low-side transistor driver 2120 having an output 2123 connected to the low-side transistor control gate 2117, in another embodiment, there may be a high-side circuit disposed on a high-side GaN device 2105 that includes a high-side transistor 2125 having a high-side control gate 2127, the high-side circuit may further include an integrated high-side transistor driver 2130 having an output 2133 connected to the high-side transistor control gate 2127.

The high-side transistor 2125 may be used to control power input into the power conversion circuit 2100 and has a voltage source (V +)2135 (sometimes referred to as a rail voltage) connected to a drain 2137 of the high-side transistor 2125 may further have a source 2140 coupled to a drain 2143 of the low-side transistor 2115, forming a switching node (Vsw)2145 the low-side transistor 2115 may have a source 2147 connected to ground in embodiments the low-side transistor 2115 and the high-side transistor 2125 may be enhancement mode field effect transistors.

In some embodiments, high-side device 2105 and low-side device 2103 may be made of GaN-based materials. embodiments, the GaN-based material may include layers of GaN on layers of silicon.in other embodiments, the GaN-based material may include, but is not limited to, layers of silicon carbide, layers of GaN on sapphire or aluminum nitride.in embodiments, the GaN-based layers may include, but is not limited to, a composite stack of other group III nitrides, such as aluminum nitride and indium nitride, and group III nitride alloys, such as AlGaN and InGaN.

Low side device

In embodiments, the low side device 2103 may include logic, control, and level shifting circuitry (low side control circuitry) 2150 that controls switching of the low side transistor 2115 and the high side transistor 2125, along with other functions, as discussed in more detail below, the low side device 2103 may also include a startup circuit 2155, a bootstrap capacitor charging circuit 2157, and a shield capacitor 2160, as also discussed in more detail below.

Referring now to fig. 22, the circuitry within low side control circuit 2150 is functionally illustrated each of the circuitry within low side control circuit 2150 is discussed below and shown in more detail in fig. 23-28 under conditions in embodiments, the primary function of low side control circuit 2150 may be to receive , e.g., PWM signals, or the like, or a plurality of input signals from a controller and control the operation of low side transistor 2115 and high side transistor 2125.

the level shifting transistor 2203 may be an "on" pulse level shifting transistor and the second level shifting transistor 2215 may be an "off" pulse level shifting transistor in embodiments, a pulse width modulated high side (PWM _ HS) signal from a controller (not shown) may be processed by inverter/buffer 2250 and sent to on pulse generator 2260 and off pulse generator 2270 the on pulse generator 2260 may generate a pulse corresponding to a low-to-high state transient of the (PWM _ HS) signal, thus turning on the level shifting transistor 2203 during the duration of the pulse, the off pulse generator 2270 may similarly generate a pulse corresponding to a high-to-low state transition of the (PWM _ HS) signal, thus turning on the second level shifting transistor 2205 during the duration of the off pulse.

More specifically, turn-on may mean that the respective level-shifted node voltage is pulled low relative to the switch node (Vsw)2145, and turn-off may cause the respective level-shifted node to assume a (Vboost) voltage, since the level-shifting transistor 2203 and the second level-shifting transistor 2215 are each "on" only for the duration of the pulse, the power dissipation and stress level on these two devices may be less than the half-bridge circuit 100 illustrated in FIG. 1.

The th and second resistors 2207, 2208, respectively, may be added in series with the sources of the th and second level shifting transistors 2203, 2215, respectively, to limit the gate-to-source voltage and thus the maximum current through the transistors the th and second resistors 2207, 2208, respectively, may be smaller than the source follower resistors in the half bridge circuit 100 illustrated in fig. 1, which may facilitate faster pull-down actions of the th and second level shifting transistors 2203, 2215, reducing propagation delay to the high-side transistor 2125.

In further embodiments, the and second 2208 resistors may each be replaced by any form of current sink embodiments may connect the source of the and second 2205 level-shifting transistors, respectively, to a depletion mode device with a gate-to-source short circuit embodiments of depletion mode transistors formed in high voltage GaN technology may replace the enhancement mode gate stack with of high voltage field plate metal stacked on top of the field dielectric layer.

In further embodiments, the th resistor 2207 and the second resistor 2208, respectively, may be replaced by a current sink in embodiments, the reference current (Iref) generated by the startup circuit 2155 (see fig. 21) may be used.

The bootstrap transistor drive circuit 2225 may be similar to the bootstrap transistor drive circuit 225 illustrated in fig. 2 above. Bootstrap transistor drive circuit 2225 may receive an input from low side drive circuit 2220 (see fig. 22) and provide a gate drive signal, referred to as (BOOTFET _ DR), to the bootstrap transistor in bootstrap capacitor charging circuit 2157 (see fig. 21), as discussed in more detail above.

Referring now to fig. 23, an level shifting transistor 2203 is illustrated along with a pull-up resistor 2303 that may be located in a high-side device 2105 in embodiments, a 0 level shifting transistor 2203 may be operable as a pull-down transistor in a resistor pull-up inverter, similar to the 1 level shifting transistor 203 illustrated in fig. 3. as discussed above, a pull-up resistor 2303 may be disposed in the high-side device 2105 (see fig. 21.) a second level shifting transistor 2215 may have a similar configuration in embodiments, a th capacitance may be present between a th output terminal (LS _ NODE)2305 and a switch NODE (Vsw)2145 (see fig. 21) and a second capacitance may be present between the th output terminal 2305 and ground in 8652 embodiments, wherein the th capacitance is greater than the second capacitance may be designed such that the shield capacitor may be configured to minimize a power transfer between the switch NODE (Vsw)2145 (see fig. 21) and a switch NODE (Vsw) in response to a high dv/dt at the switch NODE 2145 (see fig. 21), a shield capacitor may also be configured to minimize a power transfer between the switch NODE (Vsw) and the switch NODE(s) to enable a shield current flow path between the switch NODE(s) and the switch NODE(s) in the switch NODE (2165) shield), which may be used to be further embodiments to be implemented to be used to minimize the switch NODE (see fig. 2) to shield the switch NODE (see also to shield the switch NODE(s) to shield the switch NODE (see fig. 2) and shield the switch NODE(s) shield circuit to shield the switch NODE(s) may be configured to shield the switch NODE(s) to shield the switch NODE (see fig. 2) may be used to shield the switch NODE(s) to shield the.

Referring now to FIG. 24, illustrating inverter/buffer circuit 2250 in more detail, in embodiments, the inverter/buffer circuit 2250 may have a th inverter stage 2405 and a th buffer stage 2410 in further embodiments, the inverter/buffer circuit 2250 may be driven directly by a (PWM _ HS) signal from a controller (not shown). The output of the th inverter stage 2405 may be an input signal (PULSE _ ON) to a turn-ON PULSE generator 2260 (see FIG. 22), while the output of the th buffer stage 2410 may be an input signal (PULSE _ OFF) to a turn-OFF PULSE generator 2270.

In embodiments, an optional (LS _ UVLO) signal may be generated by sending a signal generated by the UVLO circuit 2227 (see FIG. 22) into a NAND disposed in the inverter stage 2405 this circuit may be used to turn off the level shift operation if (Vcc) or (Vdd _ LS) becomes below some reference voltage (or fraction of a reference voltage). in further embodiments, the inverter/buffer circuit 2250 may generate a breakdown protection signal (STP _ LS1) for the low-side transistor 2115 (see FIG. 21) that may be applied to the low-side transistor gate driver circuit 2120, which may turn off the low-side transistor gate driver 2120 (see FIG. 21) when the (PWM _ HS) signal is high, preventing breakdown.

Referring now to FIG. 25, the turn-ON PULSE generator 2260 is illustrated in greater detail, in embodiments, the turn-ON PULSE generator 2260 may have a th inverter stage 2505, a th buffer stage 2510, an RC PULSE generator 2515, a second inverter stage 2520, a third inverter stage 2525, and a third buffer stage 2530 in further embodiments, the (PULSE _ ON) signal input from the inverter/buffer circuit 2250 (see FIG. 22) may be first inverted and then transformed into a turn-ON PULSE by the RC PULSE generator 2515 and a square wave generator.

In further embodiments, the turn-on pulse generator 2260 may comprise or a plurality of logic functions, such as binary or combinatorial functions in embodiments, the turn-on pulse generator 2260 may have a multiple input "or" "of the (STP _ HS) signal may have the same polarity as the (LS _ GATE) signal, therefore, if the (STP _ HS) signal is high (corresponding to the LS _ GATE signal being high), no turn-on pulse may be generated because the inverter circuit 2505 in FIG. 25 will pull low, which will deactivate the pulse generator 2515.

In further embodiments, RC pulse generator 2515 may include a clamp diode (not shown), clamp diodes may be added to ensure that RC pulse generator 2515 operates within a very small duty cycle of the (PWM _ LS) signal in some embodiments, turn-on pulse generator 2260 may be configured to receive an input pulse in the range of 2 nanoseconds to 20 microseconds and transmit a pulse of substantially constant duration within that range, in embodiments, if the voltage across the clamp diode becomes greater than (Vth), the clamp diode may turn on and short the resistor in RC pulse generator 2515 (while providing a very small capacitor discharge time), which may significantly improve the maximum operating duty cycle of pulse generator circuit 2260 (relative to the PWM _ HS signal).

Referring now to fig. 26, the shutdown PULSE generator 2270 is illustrated in greater detail in embodiments, the shutdown PULSE generator 2270 may have an RC PULSE generator 2603, a inverter stage 2605, a second inverter stage 2610, and a buffer stage 2615 in further embodiments, the shutdown PULSE generator 2270 may receive an input signal (PULSE OFF) from the inverter/buffer circuit 2250 (see fig. 22) that may then be passed to the RC PULSE generator 2603.

In further embodiments, the pulse from the RC pulse generator 2603 is sent through the th inverter stage 2605, the second inverter stage 2610, and the buffer stage 2615 the pulse may then be sent as an (L2_ DR) signal to the second level-shifting transistor 2215 (see FIG. 22). the clamping diode may also be included in the off pulse generator 2270. in some embodiments, the principle of operation may be similar to that discussed above with respect to the on pulse generator 2260 (see FIG. 25). such a principle of operation may ensure that the off pulse generator 2270 operates (i.e., the circuit will operate within a relatively small duty cycle) for the very low on time of the high-side transistor 2125 (see FIG. 21). in some embodiments, the off pulse generator 2270 may be configured to receive an input pulse in the range of 2 nanoseconds to 20 microseconds and transmit a pulse of substantially constant duration within that range.

In embodiments, the RC PULSE generator 2603 may include a capacitor connected with a resistive voltage divider network the output from the resistor may be a signal (INV) sent to an inverter 2275 (see fig. 22), the inverter 2275 generating a breakdown protection signal (STP _ LS2) that is transmitted to the low side driver circuit 2220 in further embodiments, the shutdown PULSE generator 2270 may include or multiple logic functions, such as binary or combinational functions in embodiments, similar to the (STP _ LS1) signal, (STP _ LS2) signals sent to NAND logic circuits within the low side driver circuit 2220 in embodiments, these signals may be used to ensure that the low side transistor 2115 (see fig. 21) does not turn on during the duration of the shutdown PULSE signal (PULSE OFF) (i.e., because the high side transistor 2125 turns OFF during the shutdown PULSE), in embodiments, this method may be adapted to compensate for the shutdown propagation delay (i.e., the PULSE OFF signal may achieve breakdown protection of the low side transistor 2115 only after the high side transistor 2115 is turned on completely.

In further embodiments, a second level shifting transistor 2215 may be used to level shift the blanking pulse to the high side device 2105 to achieve this point, the blanking pulse may be sent into the NOR input into the th inverter stage 2605.

Referring now to fig. 27, the blanking PULSE generator 2223 is illustrated in more detail, in embodiments, the blanking PULSE generator 2223 may be a simpler design than used in the half bridge circuit 100 illustrated in fig. 1 because the square wave PULSE generator is already part of the off PULSE generator 2270 in embodiments, the (LS _ GATE) signal is fed as an input to the blanking PULSE generator 2223 from the low side GATE drive circuit 2220 (see fig. 22.) this signal may be inverted and then sent through the RC PULSE generator to generate the forward PULSE in embodiments, the inverted signal may be used because the PULSE needs to correspond to the falling edge of the (LS _ GATE) signal, this output may be used as the blanking PULSE input (B _ PULSE) to the off PULSE generator 2270.

Referring now to fig. 28, the low side transistor drive circuit 2220 is illustrated in greater detail in embodiments, the low side transistor drive circuit 2220 may have a inverter stage 2805, a buffer stage 2810, a second inverter stage 2815, a second buffer stage 2820, and a third buffer stage 2825 in embodiments, two inverter/buffer stages may be used because the input to the GATE of the low side transistor 2115 is synchronized with the (PWM _ LS) signal, thus, in embodiments, the (PWM _ LS) high state may correspond to the (LS _ GATE) high state, and vice versa.

In further embodiments, the low side transistor driver circuit 2220 may also include an asymmetric hysteresis using a resistive divider with transistor pull-downs similar to the scheme described in 120 (see fig. 8). in embodiments, the low side transistor driver circuit 2220 may include a plurality of input nand (STP _ LS1) and (STP _ LS2) signals for (STP _ LS1) and (STP _ LS2) (breakdown prevention to turn on low side transistor 2115) signals may ensure that the low side transistor driver circuit 2220 (see fig. 22) may not communicate with the low side transistor 2115 (see fig. 21) when the high side transistor 2125 is turned on.

In further embodiments, the low side device 2103 (see fig. 21) may also include a start-up circuit 2155, a bootstrap capacitor charging circuit 2157, a shield capacitor 2160, and a UVLO circuit 2227 that may be similar to the start-up circuit 155, bootstrap capacitor charging circuit 157, shield capacitor 160, and UVLO circuit 227, respectively, as discussed above.

High side device

Referring now to FIG. 29, high side logic and control circuit 2153 and how it interacts with high side transistor driver 2130 is illustrated in more detail in embodiments, high side logic and control circuit 2153 may operate in a similar manner to high side logic and control circuit 153 discussed above in FIG. 15.

In embodiments, the level shifting 1 receiver circuit 2910 receives an (L _ SHIFT1) signal from the level shifting transistor 2203 (see FIG. 22), the level shifting transistor 2203 receives an ON pulse upon a low-to-high state transition of the (PWM _ HS) signal, as discussed above in response to the level shifting 1 receiver circuit 2910 driving the gate of the pull-up transistor 2960 (e.g., in embodiments, a low-voltage enhancement mode GaN transistor). in further embodiments, the pull-up transistor 2960 may then pull up the state storage capacitor 2955 voltage to a value close to (Vdd _ HS) relative to the switch node (Vsw)2145 voltage. the voltage on the state storage capacitor 2955 may then be transferred to the high-side transistor driver 2130 and to the gate of the high-side transistor gate 2127 (see FIG. 21) to turn on the high-side transistors 2125. in embodiments, the state storage capacitor 2955 may be of any other type of logic that is configured to change state in response to a pulse input signal and to latch the state storage capacitor 2955.

In further embodiments, during this time, the level-shifting 2 receiver circuit 2920 may maintain the pull-down transistor 2965 (e.g., a low voltage enhancement mode GaN transistor in embodiments) in an OFF state.

Similarly, the level shifting 2 receiver 2920 may receive an (L _ SHIFT2) signal from a second level shifting transistor 2215 (see FIG. 22), which second level shifting transistor 2215 receives a turn-off pulse upon a high-to-low state transition of the signal, as discussed above. in response, the level shifting 2 receiver circuit 2920 drives the gate of a pull-down transistor 2965 (e.g., a low-voltage enhancement mode GaN transistor in embodiments.) in further embodiments, the pull-down transistor 2965 may then pull-down (i.e., discharge) the state storage capacitor 2955 voltage to a value near a switch node (Vsw)2145, which switch node (Vsw)2145 may thus turn off the high-side transistor 2125 through a high-side transistor driver 2130.

With continued reference to fig. 29, the th and second shield capacitors 2970 and 2975, respectively, may be connected from the (L _ SHIFT1) and (L _ SHIFT2) nodes to help prevent false triggering during high dv/dt conditions at the switch node (Vsw)2145 (see fig. 21). in further embodiments, there may also be a clamp diode between the (L _ SHIFT1) and (L _ SHIFT2) nodes and the switch node (Vsw)2145 (see fig. 21). this may ensure that the potential difference between the switch node (Vsw)2145 (see fig. 21) and the (L _ SHIFT1) and (L _ SHIFT2) nodes is never above (Vth). this may be used to produce relatively rapid turn on and turn off of the high-side transistor 2125 (see fig. 21).

Referring now to fig. 30, a level shifting 1 receiver 2910 is illustrated in more detail in embodiments, the level shifting 1 receiver 2910 may include a down level shifter 3005, a th inverter 3010, a second inverter 3015, a th buffer 3020, a third inverter 3025, a second buffer 3030, and a third buffer 3135 in embodiments, the level shifting 1 receiver 2910 SHIFTs (i.e., modulates) the (L _ SHIFT1) signal down by a voltage of 3 Vth (e.g., using three enhancement mode transistors, where each enhancement mode transistor may have a gate-to-source voltage close to Vth).

in some embodiments, this configuration may be used because its source voltage may only be as high as (Vdd _ HS) (i.e., because its drain is connected to Vdd _ HS) and its gate voltage may be as high as V (L _ SHIFT1) -2 vth.

In further embodiments, the inverter 3010 may also have a NOR for high-side under-voltage lockout using the (UV _ LS1) signal generated by the high-side UVLO circuit 2915 in embodiments, the output of the level-shifting 1 receiver 2910 (see FIG. 29) may be the (PU _ FET) signal passed to the gate of the pull-up transistor 2960 (see FIG. 29). The signal may have a voltage that goes from 0 volts in the low state to (Vdd _ HS) + (Vdd _ HS-Vth) in the high state.

Referring now to fig. 31, a level shifting 2 receiver 2920 is illustrated in more detail in embodiments, the level shifting 2 receiver 2920 may be similar to the level shifting 1 receiver 2910 discussed above in further embodiments, the level shifting 2 receiver 2920 may include a blanking pulse generator 3105, a down level shifter 3110, a inverter 3115, a second inverter 3120, a buffer 3125, a third inverter 3130, a second buffer 3135 and a third buffer 3140 in embodiments, a blanking pulse generator 3105 may be used in addition to the 3 Vth down level shifter 3110 and the plurality of inverter/buffer stages.

In embodiments, this particular configuration may be applicable when the level shifting 2 receiver 2920 doubles as the high-side transistor 2125 (see fig. 21) is turned off and the blanking transistor 2940 (see fig. 29) is driven for better dv/dt immunity hi embodiments, the blanking pulse generator 3105 may be the same as the level shifting 2 receiver 1520 illustrated in fig. 17 hi embodiments, the level shifting 2 receiver 2920 (see fig. 29) may receive the (L _ SHIFT2) and (UV _ LS2) signals and in response pull down the transistor 2965 to transmit the (PD _ FET) signal hi embodiments, in further embodiments, the th inverter 3115 may have a dual input nand for the (UV _ LS2) signal from the high-side UVLO circuit 2915 (see fig. 29).

Referring now to fig. 32, the high side UVLO circuit 2915 is illustrated in more detail in embodiments, the high side UVLO circuit 2915 may include a down level shifter 3205 and a resistor pull-up inverter stage 3210 in embodiments, the high side UVLO circuit 2915 may be configured to prevent circuit failure by turning off the (HS _ GATE) signal to the high side transistor 2125 (see fig. 21) when the bootstrap capacitor 2110 voltage becomes below some threshold in example embodiments, the high side UVLO circuit 2915 is designed to engage when (Vboot) decreases to a value less than 4 Vth above the switch node (Vsw)2145 voltage in another embodiment, the output of the down level shifter 3205 may be the (UV _ LS2) signal transmitted to the second level shifting receiver 2920 and the output of the resistor pull-up inverter stage 3210 may be the (UV _ LS1) signal transmitted to the level shifting receiver 2910.

As discussed below, in embodiments, the high side UVLO circuit 2915 may be different from the high side UVLO circuit 1415 of the half bridge circuit 100 discussed above in fig. 14 and 18, respectively in embodiments, the (Vboot) signal may be shifted down by 3 Vth and transferred to the resistor pull-up inverter stage 3210 in further embodiments, the 3 Vth shift down output applied directly to the nand at the input of the level shift2 receiver circuit 2920 (see fig. 29) will engage the under-voltage lockout because the level shift2 receiver circuit 2920 (see fig. 29) controls the turn-off process based on the high side transistor 2125 (see fig. 21).

However, in embodiments, this may also keep the pull-up transistor 2960 (see FIG. 29) on because the bootstrap voltage may be too low in embodiments, this may create a conflict when the level shift2 receiver circuit 2920 (see FIG. 29) attempts to keep the high-side transistor 2125 (see FIG. 21) off, the level shift1 receiver circuit 2910 may attempt to turn on the high-side transistor.

Referring now to fig. 33, the high side transistor driver 2130 is illustrated in greater detail in embodiments, the high side transistor driver 2130 may include a th inverter 3305, a th buffer 3310, a second inverter 3315, a second buffer 3320, and a third buffer 3325 in embodiments, the high side transistor driver 2130 may be a more basic design than the high side transistor driver 130 used in the half bridge circuit 100 illustrated in fig. 1 in embodiments, the high side transistor driver 2130 receives an (S _ CAP) signal from a state storage capacitor 2955 (see fig. 29) and delivers a corresponding drive (HS _ GATE) signal to the high side transistor 2125 (see fig. 21) more specifically when the (S _ CAP) signal is in a high state, the (HS _ GATE) signal is in a high state and vice versa.

Half bridge operation No. 2

The following sequence of operation of half-bridge circuit 2100 (see fig. 21) is merely an example, and other sequences may be used without departing from this invention. Reference will now be made to fig. 21, 22 and 29 simultaneously.

In embodiments, when the (PWM _ LS) signal is in a high state, the low side logic, control and level shift circuit 2150 can send a high signal to the low side transistor driver 2120 which then communicates the signal to the low side transistor 2115 to turn it on.

In embodiments, the bootstrap transistor drive circuit 2225 may provide a drive signal (BOOTFET _ DR) to the bootstrap transistor that provides a low resistance path for charging the bootstrap capacitor 2110. in embodiments, the bootstrap diode may ensure that there is a path for charging the bootstrap capacitor 2110 during startup when no low side GATE drive signal (LS _ GATE) is present.A (PWM _ HS) signal should be in a low state during this time.if the (PWM _ HS) signal inadvertently turns on during this time, then the (STP _ HS) signal generated from the low side driver circuit 2220 will prevent the high side transistor 2125 from turning on.A (PWM _ LS) signal, if turned on when the (PWM _ HS) signal is turned on, then the STP (LS _1) and (STP _ LS2) signals generated from the inverter/buffer 220 and inverter 2275, respectively, will prevent the low side transistor 2115 from turning on.A (UVLS _ LS _ LO) signal may prevent the low side GATE 2117 and the high side GATE 2117 from becoming below a predetermined voltage (Vcc) or Vcc _ LS 21225 level in embodiments.

Conversely, in embodiments, when the (PWM _ LS) signal is in a low state, the (LS _ GATE) signal to the low-side transistor 2115 may also be in a low state in embodiments, during the dead time between the (PWM _ LS) low signal and the (PWM _ HS) high signal transition, the inductive load may force the high-side transistor 2125 or the low-side transistor 2115 to turn on in synchronous rectifier mode, depending on the direction of power flow if the high-side transistor 2125 is turned on during the dead time (e.g., in boost mode), the switch node (Vsw)2145 voltage may rise close to (V +)2135 (i.e., the rail voltage). this dv/dt condition on the switch node (Vsw)2145 may tend to pull the (L _ SHIFT1) node to a low state relative to the switch node (i.e., due to capacitive coupling to ground), which may turn on the high-side transistor 2130, causing non-conduction of the high-side transistor 2125.

In embodiments, this condition may be prevented from occurring by using the blanking pulse generator 2223 to sense the turn-off transient of the low side transistor 2115 and send a pulse to turn on the second level SHIFT transistor 2205 this may pull the (L _ SHIFT2) signal to a low state, which may then communicate with the level SHIFT2 receiver circuit 2920 to generate a blanking pulse to drive the blanking transistor 2940 in embodiments, the blanking transistor 2940 may act as a pull-up to prevent the (L _ SHIFT1) signal from going to a low state with respect to the switching node (Vsw) 2145.

In further embodiments, after the dead time, the on pulse generator 2260 may generate an on pulse when the (PWM _ HS) signal transitions from the low state to the high state. This may pull the (L _ SHIFT1) node voltage low for a brief period of time. In a further embodiment, this signal may be inverted by the level shift1 receiver circuit 2910, and a brief high signal will be sent to pull-up transistor 2960 that will charge the state storage capacitor 2955 to a high state. This may produce a corresponding high signal at the input of high-side transistor driver 2130 that will turn on high-side transistor 2125. The switch node (Vsw)2145 voltage may remain close to (V +)2135 (i.e., the rail voltage). The state storage capacitor 2955 voltage may remain in the high state during this time because there is no discharge path.

In yet further embodiments, the bootstrap capacitor 2110 may be discharged through the th level-shift transistor 2203 during the turn-on pulse, however, because the time period is relatively short, the bootstrap capacitor 2110 may not discharge as much as it would if the th level-shift transistor 2203 were turned on during the entire duration of the (PWM _ HS) signal (as is the case in the half-bridge circuit 100 in fig. 1). more specifically, in some embodiments, this may cause the switching frequency of UVLO engagement to be a relatively lower value than that of the half-bridge circuit 100 in fig. 1.

In embodiments, the turn-off pulse generator 2270 may generate a turn-off pulse when the (PWM _ HS) signal transitions from a high state to a low state this may pull the (L _ SHIFT2) node voltage low for a brief period of time this signal may be inverted by the level SHIFT2 receiver circuit 2920 and a brief high state signal may be sent to the pull-down transistor 2965 which will discharge the state storage capacitor 2955 to a low state this will generate a low signal at the input of the high side transistor driver 2130 which will turn off the high side transistor 2125 in further embodiments the state storage capacitor 2955 voltage may remain in a low state during this time because it has no discharge path.

In embodiments, the turn-off process in circuit 2100 may be relatively shorter than in the half-bridge circuit 100 of FIG. 1 because the turn-off process does not involve charging the level-shifting node capacitor through a high-value pull-up resistor in further embodiments, the turn-on and turn-off processes of the high-side transistor 2125 may be controlled by the turning-on of the substantially similar level-shifting transistors 2203, 2205, and thus the turn-on and turn-off propagation delays may be substantially similar.

ESD circuit

Referring now to fig. 34, in embodiments, or more pins (i.e., connections from a semiconductor device within an electronic package to external terminals on the electronic package) may use an electrostatic discharge (ESD) clamp to protect the circuit the following embodiments illustrate an ESD clamp that may be used on or more pins in or more embodiments disclosed herein, as well as other embodiments that may require ESD protection.

embodiments of electrostatic discharge (ESD) clamp 3400 are illustrated the ESD clamp 3400 may have a configuration using made of enhancement mode transistors or multiple source follower stages 3405 Each source follower stage 3405 may have a gate 3406 connected to a source 3407 adjacent the source follower stage in the embodiment illustrated in FIG. 34, four source follower stages 3405 are used, however in other embodiments fewer or more source follower stages may be used.

ESD transistor 3415 is coupled to or multiple source follower stages 3405 and may be configured to conduct a current greater than 500mA when exposed to an over-voltage pulse, as discussed below resistor 3410 is disposed between source 3420 of ESD transistor 3415 and each source 3407 of source follower stage 3405, drain 3408 of source follower stage 3405 is connected to drain 3425 of ESD transistor 3415. the sources 3407 of the last source follower stages are coupled to gate 3430 of ESD transistor 3415.

However, because the last source follower stages are transistors with a particular drain 3408 to source 3407 voltage and gate 3406 to source voltage, the current through the last resistor 3410 may be relatively large and may result in a larger gate 3430 to source 3420 voltage across ESD transistor 3415.

In other embodiments, ESD clamp 3400 may have multiple degrees of freedom with respect to transistor size and resistor values in embodiments, ESD clamp 3400 can be made smaller than other ESD circuit configurations in other embodiments, the performance of ESD clamp 3400 may be improved by incrementally increasing the size of the source follower stage 3405 as it is closer to ESD transistor 3415.

Referring now to fig. 35, an embodiment similar to ESD clamp 3400 in fig. 34 is illustrated, however, ESD clamp 3500 may have resistors in a different configuration, as discussed in more detail below, ESD clamp 3500 may have a configuration using made of or a plurality of enhancement mode transistors or a plurality of source follower stages 3505 each source follower stage 3505 may have a gate 3506 connected to a source 3507 adjacent the source follower stage in the embodiment illustrated in fig. 35, four source follower stages 3505 are used, however in other embodiments fewer or more source follower stages may be used, resistors 3510 are coupled between sources 3507 adjacent the source follower stages 3505, ESD transistor 3515 is coupled to source follower stages 3505 by resistors 3510 disposed between source 3520 of ESD transistor 3515 and source 3507 of source follower stages 3505. drain 8 of source follower stages 3505 may be coupled at and to drain 3525 of transistor 3515.

Electronic package

Referring now to fig. 36 and 37, in embodiments, or a plurality of semiconductor devices may be disposed in or a plurality of electronic packages various package configurations and types of electronic packages are available and are within the scope of the present disclosure fig. 36 illustrates examples referred to as a quad flat no-lead electronic package having two semiconductor devices inside.

The electronic package 3600 may have a package substrate 3610 with or a plurality of die pads 3615 surrounded by or a plurality of terminals 3620 in embodiments the package substrate 3610 may include a lead frame, while in other embodiments it may include an organic printed circuit board, a ceramic circuit, or another materials.

In the embodiment depicted in FIG. 36, an th device 3620 is mounted to a th die pad 3615 and a second device 3625 is mounted to a second die pad 3627 in another embodiment, or more of the th and second devices 3625, respectively, may be mounted on an insulator (not shown) mounted to a package substrate 3610 in embodiments, the insulator may be a ceramic or other non-conductive material the th and second devices 3620, 3625, respectively, are electrically coupled to terminals 3640 by wire bonds 3630 or any other type of electrical interconnect, such as flip chip bumps or pillars that may be used in flip chip applications, the wire bonds 3630 may extend between the device bond pads 3635 and the terminals 3640, and under conditions to the die pads 3615, 3627, and under other conditions to the device bond pads 3635 on adjacent devices.

In still other embodiments, the terminals 3640 and die attach pads 3615 and 3627 may only access the interior of the electronic package 3600 and other connections may be disposed outside of the electronic package some embodiments may have internal electrical routing and there may not be to correlation between the internal and external connections, more specifically some embodiments may have internal electrical routing.

In further embodiments, top surfaces of first device 3620 and second device 3625 (see FIG. 36) and package substrate 3610 may be encapsulated by a non-conductive material such as a molding compound various other electronic packages may be used such as, but not limited to, SOIC, DIPS, MCM, etc. furthermore, in embodiments each device may be in a separate electronic package while other embodiments may have two or more electronic devices within a single package.

Fig. 38 is a schematic illustration of an alternative embodiment of a half-bridge power conversion circuit 3800. The circuit 3800 has similar or identical features to other power conversion circuits discussed herein. Circuit 3800 includes control circuitry 3810, low-side driver 3820, low-side power switch 3830, high-side driver 3840, high-side power switch 3850, inductor 3860, filter 3870, load 3875, and slew detection circuits 3880 and 3890.

The circuit 3800 is configured to provide power to the load 3875 through the inductor 3860 and the filter 3870. The on-time of the high-side switch 3850 and the low-side switch 3830 proportionally controls the average voltage at the load 3875.

The features of the control circuitry 3810 may be similar or identical to other control circuits discussed herein, and the control circuitry 3810 is configured to provide control signals to the low-side driver 3820 and the high-side driver 3840, which causes the low-side driver 3820 to selectively turn on and off the low-side power switch 3830 and causes the high-side driver 3840 to selectively turn on and off the high-side power switch 3840. The control circuitry 3810 is configured to selectively turn on and off the low-side power switch 3830 and the high-side power switch 3840 in accordance with a received input signal in order to achieve a desired voltage at the load 3875.

Fig. 39 is a waveform diagram illustrating the -like operation of the circuit 3800.

During time period T-1, in response to a signal from control circuitry 3810, high-side driver 3840 causes the voltage at node VHG to be high, causing high-side driver 3850 to conduct. In addition, during time period T-1, the low side driver 3820 causes the voltage at node VLG to be low in response to a signal from the control circuitry 3810. Thus, during time period T-1, the voltage at switch node VSW is equal to V +.

Upon transition of time period T-1 to time period T-2, high-side driver 3840 causes node VHG to be low in response to a signal from control circuitry 3810, , upon node VHG being low, high-side switch 3850 turns off at the beginning of time period T-2, and current through inductor 3860 causes the voltage at switch node VSW to decrease toward 0V.

Once the voltage at the switch node VSW stops slewing, at the beginning of time period T-3, the slew detection circuit 3880 provides a slew-end signal to the low-side driver 3820 indicating that the switch node VSW is no longer slewing in response to the slew-end signal, and additionally in response to a signal from the control circuitry 3810, the low-side driver 3820 causes the voltage at the node VLG to be high, causing the low-side switch 3830 to turn on. in response to the low-side switch 3830 turning on, current flows from the pass inductor 3860 through the low-side switch 3830 to ground.

Upon transition of time period T-3 to time period T-4, the low-side driver 3820 causes the voltage at node VLG to be low in response to a signal from the control circuitry 3810, , upon node VHL being low, at the beginning of time period T-4, the low-side switch 3830 turns off and the current through inductor 3860 causes the voltage at switch node VSW to increase toward V +.

Once the voltage at switch node VSW stops slewing, at the beginning of time period T-5, slew detection circuit 3890 provides a slew-end signal to high-side driver 3840 indicating that switch node VSW is no longer slewing in response to the slew-end signal, and additionally in response to a signal from control circuitry 3810, high-side driver 3840 causes the voltage at node VHG to be high, causing high-side switch 3850 to turn on in response to high-side switch 3850 turning on, current flows from through-inductor 3860 to the V + power supply through high-side switch 3850.

Fig. 40 is a schematic illustration of an embodiment of a driver circuit 4000 examples of the driver circuit 4000 may be used, for example, in circuit 3800 as either or both of the low side driver 3820 and the high side driver 3840 the driver circuit 4000 includes a buffer 4010, a delay circuit 4020, logic 4030, and logic 4040.

Buffer 4010 can be an example of any of the other buffers discussed herein.

As understood by those skilled in the art, the delay circuit 4020 may be a conventional delay circuit. For example, the delay circuit 4020 may include a number of inverters or buffers connected in series. The delay circuit 4020 may additionally or alternatively comprise an RC delay filter comprising a series resistor, followed by a capacitor connected to the supply voltage source. Other delay circuits may additionally or alternatively be used.

Logic 4030 provides an output based on the th and second inputs connected to the slewing terminal input and the output of delay circuit 4020, respectively.

Logic 4040 provides an output based on the input and the second input connected to the output of logic 4030 and the output of buffer 4010, respectively.

In operation, buffer 4010 and delay circuit 4020 each receive a signal input IN. buffer 4010 drives of the inputs of logic 4040 according to the received signal, if another of the inputs of logic 4040 have received an on signal from logic 4030, logic 4040 turns on the signal received from buffer 4010 logic eight 4030 generates an on signal in response to receiving a slew end signal at of its inputs or a delayed signal from delay circuit 4020 at another of its inputs.

For example, if the driver circuit 4000 is used as the low side driver 3820 IN the circuit 3800, after receiving a logic high signal from the control circuitry 3810 at the input IN, the buffer 4010 drives of the inputs of the logic 4040 with the logic high signal additionally, IN response to receiving the logic high input from the slewing end input of the logic 4030 or from the delay circuit 4020, the logic 4030 generates a logic high signal at the other input of the logic 4040. IN response to the logic high signal from the logic 4030, the logic 4040 drives the output OUT high such that the low side switch 3830 turns on.

Thus, once the low side driver 3820 receives a logic high signal from the control circuit 3810, the low side driver 3820 drives the node VLG with a logic high in response to the received slew-end signal or the delay time set by the delay circuit 4020, and the low side switch 3830 is turned on.

Similarly, if driver circuit 4000 is used as high-side driver 3840 IN circuit 3800, buffer 4010 drives of the inputs of logic 4040 with a logic high signal after receiving a logic high signal from control circuit 3810 at input IN additionally, IN response to receiving a logic high input from the slewing end input of logic 4030 or from delay circuit 4020, logic 4030 generates a logic high signal at the other input of logic 4040 IN response to a logic high signal from logic 4030, logic 4040 drives output OUT high so that high-side driver 3840 turns on.

Thus, once high side driver 3840 receives a logic high signal from control circuit 3810, high side driver 3840 drives node VHG at a logic high in response to the received slew-end signal or the delay time set by delay circuit 4020, and high side driver 3840 turns on.

Fig. 41 is a schematic illustration of an embodiment of a slew detection circuit 4100 an example of the slew detection circuit 4100 may be used, for example, as either or both of the slew detection circuits 3880 and 3890 in the circuit 3800 the slew detection circuit 4100 includes a capacitor 4110, a clamp circuit 4120, a bias circuit 4130, and an output circuit 4140.

Capacitor 4110 is configured to couple a signal onto node SENSE, where the coupled signal results from a change in voltage difference between the voltages at the D and S input nodes. In the embodiment illustrated in fig. 38 to 41, when the switch node VSW turns around, the voltage difference between the voltages at the D and S input nodes of the turn-around detection circuits 3880 and 3890 decreases. Therefore, the voltage at the node SENSE of the slew detection circuit 4100 decreases relative to the voltage at the input node S.

The output circuit 4140 is configured to respond to a voltage at the node SENSE that is sufficiently low relative to the voltage at the input node S by generating a logic high signal at the output node SLEW END, indicating that the voltage across the drain and source of the corresponding power switch is slewing.

In the embodiment illustrated in FIGS. 38 through 41, the voltage difference between the voltages at the D and S input nodes of slew detection circuits 3880 and 3890 does not change once the switch node VSW has stopped slewing, therefore, the voltage at node SENSE of slew detection circuit 4100 increases relative to the voltage at input node S.

The output circuit 4140 is configured to respond to a voltage at the node SENSE that is sufficiently high relative to the voltage at the input node S by generating a logic low signal at the output node SLEW END, indicating that the voltage across the drain and source of the corresponding power switch has stopped slewing.

The clamp circuit 4120 is configured to prevent the voltage at the node SENSE from changing beyond or more of the minimum voltage and the maximum voltage.

The bias circuit 4130 is configured to generate a bias voltage at the node SENSE relative to the voltage at the input node S, which causes the output circuit 4140 to generate a low logic signal at the output node SLEW END. The impedance of the bias circuit 4130 is sufficiently high so that when the switch node VSW turns around, the voltage at node SENSE decreases relative to the voltage at the input node S sufficiently for the output circuit 4140 to respond by generating a logic high signal at the output node SLEW END.

In embodiments, the bias circuit 4130 generates additional signals for the output circuit 4140 as indicated by the dashed line connecting the bias circuit 4130 and the output circuit 4140.

Fig. 42A is a schematic illustration of a clamp circuit 4200, and the clamp circuit 4200 can be used as a clamp circuit 4120 of the turn-around detection circuit 4100. The clamp circuit 4200 includes a pull-up clamp 4210 and a pull-down clamp 4220.

Similarly, if the voltage at node SENSE becomes greater than the voltage at node S by a threshold determined by the pull-down clamp 4220, the pull-down clamp 4220 will become conductive and reduce or prevent any further -step reduction in the voltage at node SENSE.

Fig. 42B is a schematic illustration of a clamp circuit 4250, and the clamp circuit 4250 may be used as the clamp circuit 4120 of the slew detection circuit 4100. The clamp circuit 4250 comprises a bias generator 4260 and a pull-down clamp 4270.

The bias generator 4260 comprises a pull-up device 4264 and a diode-connected FET4266, in this embodiment, the pull-up device 4264 comprises a resistor. In operation, current from node PD through the pull-up device 4264 and FET4266 induces a voltage at the node bias. As understood by those skilled in the art, the voltage at the node bias is substantially determined by the threshold voltage of FET4266, such that the voltage at the node bias is substantially equal to the voltage at node S plus the threshold voltage of FET 4266.

The pull-down clamp 4270 becomes conductive if the voltage at the node SENSE becomes lower than the voltage at the node bias by more than the threshold voltage of the FET of the pull-down clamp 4270. accordingly, if the voltage at the node SENSE becomes lower than a voltage substantially equal to the voltage at the node S, the pull-down clamp 4270 will become conductive and reduce or prevent any further step reduction in the voltage at the node SENSE.

FIG. 43 is a schematic illustration of a bias circuit 4300, which bias circuit 4300 may be used as the bias circuit 4130 for the slew detection circuit 4100. the bias circuit 4300 includes an th diode 4310 and a second diode 4320 (or diode connected FET). additionally, the bias circuit 4300 includes a pull-up resistor 4330. in alternative embodiments, alternative pull-up devices may be used.

IN operation, current from node PD, through pull-up resistor 4330, and through th diode 4310 and second diode 4320 induces a voltage at node SENSE the voltage induced at node SENSE is substantially equal to the voltage at node S plus the threshold voltage of the th diode 4310 and second diode 4320 IN embodiments, bias circuit 4300 also includes a resistor 4340 connected between node SENSE and output IN 2.

Fig. 44 is a schematic illustration of an output circuit 4400, which may be used as the output circuit 4140 of the slew detection circuit 4100. The output circuit 4400 includes a switch 4410 and a pull-up resistor 4420. In alternative embodiments, alternative pull-up devices may be used.

IN operation, as understood by those skilled IN the art, when the voltage at the input node IN1 exceeds the threshold voltage of the switch 4410, the switch 4410 becomes conductive and reduces the voltage at the output node SLEW END to or towards the voltage at node S. Additionally, as understood by those skilled IN the art, when the voltage at the input node IN1 is less than the threshold voltage of the switch 4410, the switch 4410 is non-conductive and the pull-up resistor 4420 increases the voltage at the output node sled END to or towards the voltage at the node PD.

When the output circuit 4400 functions as the output circuit 4140 of the turn detection circuit 4100 and the turn detection circuit 4100 functions as the turn detection circuit 3880 of the circuit 3800, the voltage of the node SENSE of the turn detection circuit 4100 decreases relative to the voltage at the node S of the turn detection circuit 4100 in response to the voltage at the switch node VSW decreasing toward ground. In response to the voltage sensed at the node of the SLEW detection circuit 4100 being less than a threshold voltage higher than the voltage at the node S of the SLEW detection circuit 4100, the switch 4410 of the output circuit 4400 is non-conductive and the voltage at the node SLEW END L is pulled high by the pull-up resistor 4420. Due to the high voltage at node SLEW END L, low side driver 3820 causes the voltage at node VLG to be low and low side switch 3830 is non-conductive.

the voltage at node SENSE of the SLEW detection circuit 4100 is increased relative to the voltage at node S of the SLEW detection circuit 4100 by the bias circuit 4130 in response to the voltage sensed at the node of the SLEW detection circuit 4100 being greater than a threshold voltage above the voltage at node S of the SLEW detection circuit 4100, the switch 4410 of the output circuit 4400 conducts and the voltage at node SLEW END L is pulled low by the switch 4410 of the output circuit 4400 due to the low voltage at node SLEW END L, the low side driver 3820 causes the voltage at node VLG to be high and the low side switch 3830 to conduct if the control circuit 3810 has provided an appropriate signal to the low side driver 3820.

When the output circuit 4400 functions as the output circuit 4140 of the slew detection circuit 4100 and the slew detection circuit 4100 functions as the slew detection circuit 3890 of the circuit 3800, the voltage of the node SENSE of the slew detection circuit 4100 decreases relative to the voltage at the node S of the slew detection circuit 4100 in response to the voltage at the switch node VSW increasing toward the voltage at the node V +. In response to the voltage sensed at the node of the SLEW detection circuit 4100 being less than a threshold voltage higher than the voltage at node S of the SLEW detection circuit 4100, the switch 4410 of the output circuit 4400 is non-conductive and the voltage at node sled END H is pulled high by the pull-up resistor 4420. Due to the high voltage at node SLEW END H, high-side driver 3840 causes the voltage at node VHG to be low, and high-side switch 3850 is non-conductive.

the voltage at node SENSE of the SLEW detection circuit 4100 is increased relative to the voltage at node S of the SLEW detection circuit 4100 by the bias circuit 4130 in response to the voltage sensed at the node of the SLEW detection circuit 4100 being greater than a threshold voltage that is higher than the voltage at node S of the SLEW detection circuit 4100, the switch 4410 of the output circuit 4400 conducts and the voltage at node SLEW END H is pulled low by the switch 4410 of the output circuit 4400 due to the low voltage at node SLEW END H, if the control circuit 3810 has provided an appropriate signal to the high-side driver 3840, the high-side driver 3840 causes the voltage at node VHG to be high and the high-side switch 3850 to conduct.

FIG. 45 is a schematic illustration of an output circuit 4500, which output circuit 4500 can serve as the output circuit 4140 of the slew detection circuit 4100. the output circuit 4400 includes a latch 4510, an -th path 4520 and a second path 4540.

As illustrated and understood by those skilled in the art, the latch 4510 produces a SLEW END output based on the signals produced by the path 4520 and the second path 4540 at nodes P1, P21 and P22.

The th path 4520 includes a pass transistor 4524, a bias generator 4522, a pull-up device 4526, an inverter 4528, an inverter 4532, a capacitor 4534, and a pull-down resistor 4538.

The bias generator 4522 generates a voltage for the gate of the pass transistor 4524. The voltage applied at input node IN1 pulls up or down the voltage at node S1 IN cooperation with or working against the pull-up device 4526.

Inverter 4528 inverts the signal at node S1, and drives inverter 4532 with the inverted signal. Inverter 4532 receives the signal and drives node P1 through capacitor 4534.

The resistor 4538 biases the voltage at node P1 to the voltage at node S IN response to the voltage at the input node IN1 going from low to high, the th path 4520 causes the voltage at node P1 to go from low to high IN addition, the th path 4520 causes the voltage at node P1 to go from high to low IN response to the voltage at the input node IN1 going from high to low.

Because the pull-up device 4526 biases the voltage at node S1 high, the path 4520 changes from high to low relative to its response to a voltage transition at the input node IN1 and fast response to a voltage transition at the input node IN1 changing from low to high accordingly, the path 4520 responds more slowly to voltage slewing at the open joint point VSW and more quickly to a voltage stop slewing at the open joint point VSW.

Second path 4540 includes inverter 4542, coupling capacitor 4544, pull-down resistor 4546, pull-down transistor 4548, inverter 4552, coupling capacitor 4554, and pull-down resistor 4556.

Inverter 4542 inverts the signal at input node IN2, which is the same polarity as the signal at input node IN1, but at a lower voltage. Coupling capacitor 4544 couples the output of inverter 4542 to node P21, which node P21 is biased to the voltage at node S through pull-down resistor 4546. In response to the high voltage at node P1, pull-down transistor 4548 provides a fast path, causing the voltage at node P21 to be low, causing the output circuit 4500 to stop slewing in fast response to the voltage at switch node VSW. Making the voltage at node P21 low also prevents the output SLEW END from going high without an appropriate voltage transition at the input node IN 2.

Inverter 4542 also drives inverter 4552, inverter 4552 inverting the signal received from inverter 4542 and producing an inverted signal at its output. Coupling capacitor 4554 couples the output of inverter 4552 to node P22, which is node P22 biased to the voltage at node S through pull-down resistor 4556.

Because the voltage at input node IN2 is lower than the voltage at input IN1 and is directly connected with inverter 4542, and because the output of inverter 4542 is directly connected to node P21 through coupling capacitor 4544, second path 4540 changes from high to low IN quick response to a voltage transition at input node IN2 IN relation to its response to a voltage transition at input node IN2 changing from low to high. Thus, second path 4540 responds faster to voltage slewing at open joint point VSW, and more slowly to voltage stall slewing at open joint point VSW.

Thus, the path 4520 quickly causes the output circuit 4500 to provide the output SLEW END voltage indicative of the switch node VSW stopping SLEW, and the second path 4540 quickly causes the output circuit 4500 to provide the output SLEW END voltage indicative of the switch node VSW SLEW.

Fig. 46 is a schematic illustration of a pull-up circuit 4600, the pull-up circuit 4600 may be used as a pull-up device 4526 for the path 4520 of the output circuit 4500, as illustrated in fig. 45.

In embodiments, pull-up circuit 4600 includes resistor 4610.

In an alternative embodiment, pull-up circuit 4600 additionally includes bootstrap circuit 4650, bootstrap circuit 4650 increasing the speed at which the voltage at node S1 is pulled high. Bootstrap circuit 4650 includes a pull-up transistor 4620, a gate voltage generator 5640, and a bootstrap capacitor 4630.

IN operation, the voltage at the input node IN1 (node PGS IN pull-up circuit 4600) pulls up or down the voltage at the gate of the pull-up transistor 4620 depending on the turn-on 4642, resistor 4644, and diode 4646 the voltage at the gate of the pull-up transistor 4620 is less than a threshold voltage higher than the voltage at node S1 during negative voltage transitions at the input node IN1 and node S1 therefore, the pull-up transistor 4620 is turned off during negative voltage transitions at the input node IN1 and node S1 the pull-up transistor 4620 is turned off during positive voltage transitions at the input node IN1 and node S1 couples charge onto the gate of the pull-up transistor 4620 upon the voltage at the gate of the pull-up transistor 4620 being greater than the threshold voltage higher than the voltage at node S1, the pull-up transistor 4620 turns on and facilitates the pull-up of the voltage at node S1 additionally, as the voltage at node S1 increases, the pull-up capacitor 4630 couples charge onto the gate of the pull-up transistor 4620 such that the voltage at the pull-up node PD at the pull-up transistor 4620 increases to the pull-up node PD voltage at the pull-up node S1 such that the pull-up transistor PD increases at the pull.

Device 4710 includes source electrode 4712, drain electrode 4713, gate electrode 4714, and field plate electrode 4716, and is formed on GaN substrate 4740, in embodiments, GaN substrate 4740 is a GaN buffer layer over another substrate.

The 2DEG sensing layer 4750 is formed over the substrate 4740 in embodiments, the 2DEG (2-dimensional electron gas) is sensed by a combination of piezoelectric effect (stress), band gap differential, and polarization charge for example, there may be a reduction in conduction band at the surface where the conduction band drops below the fermi level to create a well filled with electrons embodiments, the 2DEG sensing layer 4750 includes algan in the range of, for example, about 20nm thick Al (25%) Ga (75%) N in alternative embodiments, the 2 sensing layer may include AlN, AlGaInN, or another material in embodiments, the 2DEG sensing layer 4750 includes a thin boundary layer with high Al content and a thicker layer with less Al content the 2DEG sensing layer 4750 may have a top cap layer in embodiments, the 2DEG sensing layer 4750 has no top GaN.

In embodiments, the 2DEG is generated from a rectangular quantum well, for example, two closely spaced heterojunction interfaces may be used to confine electrons to a rectangular quantum well.

Isolation regions may be formed in the 2DEG sensing layer 4750 between the devices 4710 and or a plurality of other devices in order to isolate carriers between the devices, isolation regions are electrically insulating and prevent conduction between adjacent electrical elements in embodiments isolation regions are formed by ion bombardment using neutral species such as oxygen, nitrogen, or argon.

Gate stack 4755 is formed over 2DEG sense layer 4750 for example, gate stack 4755 may include several layers of compound semiconductors (i.e., 3N layers) each including nitrogen and or more elements from column 3 of the periodic table, such as aluminum or gallium or indium or other elements.

A relatively thick insulator layer 4760 such as silicon nitride (e.g., Si3N4, Si2N, or SN) may be deposited over the gate stack 4755. in embodiments, the thick insulator layer 4760 comprises only a single layer of insulator material. in embodiments, the thickness of the thick insulator layer 4760 may be, for example, about 200nm, 300nm, 400nm, 500nm, or 600 nm. in embodiments, the thick insulator layer 4760 comprises only a single layer of insulator material.

Openings may be formed in the thick insulator layer 4760 to expose the source and drain ohmic contact regions 4715 and 4717 of the device 4710. Ohmic metal can then be deposited and patterned to form ohmic contacts 4770 in ohmic contact regions 4715 and 4717. After patterning the ohmic metal, the ohmic metal may be annealed to form a low resistance electrical connection between ohmic contact 4770 and 2DEG sensing layer 4750 exposed in ohmic contact regions 4715 and 4717.

A relatively thin insulator 4780 (e.g., nitride) may be applied over ohmic contact 4770 to protect them during further processing in embodiments , thin insulator layer 4780 comprises only a single layer of insulator material in embodiments , thin insulator 4780 is about 15nm, 25nm, 50nm, 75nm, 100nm, 200nm, 400nm, or 500nm in embodiments.

An opening in the thin insulator 4780 may be formed to expose the gate stack 4755 and a gate metal 4790 may be deposited. Gate metal 4790 can then be patterned to form gate contact 4792 and field plate 4794.

Interlayer dielectric (ILD)4785 may be formed over the gate metal structure and may be etched to form openings for vias 4795 to electrically connect ohmic contacts 4770 to source and drain electrodes 4712 and 4713, gate electrode 4714, and field plate electrode 4716, which are formed by depositing and etching a metal layer.

Additional or alternative structures and process steps may be used.

As understood by those skilled in the art, the structure of device 10 functions as a transistor if, for example, field plate electrode 4716 is electrically connected to source electrode 4712 through, for example, or multiple metallization layers, as when functioning as a transistor, source electrode 4712 functions as the source electrode for the transistor, drain electrode 4713 functions as the drain electrode for the transistor, and gate electrode 4714 functions as the gate electrode for the transistor.

As understood by those skilled in the art, the structure of device 10 may function as a capacitor if gate electrode 4714 is electrically connected to source electrode 4712 through, for example, or multiple metallization layers, as understood by those skilled in the art, drain electrode 4713 performs as a terminal of the th plate of the capacitor and field plate electrode 4716 performs as a terminal of the second plate of the capacitor when functioning as a capacitor, the voltage of electrically connected gate electrode 4714 and source electrode 4712 may be fixed at a voltage that is lower than the voltage of drain electrode 4713 and field plate electrode 4716 to prevent device 10 from conducting current from source electrode 4712 to drain electrode 4713 like diode-connected transistor .

For example, capacitor 4110 of slew detection circuit 4100 may be an example of device 10 with its gate and source electrodes both connected to ground, its drain electrode connected to the D input of slew detection circuit 4100, and its submitted plate electrode connected to node SENSE of slew detection circuit 4100.

The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense, the invention scope and the exclusive indicator of what is intended by the applicant to be the scope of the invention, are intended to be produced by the applicant in the language of the set of claims of this application in the specific form in which any subsequent correction is made.