阅读说明：本技术 一种晶片的制造方法 (Method for manufacturing wafer ) 是由 刘程秀 于 2018-06-28 设计创作，主要内容包括：本发明涉及一种晶片的制造方法即一种在供有抛光流体的情况下于两个覆以抛光布的旋转抛光盘之间同时抛光半导体晶片正面及背面的方法,在抛光过程中,半导体晶片的正面与下抛光盘的抛光布接触,且在抛光过程中,半导体晶片的背面与上抛光盘的抛光布接触。这样可得到抛光半导体晶片的改良位相,适用于半导体尤其适用于电子元件的制作。(The invention relates to a method for producing a wafer, namely a method for simultaneously polishing the front and back of a semiconductor wafer between two rotating polishing disks coated with a polishing cloth, while supplying a polishing fluid, during which the front of the semiconductor wafer is brought into contact with the polishing cloth of the lower polishing disk and during which the back of the semiconductor wafer is brought into contact with the polishing cloth of the upper polishing disk. This results in an improved phase for polishing semiconductor wafers, suitable for use in semiconductor, particularly electronic, component fabrication.)

1. A method of manufacturing a wafer by simultaneously polishing the front and back surfaces of a semiconductor wafer between two rotating polishing disks covered with polishing cloth in the presence of a polishing fluid, the front surface of the semiconductor wafer being in contact with the polishing cloth of the lower polishing disk during polishing and the back surface of the semiconductor wafer being in contact with the polishing cloth of the upper polishing disk during polishing, the polishing cloth of the lower polishing disk having a smooth surface, the surface of the polishing cloth of the upper polishing disk being spaced apart by grooves, the semiconductor wafer being located in a dicing frame of a carrier disk and held in a defined geometric path.

2. The method of claim 1, wherein the front side of the semiconductor wafer is subjected to final polishing subsequent to simultaneous front and back side polishing.

Technical Field

The invention relates to a method for producing a wafer, namely a method for producing a polished semiconductor wafer, by means of which an improved phase for polishing semiconductor wafers can be achieved, which is suitable for the production of semiconductors, in particular for electronic components.

Background

Semiconductor wafers intended for the fabrication of electronic components with line widths lower than or equal to 0.1 micrometer must have a number of specific properties, the most important of which is the known deviation of the flatness of the semiconductor wafer nanophase, i.e. of the entire wafer front surface, within the range of spatial wavelengths 0.2 to 20 millimeters (side correlation length) and within the "application area". The final nanophase of the semiconductor wafer is formed by a polishing process. To improve the planarity of semiconductor wafers, apparatus and methods for simultaneously polishing both front and back sides of a semiconductor wafer are being developed. Foreign countries also have some methods such as so-called double-side polishing in the U.S., European double-side polishing, and the like, which are improved methods. These prior art methods above do not meet the increasing demands on the nanophase of semiconductor wafers that have been subjected to double-side polishing for use in new elements of future generations.

Disclosure of Invention

In order to overcome the defects of the method, the invention provides a method for preparing a semiconductor wafer with improved nanometer phase, which can meet the requirements of manufacturing special required elements. To this end, a method is proposed for simultaneously polishing the front and back of a semiconductor wafer between two rotating polishing disks covered with a polishing cloth, the polishing cloth of the lower polishing disk having a smooth surface, the surface of the polishing cloth of the upper polishing disk being spaced apart by grooves, the semiconductor wafer being located in a dicing frame of a carrier disk and being held in a defined geometric path, in which, during the polishing process, the front of the semiconductor wafer is in contact with the polishing cloth of the lower polishing disk and, during the polishing process, the back of the semiconductor wafer is in contact with the polishing cloth of the upper polishing disk.

The final product obtained by the method is a semiconductor wafer which has been subjected to double-side polishing and has a greatly improved nanophase. In principle, the method of the invention can be used to produce objects in the shape of wafers, which consist of materials that can be processed using chemical-mechanical double-side polishing methods. For example, such materials are further processed primarily for use in the semiconductor industry, but are not limited to this particular application, and include silicon-germanium, silicon nitride, silicon dioxide, gallium arsenide and other III-V semiconductors. Among these, silicon in the form of a single crystal crystallized by the Czochralski method or the floating zone pulling method is preferable, and silicon having a crystal orientation of (99), (109) or (111) is particularly preferable. The process is particularly suitable for the production of silicon wafers having a diameter of 250 mm, 300 mm, 400 mm, 450 mm and a thickness of from several hundred micrometers to several centimeters, preferably from 400 micrometers to 1200 micrometers. The semiconductor wafer can be used directly as starting material for the production of semiconductor components or for its intended use after a final polishing step according to the prior art and/or after application of several layers (for example a back-sealing layer or a front-side epitaxial layer formed from silicon or other suitable semiconductor material) and/or after treatment by means of a thermal treatment.

Detailed Description

The method of the present invention will now be further described by taking the production of silicon wafers as an example. In principle, silicon wafers cut with circular saws or wire saws and having regions with a damage to the lattice depth of 12 to 45 μm, depending on the diameter and the type of sawing process, can be subjected directly to the double-side polishing step according to the invention. However, before double-side polishing is carried out, the clearly defined (sharp interface) and thus mechanically highly sensitive wafer edge is preferably rounded off by means of a grinding wheel of suitable profile or contour. In addition, to improve the geometry and partially remove the damaged crystalline layer, the silicon wafer may be subjected to a mechanical polishing step (e.g., lapping or grinding) to reduce the amount of material removed during the polishing step of the present invention. In order to remove crystalline regions of the wafer surface and edges that are inevitably damaged during the machining step and to remove any impurities that may be present, such as metal impurities that stick together with the damaged portions, an etching step may be followed. The etching step can be carried out by wet-chemical treatment or plasma treatment of the silicon wafer in an alkaline or acidic etching mixture. It is possible to polish only one silicon wafer, but it is usually cost effective to polish multiple silicon wafers simultaneously, the actual number depending on the configuration of the polisher. The silicon wafers are held in a geometric path determined by the processing parameters of the polisher and carrier disk during polishing, the carrier disk having a cutting frame sufficient to hold the silicon wafers. For example, the carrier disk is brought into contact with the polishing machine by means of pin gear transmission or involute gear transmission (via a rotating inner pin or ring and a substantially opposite rotating outer pin or ring), so that the carrier disk can be moved rotationally between the two polishing disks. Examples of parameters that affect the path of the silicon wafer with respect to the upper and lower polishing pads during the polishing operation include the size of the polishing pads, the design of the carrier pad, and the rotational speeds of the upper polishing pad, the lower polishing pad, and the carrier pad. If there is always a silicon wafer in the center of the carrier plate, the silicon wafer moves along a circle around the center of the polisher. If a plurality of silicon wafers are eccentrically arranged in a carrier plate, the carrier plate is rotated around its axis to form an hypocycloid path. The polishing process of the present invention is preferably a hypocycloid path. Preferably, four to six carrier plates (each carrying at least three silicon wafers arranged at regular intervals on a circular path) are used simultaneously. The carrier plate used in the method according to the invention can in principle be made of any material, but these materials have: (1) sufficient mechanical stability to mechanical loads caused by driving (in particular compressive and tensile loads); (2) the material must be impervious to significant chemical and mechanical attack by the polishing fluid and polishing cloth used to ensure adequate carrier disk life and to prevent contamination of the polished silicon wafer, (3) the material must also be suitable for producing highly planar, stress-free, and undulation-free carrier disks of the desired thickness and geometry. Such as those made of metal, plastic, fiber reinforced plastic or plastic coated metal, preferably the carrier plate is made of steel or fiber reinforced plastic, more preferably the carrier plate is made of stainless steel. The carrier plate has one or more cutting frames, preferably circular, to hold or accommodate one or more silicon wafers. To ensure that the silicon wafer can move freely within the rotary carrier plate, the cutting frame must be slightly larger in diameter than the silicon wafer to be polished. Preferably, the diameter is slightly larger than 0.1 to 2 mm, more preferably, the diameter is slightly larger than 0.3 to 1.3 mm. In order to prevent the edge of the wafer from being damaged by the inner edge of the cutting frame in the carrier plate during polishing, a plastic liner having the same thickness as the carrier plate is preferably added on the inner side of the cutting frame. The carrier plate used in the polishing method of the present invention preferably has a thickness of 400 to 1200 microns, more preferably depending on the final thickness of the polished silicon wafer. The amount of silicon removed in the polishing step is preferably from 5 to 100 microns, preferably from 10 to 60 microns, more preferably from 20 to 50 microns. In the context of the description with respect to the front-side down orientation of a semiconductor wafer, polishing cloths having a wide range of properties are commercially available. The polishing action is preferably carried out using a commercially available polyurethane (i.e., polyurethane) polishing cloth having a hardness of 45 to 125 (shore a). Particularly, a polyurethane polishing cloth mixed with polyethylene fibers and having a hardness of 65 to 95 (Shore A) is preferable. In the case of polishing silicon wafers, it is advisable to continuously supply a polishing fluid having a pH of from 8 to 12, preferably from 10 to 11, which comprises from 2 to 15% by weight, preferably from 2 to 5% by weight, of SiO2 in water, preferably at a polishing pressure of from 0.05 to 0.5 bar, preferably from 0.2 to 0.3. The silicon removal rate is preferably from 0.15 to 1.5 microns/min, more preferably from 0.4 to 0.8 microns/min. When the polished semiconductor wafer is unloaded from the lower polishing pad, it is preferably placed on a standard processing holder for further processing and proper orientation of its surface during subsequent processing steps. If the carrier holding the semiconductor wafer is configured to rotate 180 deg., the need to rotate the semiconductor wafer 180 deg. can be avoided, as compared to conventional double-side polishing, in which the semiconductor wafer is polished with its front side facing upward. The same advantageous results can be obtained with this work either manually or robotically. The above-described nature of the work is also conceivable when mounting a semiconductor wafer on a lower polishing pad. The polished semiconductor wafer can be removed from the lower polishing plate manually or by means of an automatic moving device; in both cases, it is preferable to use a vacuum suction device. After removal from the polishing pad, the semiconductor wafer is preferably immediately transferred into a liquid bath (preferably a water bath). In this way, it is possible to effectively prevent the polishing abrasive from drying out and from forming marks in the vacuum suction apparatus or, more broadly, the moving apparatus. After the polishing process is complete, any adhering polishing fluid is rinsed from the silicon wafer and the wafer is dried. Depending on their further use, the front side of these wafers may need to be subjected to final polishing according to the prior art, for example with a soft polishing cloth and with the aid of an SiO 2-based basic polishing fluid. For example, the polisher is equipped with five carrier disks made of stainless chromium steel, having a ground surface, a thickness of 720 microns, each carrier disk having six circular cutting frames with an inner diameter of 200.5 mm, which are arranged at regular or equal intervals on a circular path and are lined with a layer of polyvinylidene fluoride, and the polisher can polish 30 silicon wafers with a diameter of 200 mm simultaneously per batch. The upper and lower polishing disks were coated with a polyurethane polishing cloth reinforced with polyethylene fibers having a hardness of 74 (shore a) with SUBA 500. The polishing cloth stretched on the lower polishing disk has a smooth surface, the surface of the polishing cloth stretched on the upper polishing disk has a chessboard-like pattern formed by milling partial annular grooves with the width of 1.5 mm and the depth of 0.5 mm, and the grooves are arranged at intervals of 30 mm.