Stacked memory packages incorporating millimeter-wave antennas in die stacks
阅读说明:本技术 在裸片堆叠中并入毫米波天线的堆叠式存储器封装 (Stacked memory packages incorporating millimeter-wave antennas in die stacks ) 是由 J·F·克丁 O·R·费伊 于 2019-06-03 设计创作,主要内容包括:本申请案涉及在裸片堆叠中并入毫米波天线的堆叠式存储器封装。一种堆叠式半导体装置组合件可包含具有第一衬底和穿过所述第一衬底的第一组导通孔的第一半导体装置。所述第一组导通孔可界定天线结构的第一部分。所述堆叠式半导体装置组合件可另外包含具有第二衬底和穿过所述第二衬底的第二组导通孔的第二半导体装置。所述第二组导通孔可界定所述天线结构的第二部分。所述堆叠式半导体装置组合件也可包含将所述天线结构的所述第一部分电耦合到所述天线的所述第二部分的堆叠互连结构。(The application relates to stacked memory packages incorporating millimeter-wave antennas in a die stack. A stacked semiconductor device assembly may include a first semiconductor device having a first substrate and a first set of vias through the first substrate. The first set of vias may define a first portion of an antenna structure. The stacked semiconductor device assembly may additionally include a second semiconductor device having a second substrate and a second set of vias through the second substrate. The second set of vias can define a second portion of the antenna structure. The stacked semiconductor device assembly may also include a stacked interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna.)
1. A stacked semiconductor device assembly, comprising:
a first semiconductor device having a first substrate and a first set of vias through the first substrate, the first set of vias defining a first portion of an antenna structure;
a second semiconductor device having a second substrate and a second set of vias through the second substrate, the second set of vias defining a second portion of the antenna structure; and
a stacked interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.
2. The assembly of claim 1, further comprising:
one or more additional semiconductor devices each having an additional substrate and an additional set of vias through the additional substrate, the additional set of vias defining an additional portion of the antenna structure; and
one or more additional interconnect structures electrically coupling the additional portion of the antenna structure of each of the additional semiconductor devices to the first portion of the antenna structure and the second portion of the antenna structure.
3. The assembly of claim 1, wherein the first semiconductor device and the second semiconductor device are incorporated into a stacked three-dimensional integrated circuit, and wherein the antenna structure extends along a vertical surface of the stacked three-dimensional integrated circuit.
4. The assembly of claim 1, wherein the first semiconductor device includes at least one of a transmitter, receiver, or transceiver communicatively coupled to the antenna structure.
5. The assembly of claim 1, wherein said second semiconductor device includes at least two vias electrically coupled in a daisy-chain configuration from said second set of vias.
6. The assembly of claim 5, wherein at least a portion of an interconnect matrix defines an exposed laser ablation zone for tuning the antenna structure.
7. The assembly of claim 5, wherein at least a portion of an interconnect matrix defines a fuse for tuning the antenna structure.
8. The assembly of claim 1, wherein the stacked interconnect structure includes a ball grid array.
9. The assembly of claim 1, wherein the first substrate is a silicon substrate and the first set of vias are each through silicon vias, and wherein the second substrate is another silicon substrate and the second set of vias are each through silicon vias.
10. The assembly of claim 1, wherein the antenna structure is a millimeter wave antenna.
11. A method, comprising:
forming a first set of vias through a first substrate of a first semiconductor device, the first set of vias defining a first portion of an antenna structure;
forming a second set of vias through a second substrate of a second semiconductor device, the second set of vias defining a second portion of the antenna structure; and
electrically coupling the first portion of the antenna structure to the second portion of the antenna structure through a stacked interconnect structure.
12. The method of claim 11, further comprising, for one or more additional semiconductor devices:
forming an additional set of vias through an additional substrate, the additional set of vias defining an additional portion of the antenna structure; and
electrically coupling the additional portion of the antenna structure to the first portion of the antenna structure and the second portion of the antenna structure through an additional stacked interconnect structure.
13. The method of claim 11, further comprising:
communicatively coupling at least one of a transmitter, a receiver, or a transceiver to the antenna structure.
14. The method of claim 11, further comprising:
at least two vias from the second set of vias are electrically coupled in a daisy-chain configuration through an interconnect matrix.
15. The method of claim 11, further comprising tuning the antenna by at least one of a laser ablation process or a fuse blowing process.
16. The method of claim 11, wherein the stacked interconnect structure includes a ball grid array.
17. The method of claim 11, wherein the first substrate is a silicon substrate and the first set of vias are each through silicon vias, and wherein the second substrate is another silicon substrate and the second set of vias are each through silicon vias.
18. The method of claim 11, wherein the antenna structure is a millimeter wave antenna.
19. A stacked three-dimensional integrated circuit apparatus, comprising:
a first semiconductor device having a first substrate;
a second semiconductor device having a second substrate; and
an antenna structure extending along a vertical surface of the stacked three-dimensional integrated circuit device, the antenna structure defined by at least a first set of vias through the first substrate and a second set of vias through the second substrate.
20. The apparatus of claim 19, further comprising:
a stacked interconnect structure electrically coupling the first set of vias to the second set of vias.
Technical Field
Embodiments described herein relate to millimeter-wave antennas, and in particular, to stacked memory packages incorporating millimeter-wave antennas in a stack of dies.
Background
As computing devices increasingly come into close contact with our society, data access and mobility are becoming increasingly important to typical consumers. Compact wireless computing devices, such as cellular phones, tablet computers, notebook computers, and the like, are becoming faster, smaller, and more mobile. To meet the needs of the new generation of products, processing and memory packaging within mobile devices must become faster and more compact. The 5 th generation wireless system (5G) provides high throughput, low latency, high mobility, and high connection density. Mobile data communication using millimeter wave band (24-86GHz) is advantageous to produce 5G systems.
Antennas for millimeter-wave communications typically include antenna arrays deposited on Printed Circuit Boards (PCBs) within mobile devices. The area occupied by the antenna or footprint may reduce the density of devices attached to the PCB and may result in larger and less mobile devices. Further, a horizontal millimeter wave antenna may cause interference with neighboring circuitry over which the antenna may be deposited. These factors can make it difficult to incorporate millimeter-wave antennas into mobile devices. Other disadvantages may exist.
Disclosure of Invention
In one aspect, the present application provides a stacked semiconductor device assembly comprising: a first semiconductor device having a first substrate and a first set of vias through the first substrate, the first set of vias defining a first portion of an antenna structure; a second semiconductor device having a second substrate and a second set of vias through the second substrate, the second set of vias defining a second portion of the antenna structure; and a stacked interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.
In another aspect, the present application provides a method comprising: forming a first set of vias through a first substrate of a first semiconductor device, the first set of vias defining a first portion of an antenna structure; forming a second set of vias through a second substrate of a second semiconductor device, the second set of vias defining a second portion of the antenna structure; and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure through a stacked interconnect structure.
In another aspect, the present application additionally provides a stacked three-dimensional integrated circuit apparatus comprising: a first semiconductor device having a first substrate; a second semiconductor device having a second substrate; and an antenna structure extending along a vertical surface of the stacked three-dimensional integrated circuit device, the antenna structure defined by at least a first set of vias through the first substrate and a second set of vias through the second substrate.
Drawings
Fig. 1 is a diagram depicting an embodiment of a stacked semiconductor device assembly including a millimeter-wave antenna structure.
Fig. 2 is a diagram depicting an embodiment of a stacked semiconductor device assembly including a millimeter-wave antenna structure.
FIG. 3 is a diagram depicting an embodiment of an interconnect matrix having laser ablated portions.
FIG. 4 is a diagram depicting an embodiment of an interconnect matrix with fuses.
Figure 5 is a flow diagram depicting an embodiment of a method for forming a stacked integrated circuit package including millimeter-wave antenna structures.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure as defined by the appended claims.
Detailed Description
In the present disclosure, numerous specific details are discussed to provide a thorough and instructive description of embodiments of the present disclosure. One skilled in the art will recognize that the present disclosure may be practiced without one or more of the specific details. Well-known structures and/or operations typically associated with semiconductor devices may not be shown and/or described in detail to avoid obscuring other aspects of the disclosure. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may also be within the scope of the present disclosure.
The term "semiconductor device assembly" may refer to an assembly of one or more semiconductor devices, semiconductor device packages, and/or substrates, which may include interposers, supports, and/or other suitable substrates. The semiconductor device assembly may be fabricated in, but not limited to, discrete package form, strip or matrix form, and/or wafer panel form. The term "semiconductor device" generally refers to a solid state device comprising a semiconductor material. The semiconductor device may include a semiconductor substrate, such as from a wafer or substrate, a wafer, a panel, or a single die. The semiconductor device may additionally include one or more device layers deposited on the substrate. The semiconductor device may refer to a semiconductor die herein, but the semiconductor device is not limited to a semiconductor die.
The term "semiconductor device package" may refer to an arrangement in which one or more semiconductor devices are incorporated into a common package. A semiconductor package may include a casing or housing that partially or completely encloses at least one semiconductor device. The semiconductor package may also include a substrate carrying one or more semiconductor devices. The substrate may be attached to or otherwise incorporated within a housing or casing.
As used herein, the terms "vertical," "lateral," "upper," and "lower" may refer to the relative directions or positions of features shown in the drawings in a semiconductor device and/or semiconductor device assembly. For example, "upper" or "uppermost" may refer to a feature that is positioned closer to the top of the page than another feature. However, these terms should be broadly interpreted to include semiconductor devices and/or semiconductor device assemblies having other orientations, such as upside down or tilted orientations, where top/bottom, above/below, up/down, and left/right may be interchanged depending on the orientation.
Various embodiments of the present disclosure are directed to semiconductor devices, semiconductor device assemblies, semiconductor packages, and methods of manufacturing and/or operating semiconductor devices. In one embodiment of the present disclosure, a stacked semiconductor device assembly includes a first semiconductor device having a first substrate and a first set of vias through the first substrate, the first set of vias defining a first portion of an antenna structure. The semiconductor device assembly additionally includes a second semiconductor device having a second substrate and a second set of vias through the second substrate, the second set of vias defining a second portion of the antenna structure. The semiconductor device assembly also includes a stacked interconnect structure electrically coupling the first portion of the antenna structure to the second portion of the antenna.
Referring to fig. 1, a stacked
The
The
The
The
The
The
A benefit of the
Referring to fig. 2, an embodiment of a stacked
The
The
As shown in fig. 2, the vertical surfaces of the
Referring to fig. 3, an embodiment of an
The
Referring to fig. 4, an embodiment of an
The
Blowing the
Referring to fig. 5, an embodiment of a method 500 for forming a stacked integrated circuit package including millimeter-wave antenna structures is depicted. The method 500 may include, at 502, forming a first set of vias through a substrate of a first semiconductor device, the first set of vias defining a first portion of an antenna structure. For example, a first set of
The method 500 may additionally include forming a second set of vias through the substrate of the second semiconductor device at 504, the second set of vias defining a second portion of the antenna structure. For example, a second set of
The method 500 may also include electrically coupling a first portion of an antenna structure to a second portion of an antenna through a stacked interconnect structure, at 506. For example, the
A benefit of the method 500 is that the antenna structures can be formed along the vertical edges of the semiconductor device stack rather than occupying valuable horizontal real estate on a chip or printed circuit board. Other advantages may exist.
Although the present disclosure has been described with respect to certain embodiments, other embodiments (including embodiments that do not provide all of the features and advantages set forth herein) that are apparent to those of ordinary skill in the art are also within the scope of the present disclosure. The disclosure may encompass other embodiments not explicitly shown or described herein. Accordingly, the scope of the disclosure is defined only by reference to the appended claims and equivalents thereof.
- 上一篇:一种医用注射器针头装配设备
- 下一篇:半导体器件封装件和方法