阅读说明：本技术 一种多输入多输出的多格式数字视频处理实验平台 (Multi-input multi-output multi-format digital video processing experiment platform ) 是由 王娜 蔡鸥 刘一清 于 2019-10-24 设计创作，主要内容包括：本发明公开了一种多输入多输出的多格式数字视频处理实验平台,它包括电源模块、时钟模块、视频输入接口模块、视频并行处理模块、视频数据高速缓存模块、视频微处理器模块、程序执行缓存兼视频数据高速缓存模块与视频输出接口模块。本发明为研究数字视频处理技术提供了一个集视频采集、接收、处理与显示等多方面功能于一体的实验平台,适合进行多种技术算法的前期开发与验证。(The invention discloses a multi-input multi-output multi-format digital video processing experimental platform which comprises a power supply module, a clock module, a video input interface module, a video parallel processing module, a video data cache module, a video microprocessor module, a program execution cache and video data cache module and a video output interface module. The invention provides an experimental platform integrating the functions of video acquisition, receiving, processing, display and the like for researching the digital video processing technology, and is suitable for early development and verification of various technical algorithms.)

1. A multi-input multi-output multi-format digital video processing experiment platform is characterized by comprising a power supply module (1), a clock module (2), a video input interface module (3), a video parallel processing module (4), a video data cache module (5), a video microprocessor module (6), a program execution cache and video data cache module (7) and a video output interface module (8);

the power module (1) is respectively connected with the clock module (2), the video input interface module (3), the video parallel processing module (4), the video data cache module (5), the video microprocessor module (6), the program execution cache and video data cache module (7) and the video output interface module (8);

the clock module (2) is respectively connected with the video input interface module (3), the video parallel processing module (4), the video data cache module (5), the video microprocessor module (6), the program execution cache and video data cache module (7) and the video output interface module (8);

the video input interface module (3) is connected with the video parallel processing module (4);

the video parallel processing module (4) is respectively connected with the video data cache module (5), the video microprocessor module (6) and the video output interface module (8);

the video microprocessor module (6) is connected with a program execution cache and video data cache module (7).

2. The multi-input multi-output multi-format digital video processing experiment platform according to claim 1, wherein the video input interface module (3) is composed of multiple mutually independent HDMI video input interfaces (31) and multiple DVP camera video input interfaces (32), wherein any one of the HDMI video input interfaces (31) comprises an HDMI socket (311) and a video receiving chip (312), the HDMI socket (311) and the video receiving chip (312) are connected with each other, and the video input interface module (3) supports input of multiple HDMI videos in multi-resolution formats and input of multiple DVP camera videos.

3. The experimental platform for multi-input multi-output multi-format digital video processing as claimed in claim 1, wherein the video output interface module (8) is provided with multiple independent HDMI video output interfaces (81), wherein any one of the HDMI video output interfaces (81) comprises an HDMI socket (811) and a video forwarding chip (812), the HDMI socket (811) and the video forwarding chip (812) are connected to each other, and the video output interface module (8) supports multiple video outputs in multi-resolution formats.

4. The multi-input multi-output multi-format digital video processing experiment platform according to claim 1, wherein the video parallel processing module (4) adopts an FPGA (field programmable gate array) as a core processor.

5. The MSO multiformat digital video processing experiment platform as claimed in claim 1, wherein the video microprocessor module (6) employs an ARM core as a core processor.

6. The experimental platform for mimo multi-format digital video processing according to claim 1, wherein the video data cache module (5) and the program execution cache and video data cache module (7) each comprise a DDR3 high-speed memory chip, wherein the video data cache module (5) serves the video parallel processing module (4), and the program execution cache and video data cache module (7) serves the video microprocessor module (6).

Technical Field

The invention relates to the video acquisition, video reception, video processing and video display technology in the technical field of video, in particular to real-time video processing and algorithm development verification of a multi-path HDMI input interface and a DVP camera input interface and real-time video display of a multi-path HDMI output interface, and particularly relates to a multi-input multi-output multi-format digital video processing experimental platform.

Background

With the progress of information technology and the improvement of living standard, the application of digital video becomes more and more popular, so that it becomes necessary to continuously develop a general digital processing technology for videos with different formats.

Disclosure of Invention

The invention aims to provide a multi-input multi-output multi-format digital video processing experimental platform aiming at the defects of the prior art. Aiming at digital videos with various formats input by an HDMI (high-definition multimedia interface) input and acquired by a DVP (digital video processing) camera, the invention utilizes a parallel processing module to build a high-speed video flow path, and develops an upper-layer video processing algorithm by combining a microprocessor module, thereby providing an efficient and convenient platform for early development and verification of a digital video processing technology.

The specific technical scheme for realizing the purpose of the invention is as follows:

a multi-input multi-output multi-format digital video processing experimental platform is characterized by comprising a power supply module, a clock module, a video input interface module, a video parallel processing module, a video data cache module, a video microprocessor module, a program execution cache and video data cache module and a video output interface module;

the power supply module is respectively connected with the clock module, the video input interface module, the video parallel processing module, the video data cache module, the video microprocessor module, the program execution cache and video data cache module and the video output interface module; the power module is used for supplying power to the modules.

The clock module is respectively connected with the power supply module, the video input interface module, the video parallel processing module, the video data cache module, the video microprocessor module, the program execution cache and video data cache module and the video output interface module; the clock module is used for providing a reference clock for each module.

The video input interface module is connected with the video parallel processing module; the function of the device is to receive videos with different formats input from an HDMI interface or a DVP camera interface and convert the signals into the format required by the video parallel processing module.

The video parallel processing module is respectively connected with the video data cache module, the video microprocessor module and the video output interface module; the video parallel processing module is used for connecting the video input interface module and the video output interface module aiming at digital video streams with different formats, building a high-speed and high-efficiency parallel processing video flow path, controlling the read-write process of the video data cache module at the same time, completing the speed balance of video input and output, and simultaneously serving as the cache of the video parallel processing module to provide a storage operation space for video read-write.

The video microprocessor module is connected with the program execution cache and video data cache module;

the method has the functions that on the basis of acceleration of a video parallel processing module, an upper-layer video processing algorithm is developed and verified;

meanwhile, the program as a video microprocessor module provides a cache space for a large amount of data of the video stream when executing cache and executing upper-layer algorithms to balance the rate.

And the video output interface module is used for performing real-time output and display through the multi-path HDMI output interface after converting the signals of the digital video streams with different formats from the video parallel processing module.

Aiming at digital videos with various formats input by an HDMI (high-definition multimedia interface) input and acquired by a DVP (digital video processing) camera, the invention utilizes a parallel processing module to build a high-speed video flow path, and develops an upper-layer video processing algorithm by combining a microprocessor module, thereby providing an efficient and convenient platform for early development and verification of a digital video processing technology.

The invention has the following advantages:

the video input interface module comprises a plurality of paths of independent HDMI video input interfaces and DVP camera video input interfaces, wherein any path of HDMI video input interface comprises an HDMI socket and a video receiving chip, and the HDMI socket is connected with the video receiving chip in an interconnecting way; the video input interface module supports the input of multi-path HDMI videos in multi-resolution formats and DVP interface camera videos.

The video output interface module comprises a plurality of paths of independent HDMI video output interfaces, wherein any path of HDMI video output interface comprises an HDMI socket and a video forwarding chip, and the HDMI socket and the video forwarding chip are connected with each other; the video output interface module supports video output in a multi-path and multi-resolution format.

The video parallel processing module adopts an FPGA programmable logic array as a core processor, the video microprocessor module adopts an ARM core as the core processor, and the platform combines the high efficiency of FPGA parallel processing and the convenience of ARM upper layer development.

The video data cache module and the program execution cache and video data cache module both comprise DDR3 high-speed memory chips which respectively serve the video parallel processing module and the video microprocessor module.

The invention has the beneficial effects that:

the design of the invention is completely autonomous and does not depend on any finished product module. By adopting the FPGA + ARM architecture and combining the parallel efficient characteristic of the FPGA and the advantage of ARM embedded processing, the digital video processing can meet the real-time requirement, and meanwhile, developers can conveniently develop the algorithm by using high-level languages. In addition, the reconfigurability of the FPGA enables the bottom hardware module of the video processing to be very convenient to customize and redefine. The platform is provided with a DDR3 high-speed cache for the video parallel processing module and the video microprocessor module, so that the capacity of video data cache is improved, and the FPGA and the ARM can conveniently and independently complete the video processing and algorithm development of the bottom layer and the upper layer in a high-efficiency manner. The platform combines the high efficiency of FPGA parallel processing and the convenience of ARM upper-layer development. The platform is provided with a plurality of HDMI input interfaces, a DVP camera input interface and a plurality of HDMI output interfaces, is compatible with multi-format video input, and has certain advancement in the fields of video acquisition, receiving, processing and display.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a block diagram of the workflow of the present invention;

FIG. 3 is a block diagram of a multi-format input video input interface according to the present invention;

FIG. 4 is a block diagram of a video output interface for multi-format output according to the present invention.

Detailed Description

Referring to fig. 1, the present invention includes a power module 1, a clock module 2, a video input interface module 3, a video parallel processing module 4, a video data cache module 5, a video microprocessor module 6, a program execution cache and video data cache module 7, and a video output interface module 8;

the power module 1 is respectively connected with a clock module 2, a video input interface module 3, a video parallel processing module 4, a video data cache module 5, a video microprocessor module 6, a program execution cache and video data cache module 7 and a video output interface module 8;

the clock module 2 is respectively connected with the video input interface module 3, the video parallel processing module 4, the video data cache module 5, the video microprocessor module 6, the program execution cache and video data cache module 7 and the video output interface module 8;

the video input interface module 3 is connected with the video parallel processing module 4;

the video parallel processing module 4 is respectively connected with the video data cache module 5, the video microprocessor module 6 and the video output interface module 8;

the video microprocessor module 6 is connected with a program execution cache and video data cache module 7.

The video input interface module 3 is composed of multiple mutually independent HDMI video input interfaces 31 and multiple DVP camera video input interfaces 32, wherein any one of the HDMI video input interfaces 31 includes an HDMI socket 311 and a video receiving chip 312, the HDMI socket 311 and the video receiving chip 312 are connected with each other, and the video input interface module 3 supports the input of multiple HDMI videos in multiple resolution formats and DVP camera videos.

The video output interface module 8 is provided with multiple paths of independent HDMI video output interfaces 81, wherein any path of HDMI video output interface 81 comprises an HDMI socket 811 and a video forwarding chip 812, the HDMI socket 811 and the video forwarding chip 812 are connected with each other, and the video output interface module 8 supports multiple paths of video output in a multi-resolution format.

The video parallel processing module 4 adopts an FPGA programmable logic array as a core processor, and the video microprocessor module 6 adopts an ARM core as the core processor.

The video data cache module 5 and the program execution cache and video data cache module 7 both include DDR3 high-speed memory chips, wherein the video data cache module 5 serves the video parallel processing module 4, and the program execution cache and video data cache module 7 serves the video microprocessor module 6.