Semiconductor device with a plurality of semiconductor chips
阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 三好智之 森睦宏 竹内悠次郎 古川智康 于 2018-04-12 设计创作，主要内容包括：提供同时实现低导通损失和低开关损失的IGBT和应用其的电力变换装置。特征在于具备：半导体基板；第1导电类型的半导体层；第2导电类型的阱区域；第1栅电极及第2栅电极,隔着栅极绝缘膜而与所述半导体层及所述阱区域相接,夹着所述阱区域相互相邻地形成；第1导电类型的发射极区域；第2导电类型的供电区域；发射极电极；第2导电类型的集电极层；以及集电极电极,其中,所述第1栅电极及所述第2栅电极的间隔比与和各自相邻的其它栅电极之间的间隔窄,所述第1栅电极及所述第2栅电极各自与开关栅极布线或载流子控制栅极布线中的某一方电连接,与所述载流子控制栅极布线连接的栅电极的数量比与所述开关栅极布线连接的栅电极的数量多。(Provided are an IGBT that achieves both low conduction loss and low switching loss, and a power conversion device using the same. Characterized in that it comprises: a semiconductor substrate; a semiconductor layer of a 1 st conductivity type; a well region of a 2 nd conductivity type; a 1 st gate electrode and a 2 nd gate electrode which are in contact with the semiconductor layer and the well region with a gate insulating film interposed therebetween and are formed adjacent to each other with the well region interposed therebetween; an emitter region of a 1 st conductivity type; a power supply region of the 2 nd conductivity type; an emitter electrode; a collector layer of a 2 nd conductivity type; and a collector electrode, wherein a distance between the 1 st gate electrode and the 2 nd gate electrode is narrower than a distance between the 1 st gate electrode and the 2 nd gate electrode and another gate electrode adjacent to each other, each of the 1 st gate electrode and the 2 nd gate electrode is electrically connected to one of a switching gate wiring and a carrier control gate wiring, and the number of gate electrodes connected to the carrier control gate wiring is larger than the number of gate electrodes connected to the switching gate wiring.)
1. A semiconductor device is characterized by comprising:
a 1 st conductive type semiconductor layer formed on a 1 st main surface of the semiconductor substrate;
a well region of the 2 nd conductivity type formed on the 1 st main surface side in contact with the semiconductor layer of the 1 st conductivity type;
a 1 st gate electrode and a 2 nd gate electrode which are in contact with the 1 st conductivity type semiconductor layer and the 2 nd conductivity type well region with a gate insulating film interposed therebetween, and which are formed adjacent to each other with the 2 nd conductivity type well region interposed therebetween;
an emitter region of a 1 st conductivity type formed on the 1 st main surface side of the well region of the 2 nd conductivity type;
a 2 nd conductive type power supply region penetrating the 1 st conductive type emitter region and electrically connected to the 2 nd conductive type well region;
an emitter electrode electrically connected to the well region of the 2 nd conductivity type via the power supply region of the 2 nd conductivity type;
a collector layer of a 2 nd conductivity type which is in contact with the semiconductor layer of the 1 st conductivity type and is formed on a 2 nd principal surface side of the semiconductor substrate on a side opposite to the 1 st principal surface side; and
a collector electrode electrically connected to the collector layer of the 2 nd conductivity type,
the interval between the 1 st gate electrode and the 2 nd gate electrode is narrower than the interval between the adjacent other gate electrodes,
the 1 st gate electrode and the 2 nd gate electrode are each electrically connected to either a switching gate wiring or a carrier control gate wiring,
the number of gate electrodes connected to the carrier control gate wiring is larger than the number of gate electrodes connected to the switching gate wiring.
2. The semiconductor device according to claim 1,
the 1 st gate electrode and the 2 nd gate electrode are trench gate type gate electrodes provided in trenches formed to penetrate the 2 nd conductivity type well region.
3. The semiconductor device according to claim 1,
the 1 st gate electrode and the 2 nd gate electrode are side gate type gate electrodes having no conductive region between the adjacent other gate electrodes.
4. The semiconductor device according to claim 3,
the 1 st gate electrode and the 2 nd gate electrode are sidewall gate type gate electrodes having a sidewall shape whose width is wider from the emitter electrode side toward the collector electrode side.
5. The semiconductor device according to any one of claims 1 to 4,
the 1 st gate electrode and the 2 nd gate electrode can be controlled independently of each other,
the semiconductor device is provided with:
(a) a 1 st state in which a voltage equal to or higher than a threshold voltage is applied to both of the gate electrode connected to the switching gate line and the gate electrode connected to the carrier control gate line;
(b) a 2 nd state in which a voltage equal to or higher than a threshold voltage is applied to the gate electrode connected to the switching gate wiring, and a voltage lower than the threshold voltage is applied to the gate electrode connected to the carrier control gate wiring; and
(c) and a 3 rd state in which a voltage smaller than a threshold value is applied to both the gate electrode connected to the switching gate wiring and the gate electrode connected to the carrier control gate wiring.
6. The semiconductor device according to claim 5,
when the semiconductor device is switched from a conductive state to a non-conductive state, the semiconductor device is switched in the order of (a), (b), and (c).
7. The semiconductor device according to claim 5,
when the semiconductor device is transferred from a non-conductive state to a conductive state, the semiconductor device is transferred in the order of (c), (b), and (a).
8. The semiconductor device according to claim 5,
when the semiconductor device is transferred from a non-conductive state to a conductive state, the semiconductor device is transferred in the order of (c), the order of (a), the order of (b), and the order of (a).
9. The semiconductor device according to any one of claims 5 to 8,
the time after the (b) is 10 μ sec or more when the semiconductor device is changed from the on state to the off state.
10. The semiconductor device according to any one of claims 5 to 9,
the time after the (b) is 0.5 μ sec or more when the semiconductor device is transferred from a non-conductive state to a conductive state.
Technical Field
The present invention relates to a semiconductor device and a power conversion device using the same, and particularly to a technique effective for reducing power loss of an IGBT and for increasing efficiency of a power conversion device.
Background
Global warming is an important urgent problem common throughout the world, and one of the measures to this problem is to increase the degree of expectation of contribution of power electronics technology. In particular, for the efficiency improvement of an inverter that performs a power conversion function, power semiconductor devices mainly including an IGBT (Insulated Gate Bipolar Transistor) that functions as a power switch and a diode that functions as a rectifier constituting the inverter are required to have low power consumption.
Fig. 20 is a partial circuit diagram of a conventional inverter. For the IGBT70 having the insulated
Since the IGBT70 and the
As a technique for reducing on-loss and off-loss of an IGBT, for example, a technique related to "an IGBT structure having 2 gates that can be independently controlled" as described in
Fig. 21 is a sectional view of the IGBT described in
Next, at the time of off-state, carriers contributing to conductivity modulation are discharged to
Here, in the present structure having 2 independently controllable gates, a voltage smaller than the threshold voltage can be applied to one gate G2 prior to G1 immediately before turning off, and a drift region in which conductivity modulation is suppressed can be formed temporarily. This can reduce the current caused by carriers discharged at the time of turn-off, and can reduce turn-off loss by applying a reverse voltage between the collector and emitter at a high speed. Namely, the following technique is used: the gate bias applied to G1 and G2 can be dynamically controlled immediately before the conductive state and the non-conductive state are achieved, and loss occurring at the time of off-state can be reduced by this control.
Fig. 22 is a cross-sectional view of an IGBT described in
In the on state, electron carriers are injected from the
Disclosure of Invention
In these conventional IGBTs, in order to further reduce the loss, it is effective to further improve controllability of the conductivity modulation in the drift region at the on and off times. That is, the following configuration is required: the conductivity modulation can be promoted at the time of on-state, and therefore the carrier accumulation effect is improved, while the conductivity modulation is suppressed immediately before off-state, and therefore the carrier extraction efficiency is improved.
However, in the IGBT of fig. 21, it is difficult to improve the conductivity modulation at the time of on-state, and in the IGBT of fig. 22, the action of extracting carriers immediately before off is insufficient, and it is difficult to further improve the trade-off relationship between the on-state loss and the off-state loss of the IGBT by these structures.
Therefore, an object of the present invention is to provide an IGBT capable of achieving both low on loss and low switching loss in the IGBT and achieving low power consumption, and a power conversion device using the IGBT.
In order to solve the above problem, the present invention is characterized by comprising: a 1 st conductive type semiconductor layer formed on a 1 st main surface of the semiconductor substrate; a well region of the 2 nd conductivity type formed on the 1 st main surface side in contact with the semiconductor layer of the 1 st conductivity type; a 1 st gate electrode and a 2 nd gate electrode which are in contact with the 1 st conductivity type semiconductor layer and the 2 nd conductivity type well region with a gate insulating film interposed therebetween, and which are formed adjacent to each other with the 2 nd conductivity type well region interposed therebetween; an emitter region of a 1 st conductivity type formed on the 1 st main surface side of the well region of the 2 nd conductivity type; a 2 nd conductive type power supply region penetrating the 1 st conductive type emitter region and electrically connected to the 2 nd conductive type well region; an emitter electrode electrically connected to the well region of the 2 nd conductivity type via the power supply region of the 2 nd conductivity type; a collector layer of a 2 nd conductivity type which is in contact with the semiconductor layer of the 1 st conductivity type and is formed on a 2 nd principal surface side of the semiconductor substrate on a side opposite to the 1 st principal surface side; and a collector electrode electrically connected to the collector layer of the 2 nd conductivity type, wherein a gap between the 1 st gate electrode and the 2 nd gate electrode is narrower than a gap between the 1 st gate electrode and the 2 nd gate electrode and another adjacent gate electrode, the 1 st gate electrode and the 2 nd gate electrode are each electrically connected to one of a switching gate wiring or a carrier control gate wiring, and the number of gate electrodes connected to the carrier control gate wiring is larger than the number of gate electrodes connected to the switching gate wiring.
According to the present invention, by improving controllability of conductivity modulation in an IGBT, a trade-off relationship between on-voltage and off-loss can be improved while achieving low on-loss and low switching loss.
In addition, this makes it possible to realize an IGBT capable of reducing power consumption and a power conversion device using the IGBT.
Problems, structures, and effects other than those described above will become apparent from the following description of the embodiments.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor device according to
Fig. 2 is a diagram conceptually showing the carrier distribution in the on state of the IGBT when a voltage equal to or higher than the threshold voltage is applied to the GS gate and the GC gate in the semiconductor device according to
Fig. 3 is a diagram conceptually showing the carrier distribution in the on state of the IGBT in the semiconductor device according to
Fig. 4 is a diagram showing drive waveforms at the time of turn-off of the semiconductor device applied to
Fig. 5 is a graph showing the correlation between the turn-off loss of the IGBT obtained by the present invention and the ratio of the number of channels generated by the GC gate to the number of channels generated by the GS gate.
Fig. 6A is a cross-sectional view of a semiconductor device according to
Fig. 6B is a plan configuration view of a semiconductor device of
Fig. 7A is a cross-sectional view of a semiconductor device according to a modification of
Fig. 7B is a plan view of a semiconductor device according to a modification of
Fig. 8 is a cross-sectional view of a semiconductor device according to
Fig. 9A is a diagram showing a feedback capacitance of the semiconductor device according to
Fig. 9B is a diagram showing the feedback capacitance that the semiconductor device of
Fig. 10 is a sectional view of a semiconductor device according to a modification of
Fig. 11 is a diagram showing drive signals of the semiconductor device of
Fig. 12 is a diagram showing drive signals of a semiconductor device according to a modification (modification 1) of
Fig. 13 is a diagram showing drive signals of the semiconductor device according to the modification (modification 1) of
Fig. 14 is a diagram showing drive signals of a semiconductor device according to another modification (modification 2) of
Fig. 15 is a diagram showing drive signals of a semiconductor device according to another modification (modification 2) of
Fig. 16 is a diagram showing a circuit configuration of a power conversion device according to
Fig. 17 is a diagram showing a circuit configuration of a power conversion device according to a modification (modification 1) of
Fig. 18 is a diagram showing a circuit configuration of a power conversion device according to another modification (modification 2) of
Fig. 19 is a diagram showing a circuit configuration of a power conversion device according to another modification (modification 3) of
Fig. 20 is a diagram showing a circuit configuration of a power conversion device to which the related art is applied.
Fig. 21 is a cross-sectional view of a semiconductor device to which the conventional technique described in
Fig. 22 is a cross-sectional view of a semiconductor device to which the conventional technique described in
(symbol description)
1: an n-type drift layer; 2: a p-type well layer; 3: an n-type emitter layer; 4: a p-type collector layer; 5: a gate insulating film (oxide film); 6: an insulated gate electrode GS (GS gate); 7: an emitter electrode; 8: a collector electrode; 12: a p-type power supply layer; 13: an insulated gate electrode GC (GC gate); 15: a p-type floating layer or an n-type drift layer; 16: a thick insulating film; 18: (drive signal of) the GS gate; 19: (drive signal of) GC gate; 20: the collector-emitter voltage (waveform) of the IGBT; 21: collector current (waveform) of the IGBT; 22: the current-voltage product of the IGBT; 23: on period (of the IGBT); 24: the period immediately before expiration; 25: a cutoff period; 26: a threshold voltage (where an inversion layer is formed in the p-type well layer 2); 27: a supply voltage; 28: conventional IGBTs; 29: the IGBT to which embodiment 1 (example 1) of the present invention is applied; 30: the rising amount of the conduction loss (in the period 24 immediately before the off state); 31: turn-off switching losses (during turn-off period 25); 32: aggregate cutoff losses; 40: GS grid wiring; 41: GC gate wiring; 42: a contact layer; 43: a feedback capacitance (of the trench gate type IGBT); 44: feedback capacitance (of side gate type IGBT); 45: a non-conducting period; 46: a switch-on period; 47: the waveform of the IGBT to which embodiment 4 (fig. 11) of the present invention is applied; 48: the waveform of the IGBT to which the first modification (fig. 12) of embodiment 4 of the present invention is applied; 49: a waveform of an IGBT to which a second modification (fig. 14) of embodiment 4 of the present invention is applied; 64: a control circuit; 66: a diode; 67: a drive circuit (that drives the IGBT); 68: an inductive load; 69: a source of direct current voltage (power); 70: an IGBT; 71: an insulated gate (terminal) of the IGBT 70; 72: a diode (connected anti-parallel to the IGBT 70); 76: an IGBT (of the invention); 77: the GS gate terminal (of the IGBT76 of the invention); 78: a GC gate terminal (of the IGBT76 of the invention); 81: a Schottky barrier diode; 82: an insulated gate controlled diode; 83: an insulated gate terminal (of an insulated gate control type diode); 84: an insulated gate controlled diode (composed of 2 insulated gates); 85: a first insulated-gate terminal (of an insulated-gate control type diode composed of 2 insulated gates); 86: a second insulated-gate terminal (of an insulated-gate control type diode composed of 2 insulated gates); 91: a gate electrode (insulated gate electrode G1); 92: a gate electrode (insulated gate electrode G2); 93: a p-type floating layer; 94: conductivity modulation; 100: an IGBT (according to embodiment 1 of the present invention); 200: an IGBT (according to embodiment 2 of the present invention); 201: an IGBT (according to a modification of embodiment 2 of the present invention); 300: an IGBT (according to embodiment 3 of the present invention); 301: an IGBT (according to a modification of embodiment 3 of the present invention); 400: a method for driving an IGBT (according to embodiment 4 of the present invention); 401: a method for driving an IGBT (according to a first modification of embodiment 4 of the present invention); 402: a method for driving an IGBT (according to a second modification of embodiment 4 of the present invention); 500: a power conversion device (according to embodiment 5 of the present invention); 501: a power conversion device (according to a first modification of embodiment 5 of the present invention); 502: a power conversion device (according to a second modification of embodiment 5 of the present invention); 503: a power conversion device (according to a third modification of embodiment 5 of the present invention).
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and the detailed description of the overlapping portions will be omitted. Note that the expression "n" or "n" in the drawings indicates that the semiconductor layer is n-type, and indicates that the impurity concentration is relatively high in this order. Similarly, the expression p-, p-indicates that the semiconductor layer is p-type, and indicates that the impurity concentration is relatively high in this order.
- 上一篇：一种医用注射器针头装配设备
- 下一篇：半导体装置及半导体装置的制造方法