阅读说明：本技术 一种可同时支持多套Cache数据私有段动态设置的方法 (Method capable of simultaneously supporting dynamic setting of multiple sets of Cache data private sections ) 是由 陈芳园 过锋 高红光 吴珊 陈庆强 郝子宇 孙红辉 于 2019-09-06 设计创作，主要内容包括：本发明公开了一种可同时支持多套Cache数据私有段动态设置的方法,包括步骤S1、确定目标数据Cache中需要设置的n套私有段数据位置地址,为各个私有段数据设置相对应的n套第一私有段寄存器；S2、在目标数据Cache中分别设置与每套私有段数据相对应的第一比较器、第二比较器；S3、按一定规则对需要写入Cache中的数据行进行判断,来确定其是否具有“私有段标准”；S4、确认符合“私有段标准”后,在指令Cache中生成私有段设置指令；S5、设置指令发射规则判断器,对指令Cache内的指令执行情况进行判断；S6、确认在指令Cache内排列在私有段设置指令前的指令全部执行结束后,开始执行私有段设置指令,将需要写入Cache中的数据行写入与对应的私有段位置地址相联的数据Cache中。(The invention discloses a method capable of simultaneously supporting dynamic setting of multiple sets of private sections of Cache data, which comprises the steps of S1, determining position addresses of n sets of private section data to be set in a target data Cache, and setting n sets of corresponding first private section registers for each private section data; s2, respectively setting a first comparator and a second comparator corresponding to each set of private segment data in the target data Cache; s3, judging the data line needed to be written into the Cache according to a certain rule to determine whether the data line has a 'private section standard'; s4, generating a private section setting instruction in the instruction Cache after confirming that the private section standard is met; s5, setting an instruction emission rule judger, and judging the instruction execution condition in the instruction Cache; and S6, after confirming that all the instructions arranged in the instruction Cache before the private section setting instruction are executed, starting to execute the private section setting instruction, and writing the data line required to be written into the Cache into the data Cache connected with the position address of the corresponding private section.)

1. A method for supporting dynamic setting of multiple sets of Cache data private sections simultaneously is characterized in that data of the multiple sets of Cache data private sections can be dynamically set, and the logic sequence of set hardware during operation can be guaranteed to be correct, and the method comprises the following steps: s1, determining n sets of private segment data position addresses required to be set in the target data Cache, and setting corresponding n sets of first private segment registers for each private segment data; s2, respectively setting a first comparator and a second comparator corresponding to each set of private segment data in the target data Cache; s3, judging the data line needed to be written into the Cache according to a certain rule to determine whether the data line has a 'private section standard'; s4, generating a private section setting instruction in the instruction Cache after confirming that the data line needing to be written in the Cache meets the private section standard; s5, setting a specific instruction emission rule judger, and further judging the instruction execution condition in the instruction Cache; and S6, after confirming that all the instructions arranged in the instruction Cache before the private section setting instruction are executed, starting to execute the private section setting instruction, and writing the data line required to be written into the Cache into the data Cache connected with the position address of the corresponding private section.

2. The method as claimed in claim 1, wherein in step S1, each set of first private segment registers includes a private segment start address register and a private segment end address register.

3. The method as claimed in claim 1, wherein in step S2, the first comparator and the second comparator are comparators for accessing address and starting address of the private segment, and comparators for accessing address and ending address of the private segment, respectively.

4. The method for supporting dynamic setting of multiple sets of private sections of Cache data simultaneously according to claim 1, wherein step S3 specifically comprises: s31, acquiring the access address of the data line needing to be written into the Cache; s32, judging whether the access address of the data line needing to be written into the Cache exists or not; s33, when determining that the memory access address of the data line needing to be written into the Cache exists, sending the memory access address into the first comparator and the second comparator of the corresponding private segment data for comparison; s34, when determining that the access address of the data line needing to be written into the Cache is corresponding to the start address and the end address of the corresponding private segment data, judging whether a private segment identifier which is the same as the private segment of the data Cache exists in the target data line, wherein the private segment identifier is a character identifier stored in the valid bit of the target data line; s35, when the existence of the private segment identification of the target data line is determined, the data line needing to be written into the Cache is confirmed to accord with the private segment standard.

5. The method for supporting dynamic setting of multiple sets of Cache data private sections simultaneously as claimed in claim 4, wherein step S32 "determining whether the memory access address of the data line to be written into the Cache exists" specifically includes: reading out the contents in Tag fields Tag of data lines needing to be written in the Cache at the same time; and comparing the content of the Tag with the high end of the address, and if the content of the Tag is matched with the high end of the address, indicating that the DCache (data Cache) is hit and the access address needing to be written in the data exists.

6. The method for supporting dynamic setting of multiple sets of private sections of Cache data simultaneously according to claim 4, wherein: the private segment identifier of the data Cache in step S34 may be dynamically set by the Cache controller.

7. The method for supporting dynamic setting of multiple sets of private sections of Cache data simultaneously according to claim 1, wherein: and when the data line written into the private section of the data Cache reaches the critical value of the file data in the Cache, replacing the original Cache data with all the file data within the critical value in the Cache.

Technical Field

The invention relates to the field of computer storage systems, in particular to a method capable of simultaneously supporting dynamic setting of multiple sets of Cache data private sections.

Background

In the development process of computer technology, the access speed of a main memory is much slower than the processing speed of a CPU (processor), so that the high-speed processing capability of the CPU cannot be fully exerted, and the working efficiency of the whole computer system is influenced. To mitigate the speed mismatch between the CPU and main memory, one of the more common approaches is to cache using caches at the memory level.

At present, the size of a cache is one of important indexes of a CPU, and the structure and the size of the cache have great influence on the speed of the CPU. In short, the cache is used for storing some commonly used or to-be-used data or instructions, and when the data or instructions are needed, the data or instructions are directly read from the cache, so that the data or instructions are much faster than the data or instructions read from a memory or even a hard disk, and the processing speed of the cpu can be greatly improved.

While data cache (Dcache) is an important component of the cache of a computer storage system, since data is stored in Dcache, the value of Dcache can change according to different instruction operations. Therefore, the storage efficiency and the main memory write-back efficiency of the computer storage system are all decisively influenced. The current data Cache design can support the setting of private sections so as to ensure the non-sharing of private section data and the elimination of full main memory blocks. However, there are some problems with the current private segment setup. Firstly, the current private section of the data Cache is statically set, the private section is set before the program starts to run, the private section cannot be changed in the running process of the program, and the changed private section is not supported. Secondly, the current data Cache setting generally only supports one set of private section setting, and the discontinuous private sections cannot be simultaneously supported.

In addition, after the private section is dynamically set, most of the existing controllers of the data Cache lack the judgment and execution capabilities of the stored instruction data pipeline for out-of-order transmission and out-of-order execution, so that the judgment result of the private section of the Cache line can be influenced when the setting of an illegal private section is supported.

Therefore, a method for dynamically setting multiple sets of private sections of Cache data, which can support the setting of illegal private sections, can ensure the judgment efficiency of the private sections of Cache lines, and can ensure the correctness of the logic sequence of data before the private sections are set, the validity period of the private sections and the data after the private sections are cancelled in the operation process, becomes necessary.

Disclosure of Invention

In order to solve the problems, the technical scheme adopted by the invention is to provide a method capable of simultaneously supporting dynamic setting of multiple sets of Cache data private sections, the method is used for distinguishing and writing data of the private sections of the data Cache, the data of the multiple sets of Cache data private sections can be dynamically set, and the logical sequence of the set hardware during operation can be ensured to be correct.

The method capable of simultaneously supporting dynamic setting of multiple sets of Cache data private sections comprises the following steps: s1, determining n sets of private segment data position addresses required to be set in the target data Cache, and setting corresponding n sets of first private segment registers for each private segment data; s2, respectively setting a first comparator and a second comparator corresponding to each set of private segment data in the target data Cache; s3, judging the data line needed to be written into the Cache according to a certain rule to determine whether the data line has a 'private section standard'; s4, generating a private section setting instruction in the instruction Cache after confirming that the data line needing to be written in the Cache meets the private section standard; s5, setting a specific instruction emission rule judger, and further judging the instruction execution condition in the instruction Cache; and S6, after confirming that all the instructions arranged in the instruction Cache before the private section setting instruction are executed, starting to execute the private section setting instruction, and writing the data line required to be written into the Cache into the data Cache connected with the position address of the corresponding private section.

Further, in step S1, each set of first private segment registers includes a private segment start address register and a private segment end address register.

Further, in step S2, the first comparator and the second comparator are a comparator of a memory access address and a private segment start address, and a comparator of a memory access address and a private segment end address, respectively.

Further, step S3 specifically includes: s31, acquiring the access address of the data line needing to be written into the Cache; s32, judging whether the access address of the data line needing to be written into the Cache exists or not; s33, when determining that the memory access address of the data line needing to be written into the Cache exists, sending the memory access address into the first comparator and the second comparator of the corresponding private segment data for comparison; s34, when determining that the access address of the data line needing to be written into the Cache is corresponding to the start address and the end address of the corresponding private segment data, judging whether a private segment identifier which is the same as the private segment of the data Cache exists in the target data line, wherein the private segment identifier is a character identifier stored in the valid bit of the target data line; s35, when the existence of the private segment identification of the target data line is determined, the data line needing to be written into the Cache is confirmed to accord with the private segment standard.

Further, step S32, "judging whether the access address of the data line that needs to be written into the Cache exists" specifically includes: reading out the contents in a Tag field (Tag) of a data line required to be written in the Cache at the same time; and comparing the content of the Tag with the high end of the address, and if the content of the Tag is matched with the high end of the address, indicating that the DCache (data Cache) is hit and the access address needing to be written in the data exists.

Further, the private segment identifier of the data Cache in step S34 may be dynamically set by the Cache controller.

Further, when the data line written into the private section of the data Cache reaches the critical value of the file data in the Cache, replacing the original Cache data with all the file data within the critical value in the Cache.

The invention can realize the simultaneous setting of a plurality of sets of private sections by the DCache controller by setting the corresponding section register for each set of private section; according to the invention, the address of the data line needing to be written into the private section of the data Cache is judged through the first comparator and the second comparator, and then the private section standard judgment is carried out on the data line by matching with the private section identification arranged on the data Cache, so that the correctness of the logic sequence of the data written into the data Cache can be ensured, and the correctness of the data logic of out-of-order emission and out-of-order execution of the written data can be ensured under the condition of dynamic configuration. The invention confirms that all the instructions arranged in the instruction Cache before the private section setting instruction are completely executed by setting the specific instruction emission rule judger, thereby preventing the occurrence of logic errors when writing data into the private ends of a plurality of sets of Cache data.

Drawings

FIG. 1 is a general flowchart of a method for supporting dynamic setting of multiple sets of private sections of Cache data simultaneously according to the present invention;

fig. 2 is a flowchart of the substep of step S3 of the method for supporting dynamic setting of multiple sets of private sections of Cache data simultaneously according to the present invention.

Detailed Description

In order to more clearly illustrate the embodiments of the present invention and/or the technical solutions in the prior art, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.