阅读说明：本技术 一种绝缘栅双极型晶体管及其制备方法 (Insulated gate bipolar transistor and preparation method thereof ) 是由 不公告发明人 于 2019-10-22 设计创作，主要内容包括：本发明提供了一种绝缘栅双极型晶体管及其制作方法,包括：通过设置元胞结构和哑元胞结构,哑元胞结构的多晶硅栅极连接到发射极电极,使发射极的接触面积面大,显著降低了IGBT的导通压降,寄生氧化物电容将显著减小；在这种情况下,P集电极空穴可以很容易地流到发射极电极；n型空穴阻挡层位于P阱下方,以避免空穴流向发射极；这种结构将空穴存储在虚拟沟槽栅单元下,在不牺牲任何IGBT性能的情况下,寄生电容会显著降低,进而缩短逆变器的死区时间。(The invention provides an insulated gate bipolar transistor and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: by arranging the cellular structure and the dummy cellular structure, the polycrystalline silicon grid of the dummy cellular structure is connected to the emitter electrode, so that the contact area of the emitter is large, the conduction voltage drop of the IGBT is remarkably reduced, and the parasitic oxide capacitance is remarkably reduced; in this case, the P collector holes can easily flow to the emitter electrode; the n-type hole blocking layer is positioned below the P trap to prevent holes from flowing to the emitter; the structure stores holes under the virtual trench gate unit, and under the condition of not sacrificing the performance of any IGBT, the parasitic capacitance can be obviously reduced, so that the dead time of the inverter is shortened.)

1. An insulated gate bipolar transistor, comprising: the unit cell structure of the insulated gate bipolar transistor comprises a metal emitter, an N + emitter region, a P + base region, a P trap, an oxide layer, an insulating layer, a polysilicon gate, an N drift region, an N-type electric field stop layer, a P collector region and a metal collector;

the metal collector, the P collector region, the N-type electric field stop layer and the N drift region are arranged from the bottom layer to the upper layer in sequence; the N drift region is positioned above the N-type electric field stopping layer, the polycrystalline silicon grid electrode is contacted with the oxide layer, the metal emitter electrode is respectively contacted with the P + base region, the insulating layer and part of the N + emitter region on the surface of the cell, the insulating layer is connected with the oxide layer and part of the N + emitter region, and the polycrystalline silicon grid electrode and the oxide layer form a groove grid structure;

the insulated gate bipolar transistor also comprises a dummy cell structure;

the dummy cell structure comprises a metal emitter, a doping region, a P well, an oxidation layer, an insulation layer, a polysilicon gate, an N drift region, an N-type electric field stop layer, a P collector region and a metal collector, wherein the doping region is positioned on the surface of the P well and is directly connected to the emitter electrode;

the metal collector, the P collector region, the N-type electric field stop layer and the N drift region are arranged from the bottom layer to the upper layer in sequence; the N drift region is positioned above the N-type electric field stopping layer, the polysilicon gate is in contact with the oxide layer, the metal emitter is in contact with part of the doped region and the insulating layer on the surface of the cell, the insulating layer is in contact with the oxide layer and part of the doped region, and the polysilicon gate and the oxide layer form a virtual groove gate structure.

2. The IGBT of claim 1, wherein an n-type hole blocking layer is formed under the P-well.

3. The igbt of claim 1, wherein the ratio of the number of dummy cells to the number of normal cells is 3:1 or 5: 1.

4. The igbt of claim 1, wherein the polysilicon gates of the dummy cells are connected to emitter electrodes.

5. The igbt of claim 1, wherein the dummy cells have short connections between polysilicon gates.

6. The igbt of claim 1, wherein the cell structure has a plurality of polysilicon islands in the trench, the plurality of polysilicon islands being connected to the metal emitter.

7. An insulated gate bipolar transistor according to claim 6 wherein one of the polysilicon islands is connected to the n + emitter region.

8. A manufacturing method of an insulated gate bipolar transistor, which is used for manufacturing the insulated gate bipolar transistor as claimed in claims 1-7, and is characterized by comprising the following steps:

p-base diffusion, trench etching, oxidation formation and doped polysilicon deposition processes; etching the polysilicon, and then performing an n + emitter forming process; followed by oxidation formation; a second polysilicon deposition and polysilicon is etched out of the bottom of the n + emitter diffusion region and SiO2 is deposited using HDP deposition.

Technical Field

The invention belongs to the technical field of semiconductor power device design, particularly relates to an insulated gate bipolar transistor, and further relates to a preparation method of the insulated gate bipolar transistor.

Background

An insulated-Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a BJT (Bipolar Transistor) and an MOS (insulated Gate field effect Transistor), and has the advantages of both high input impedance of the MOSFET and low on-state voltage drop of the GTR. Turning on the IGBT by providing a transistor base current; conversely, if a reverse gate voltage is applied, the channel is eliminated and the IGBT is turned off by the reverse gate current. An important parameter affecting the use of IGBTs as power conversion devices such as inverters and the like is the dead time. Because power devices such as an IGBT (insulated gate bipolar transistor) have certain junction capacitance, the on-off delay phenomenon of the devices can be caused, and in order to avoid the direct connection of bridge arms of the IGBT, the so-called 'interlock delay time', or generally called 'dead time', is generally recommended to be added into a control strategy. If the dead time is set too short, bridge circuits are directly connected, and a device is short-circuited and fails; the dead time is set too much, which causes signal waveform distortion, the output efficiency is seriously reduced, and the stability of the induction motor is also adversely affected.

Therefore, it is necessary to shorten the dead time of the inverter as much as possible without bridge breakdown, and to ensure the safety and stability of the system and high conversion efficiency.

Disclosure of Invention

The invention aims to solve the technical problem of how to shorten the dead time of an inverter as much as possible without bridge circuit breakdown on the premise of ensuring the safety and stability of a system and the conversion efficiency, and provides a trench gate IGBT semiconductor device and a preparation method thereof.

In order to achieve the technical purpose, the invention adopts the following method:

an insulated gate bipolar transistor, comprising: the unit cell structure of the insulated gate bipolar transistor comprises a metal emitter, an N + emitter region, a P + base region, a P trap, an oxide layer, an insulating layer, a polysilicon gate, an N drift region, an N-type electric field stop layer, a P collector region and a metal collector;

the metal collector, the P collector region, the N-type electric field stop layer and the N drift region are arranged from the bottom layer to the upper layer in sequence; the N drift region is positioned above the N-type electric field stopping layer, the polycrystalline silicon grid electrode is contacted with the oxide layer, the metal emitter electrode is respectively contacted with the P + base region, the insulating layer and part of the N + emitter region on the surface of the cell, the insulating layer is connected with the oxide layer and part of the N + emitter region, and the polycrystalline silicon grid electrode and the oxide layer form a groove grid structure;

the insulated gate bipolar transistor also comprises a dummy cell structure;

the dummy cell structure comprises a metal emitter, a doping region, a P well, an oxidation layer, an insulation layer, a polysilicon gate, an N drift region, an N-type electric field stop layer, a P collector region and a metal collector, wherein the doping region is arranged on the surface of the P well and is directly connected to the emitter electrode;

the metal collector, the P collector region, the N-type electric field stop layer and the N drift region are arranged from the bottom layer to the upper layer in sequence; the N drift region is positioned above the N-type electric field stopping layer, the polysilicon gate is in contact with the oxide layer, the metal emitter is in contact with part of the doped region and the insulating layer on the surface of the cell, the insulating layer is in contact with the oxide layer and part of the doped region, and the polysilicon gate and the oxide layer form a virtual groove gate structure.

Further, an n-type hole blocking layer is formed on the lower surface of the P well.

Further, the number ratio of the dummy cells to the normal cells is 3:1 or 5: 1.

Further, an insulated gate bipolar transistor according to claim 1, wherein the polysilicon gate of the dummy cell is connected to the emitter electrode.

Further, short circuit is formed between the polycrystalline silicon gates of the dummy cells.

Further, a plurality of polysilicon islands are arranged in the grooves of the cellular structure, and the polysilicon islands are connected to the emitter electrode.

Further, one of the polysilicon islands is connected to the n + emitter region.

The invention also provides a manufacturing method of the trench gate IGBT semiconductor device, which is used for manufacturing the trench gate IGBT semiconductor device provided by the technical scheme and is characterized by comprising the following steps:

p-base diffusion, trench etching, oxidation formation and doped polysilicon deposition processes; etching the polysilicon, and then performing an n + emitter forming process; followed by oxidation formation; a second polysilicon deposition and polysilicon is etched out of the bottom of the n + emitter diffusion region and SiO2 is deposited using HDP deposition.

The beneficial technical effects are as follows:

according to the invention, the cellular structure and the dummy cellular structure are arranged, so that the contact area of the emitter is increased, the conduction voltage drop of the IGBT is obviously reduced, and the parasitic capacitance is obviously reduced;

the n-type hole blocking layer is positioned below the P trap to prevent holes from flowing to the emitter; the structure stores the holes under the virtual trench gate unit, so that the parasitic capacitance can be obviously reduced under the condition of not sacrificing the performance of any IGBT, and further the dead time of the inverter is shortened;

the polycrystalline silicon grid electrode and the emitter electrode of the dummy cell structure are short-circuited, and the parasitic oxide capacitance is remarkably reduced; but in this case, the P collector holes can easily flow to the emitter electrode;

the polycrystalline silicon grid of the cellular structure is formed by a plurality of polycrystalline silicon islands, parasitic capacitance can be greatly reduced, one polycrystalline silicon grid is connected with an emitter electrode, and the CGC capacitance is very low due to the special structure.

Drawings

FIG. 1 is a typical configuration of a voltage source inverter;

FIG. 2 defines dead time with logic signals, IGBT driver output, and IGBT collector voltage;

FIG. 3 illustrates an IGBT inductive load switching circuit and switching waveforms;

fig. 4IGBT parasitic capacitance element and gate charge characteristics;

FIG. 5 is a component of the parasitic capacitance of a conventional trench gate IGBT;

FIG. 6 is a schematic diagram of a conventional IGBT semiconductor device cell structure;

fig. 7 is a schematic diagram of a cell structure of an IGBT semiconductor device according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a dummy cell structure of an IGBT semiconductor device according to an embodiment of the present invention;

figure 9 is a schematic diagram of a polysilicon gate structure provided in accordance with an embodiment of the present invention;

figure 10 is a schematic diagram of a polysilicon gate structure provided in accordance with an embodiment of the present invention;

FIG. 11 is a schematic illustration of a method of making an embodiment of the present invention;

the labels in the figure are: 1: a collector electrode; 2: a P collector region; 3: n buffer layer; 4: an N-substrate; 5: a P-doped region; 6: an n + doped region; 7: a polysilicon gate; 8: an oxide layer; 9: an emitter; 101, a metal collector; 102: a P collector region; 103: an N-type electric field stop layer; 104: an N drift region; 105: a polysilicon gate; 106: an oxide layer; 107: a P well; 108: a P + base region; 109: an n + emitter region; 110: an insulating layer; 111: a metal emitter; 112: an n-type hole blocking layer; 113: and doping the region.

Detailed Description

The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.

In pwm inverters such as the industrial motor control and ev/hev applications shown in fig. 1, the pwm signal with the dead zone is typically used to protect the legs of the IGBTs in the inverter from short circuits. The dead time causes distortion of the output voltage waveform, interrupting the high carrier frequency drive of the inverter. Power inverter systems are used in many applications today. In particular in the context of battery powered vehicles, it is becoming increasingly important to improve electromagnetic compatibility and reduce power consumption.

Fig. 2 shows the definition of dead time, including logic signals, each ARM driver output, and the VCE voltage of the IGBTs.

In short, it can be said that the definition is as follows,

dead time logic set: td

Actual dead time of VCE: TDA

T1: output delay time between on signal and on drive voltage

T2: output delay time between turning on drive signal and turning on

t 3: output delay time between shutdown signal and shutdown driving voltage

t 4: output delay time between off drive and off

The actual dead time between the logic signal of igbt and vce is given by,

TDA＝TD–(T3+T4)+(T1+T2)

this formula considers that the dead time is determined by the delay time of the drive signal and the delay time of igbt. Figure 3 shows the test and on-off waveforms, ton and toff, for an igbt inductive load switching circuit.

With the prolonging of time, one igbt is always turned off first, and the other igbt is turned off after the dead time is over, so that the bridge arm breakdown caused by asymmetric on-off time of the igbt device is avoided.

To avoid the above problem, it is necessary to reduce the switching time of igbt, which is mainly td (off) and td (on), and the delay time is caused by parasitic capacitance, cge, cgc, and cae, as shown in fig. 4 and 5. From the gate charge characteristics of fig. 4 and 5, the parasitic capacitances cgc and cge should be mainly reduced.

The IGBT chip is composed of tens of thousands of cells (cells), and is manufactured by a large-scale integrated circuit technology and a power semiconductor device technology in a process, and each cell structure is as shown in fig. 6, and is composed of three parts: front side MOS structure, body structure and back side collector (this is common general knowledge and is described a little).

(1) The body structure of present IGBT is mostly soft punch-through structure, and the advantage of break-through and non-punch-through structure body has been synthesized to this structure, when promoting chip application power grade, but does not make on-state pressure drop and chip substrate thickness increase with the proportion, through control hole injection efficiency, makes IGBT obtain positive temperature coefficient moreover.

(2) The collector region structure of the IGBT is associated with the gain of the PNP transistor, so that the forward voltage drop and the turn-off loss are greatly influenced.

(3) The front MOS structure of the IGBT comprises a grid electrode and an emitter region, the grid electrode structure comprises a plane grid and a groove grid, the groove grid structure is adopted, the groove grid structure is a longitudinal structure, the influence of an RJFET in on-resistance is eliminated, the improvement of cell density is facilitated, and power consumption is reduced.

The present invention primarily contemplates reducing parasitic capacitance, and an embodiment is shown in FIG. 7.

The invention will be further explained with reference to the drawings.