阅读说明：本技术 一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统 (Inversion driving system with ultralow switching power consumption and ultralow output end electromagnetic interference ) 是由 周衍 于 2019-11-27 设计创作，主要内容包括：本发明公开了一种超低开关功耗、超低输出端电磁干扰的逆变驱动系统,包括多相逆变驱动系统,每相逆变驱动系统为独立系统,且均包括以下部分：反馈控制单元、比较控制单元和功率开关电路。本发明在通过功率开关器件与电感电容输出电路的组合,使功率开关电路工作于近似于边界传到模式BCM的状态,在输出端保持低频正弦电压电流输出的同时,使电感电流在每个高频开关周期内由反向的切换电流增长到峰值电流再降低到反向的切换电流。从原理上提供低高次谐波成分的正弦电压电路输出,同时由于电感在每个开关周期的开始和结束时电感电流与电感电流的平均值相反,通过此电流可实现功率开关器件的ZVS开关,从而实现了低开关损耗和低输出端高频电磁干扰。(The invention discloses an inversion driving system with ultra-low switching power consumption and ultra-low output end electromagnetic interference, which comprises a multi-phase inversion driving system, wherein each phase of inversion driving system is an independent system and comprises the following parts: feedback control unit, comparison control unit and power switch circuit. The invention makes the power switch circuit work in a state of being similar to boundary transmission to a mode BCM through the combination of the power switch device and the inductance capacitance output circuit, keeps the output of low-frequency sinusoidal voltage current at the output end, and simultaneously makes the inductance current increase from reverse switching current to peak current and then decrease to reverse switching current in each high-frequency switching period. The sine voltage circuit output with low high-order harmonic components is provided in principle, and meanwhile, as the inductance current is opposite to the average value of the inductance current at the beginning and the end of each switching period, the ZVS switching of the power switching device can be realized through the inductance current, so that the low switching loss and the low output end high-frequency electromagnetic interference are realized.)

1. The utility model provides an ultra-low switching power consumption, ultra-low output electromagnetic interference's contravariant actuating system which characterized in that, includes heterogeneous contravariant actuating system, and every looks contravariant actuating system is independent system, and every looks contravariant actuating system's output is the alternating current waveform of required output, and every looks contravariant actuating system all includes following part: the device comprises a feedback control unit, a comparison control unit and a power switch circuit;

each feedback control unit, through input signals: external input signal u_sin(t) output terminal voltage signal u_out(t) output terminal current signal i_out(t) to calculate the output set current i required for that phase_set(t) and setting the output of the phase required output as a current i_set(t) a comparison control unit outputting to the phase inversion driving system;

each comparison control unit has its input signal including output setting current i output by feedback control unit of the phase inversion driving system_set(t) and real-time measurement signal of inductor current i_L(t); setting a current i by an output from a feedback control unit_set(t) calculating the inductance peak current I required by switching of the switch state according to the structural characteristics of the power switch circuit_peak(t) and an intermediate comparative current I_comp(t) setting a switching current I for the zero-voltage switch_constAnd is in parallel with the real-time measured inductor current i_L(t) comparing, determining the corresponding switch state of a switch device in the power switch circuit through logic calculation, and outputting a switch state signal to the power switch circuit of the phase inversion driving system;

the input signal of each power switch circuit is a switch state signal output by a comparison control unit of the phase inversion driving system; the output signal is the voltage signal u at the output terminal_out(t) output terminal current signal i_out(t) and real-time measurement signal of inductor current i_L(t); the inductive current real-time measurement signal i_L(t) feeding back to theA comparison control unit of the phase inversion driving system, the output end voltage signal u_out(t) and an output terminal current signal i_out(t) is fed back to a feedback control unit of the phase inversion driving system.

2. The inverter driving system with ultra-low switching power consumption and ultra-low output electromagnetic interference as claimed in claim 1, wherein the power switch circuit is a half-bridge power switch circuit or a full-bridge power switch circuit according to application requirements.

3. The inverter driving system of claim 2, wherein the power switch circuits are half-bridge power switch circuits, each of which comprises a high-side switch device SW1, a low-side switch device SW2, auxiliary switch capacitors C1 and C2 connected in parallel with the high-side switch device SW1 and the low-side switch device SW2, an inductor L1, and output capacitors C3 and C4; positive and negative ends + U of DC power supply input end of each half-bridge power switch circuit_inand-U_inThe high-side switching device SW1 and the low-side switching device SW2 are connected in series between the positive end and the negative end of the input end of the direct-current power supply to form a half-bridge switching circuit, an inductance coil L1 is connected between the output end of the half-bridge switching circuit and output capacitors C3 and C4, and output capacitors C3 and C4 are connected in series between the positive end and the negative end of the input end of the direct-current power supply;

both the high-side switching device SW1 and the low-side switching device SW2 are controlled by zero-voltage switching (ZVS) gate drivers.

4. The inverter driving system according to claim 3, wherein the input signal of each comparison control unit further comprises an output terminal voltage signal u_out(t)；

Each half-bridge power switch circuit also comprises a plurality of intermediate direct-current power supply input ends, and the intermediate direct-current power supply input ends are connected with a plurality of intermediate direct-current power supplies; middle straightThe input voltage of the input end of the current power supply is in + U_inand-U_inEach half-bridge power switch circuit further comprises a plurality of bidirectional cut-off type switch devices SWM and corresponding auxiliary switch capacitors CM, each middle direct-current power supply input end is connected with one end of the high-side switch device SW1, one end of the low-side switch device SW2 and one end of the inductor L1 through one bidirectional cut-off type switch device SWM, and each bidirectional cut-off type switch device SWM is connected with one auxiliary switch capacitor CM in parallel; the bidirectional turn-off switching device SWM is controlled by a Zero Voltage Switching (ZVS) gate driver.

5. The system of claim 2, wherein the power switch circuits are full bridge power switch circuits, each full bridge power switch circuit comprises a switch device SW1, SW2, SW3, SW4, SW5, an auxiliary switch capacitor C1, C2, C3, C4, C5 connected in parallel with the switch device SW1, SW2, SW3, SW4, SW5 respectively, an inductor L1, and an output capacitor C6, C7; the switching devices SW1 and SW2 are connected in series between the positive end and the negative end of the input end of the direct-current power supply, and the switching devices SW3 and SW4 are connected in series between the positive end and the negative end of the input end of the direct-current power supply to form a left half bridge and a right half bridge in a full-bridge switching circuit respectively; positive and negative ends + U of direct-current power supply input end of full-bridge power switch circuit_inand-U_inThe inductance coil L1 is connected between the output ends of the half-bridges at the two sides in the full-bridge switching circuit; the switching device SW5 of the output end is connected between the output capacitors C6 and C7 and the output end of the right half bridge in the full bridge switching circuit; the output capacitors C6 and C7 are connected in series between the positive end and the negative end of the input end of the direct-current power supply;

switching devices SW1, SW2, SW3, SW4, SW5 are all controlled by Zero Voltage Switching (ZVS) gate drivers.

6. The inverter driving system with ultra-low switching power consumption and ultra-low output electromagnetic interference of claim 5, wherein when the full-bridge power switch circuit does not need to support the boost output, the switch device SW5 is a bidirectional cut-off power switch device, and the switch devices SW1, SW2, SW3 and SW4 are all unidirectional cut-off power switch devices; when the full-bridge power switch circuit supports boost output, the switching devices SW3, SW4 and SW5 are all bidirectional cut-off type power switching devices, and the switching devices SW1 and SW2 are all unidirectional cut-off type power switching devices.

7. The inverter driving system according to claim 5, wherein the input signal of each comparison control unit further comprises an output terminal voltage signal u_out(t)；

Each full-bridge power switch circuit also comprises a plurality of intermediate direct-current power supply input ends, and the intermediate direct-current power supply input ends are connected with a plurality of intermediate direct-current power supplies; the input voltage of the intermediate DC power supply input end is positioned at + U_inand-U_inEach full-bridge power switch circuit further comprises a plurality of bidirectional cut-off type switch devices SWM and corresponding auxiliary switch capacitors CM, each intermediate direct-current power supply input end is connected with one end of each of the switch devices SW1 and SW2 and one end of the inductor coil L1 through one bidirectional cut-off type switch device SWM, and each bidirectional cut-off type switch device SWM is connected with one auxiliary switch capacitor CM in parallel; the bidirectional turn-off switching device SWM is controlled by a Zero Voltage Switching (ZVS) gate driver.

8. The inverter driving system with ultra-low switching power consumption and ultra-low output electromagnetic interference of claim 1, wherein the power input end of each power switching circuit is: positive and negative ends (+ U) of DC power supply input end_inand-U_in) An output terminal voltage u of each of the power switch circuits_out(t), i.e. the output terminal voltage u of the inverse drive system for each phase_out(t) is;

wherein, U_AThe potential reference point is the voltage at the input end of the direct-current power supplyI.e. half the input dc supply voltage.

9. The inverter driving system with ultra-low switching power consumption and ultra-low output electromagnetic interference as claimed in claim 1, wherein each feedback control unit is driven by an external input signal u_sin(t) output terminal voltage signal u_out(t) output terminal current signal i_out(t) establishing a feedback control network to calculate the required output set current i for that phase_set(t), namely:

i_set(t)＝G(u_sin(t),u_out(t),i_out(t))

the output voltage and current can be expressed as:

wherein C is_outIs the capacity of the output capacitor.

10. The inverter driving system with ultra-low switching power consumption and ultra-low output electromagnetic interference of claim 9, wherein the feedback control unit comprises a PID controller; the specific working process for establishing the feedback control network comprises the following steps:

(1) by applying an external input signal u_sin(t) and the output voltage signal u_out(t) comparing to obtain a voltage difference signal, and inputting the voltage difference signal to a PID controller;

(2) by calculating the external input signal u_sin(t) the derivative with respect to time is multiplied by the output capacitance to give the output capacitance C_outCharging and discharging current;

(3) feeding back incremental current by the voltage difference output by the PID controller in (1) and the output capacitor charging and discharging current obtained in (2) and the current output end current i_out(t) adding, the result being the outputSetting a current i_set(t) and input to the comparison control unit.

Technical Field

The invention relates to the technical field of frequency converters, in particular to an inversion driving system with ultralow switching power consumption and ultralow output end electromagnetic interference.

Background

In a conventional inverter drive system, since the inverter modulates the output by high frequency switching, the switching process generates extremely high du/dt at the output, which may generate large common mode interference through the cable wires, the parasitic capacitance to ground of the motor winding. There is therefore a need for a sinusoidal filter or a power cable with shielding in applications environments that are long and sensitive to electromagnetic interference. At the same output power, the filter size will increase substantially when a lower switching frequency is used, and the switching losses generated by the power switches will also increase when a higher switching frequency is used. While not only increasing system weight and cost, but also creating problems such as additional reactive power and conductor shield ground resistance.

The invention makes the power switch circuit work in a state of being similar to boundary transmission mode to BCM (boundary connection mode) by the combination of the power switch device and the inductance capacitance output circuit, and makes the inductance current increase from reverse switching current to peak current and then decrease to reverse switching current in each high frequency switch period while keeping the output of low frequency sinusoidal voltage current at the output end. The sine voltage circuit output with low higher harmonic wave component is provided in principle, and simultaneously, because the inductance current is opposite to the average value of the inductance current at the beginning and the end of each Switching period, the zero voltage Switching (abbreviated as ZVS) of the power Switching device can be realized through the inductance current, so that the extremely low Switching loss is realized, and the heat generation of the power Switching device during high-frequency Switching is reduced.

Disclosure of Invention

In order to solve the problems in the background art, the present invention provides an inverter driving system with ultra-low switching power consumption and ultra-low output electromagnetic interference.

In order to achieve the purpose, the invention adopts the technical scheme that:

the invention provides an inversion driving system with ultralow switching power consumption and ultralow electromagnetic interference at an output end, which comprises three-phase driving systems, wherein each phase of inversion driving system is an independent system, the output end of each phase of inversion driving system is an alternating current waveform required to be output, and each phase of inversion driving system comprises the following parts: the device comprises a feedback control unit, a comparison control unit and a power switch circuit;

each feedback control unit, through input signals: external input signal u_sin(t) output terminal voltage signal u_out(t) output terminal current signal i_out(t) to calculate the output set current i required for that phase_set(t) and setting the output of the phase required output as a current i_set(t) a comparison control unit outputting to the phase inversion driving system;

each comparison control unit has its input signal including output setting current i output by feedback control unit of the phase inversion driving system_set(t) and real-time measured inductor current i_L(t); setting a current i by an output from a feedback control unit_set(t) calculating the inductance peak current I required by switching of the switch state according to the structural characteristics of the power switch circuit_peak(t) and an intermediate comparative current I_comp(t) setting a switching current I for the zero-voltage switch_constAnd is in parallel with the real-time measured inductor current i_L(t) comparing, determining the corresponding switch state of a switch device in the power switch circuit through logic calculation, and outputting a switch state signal to the power switch circuit of the phase inversion driving system;

the input signal of each power switch circuit is a switch state signal output by a comparison control unit of the phase inversion driving system; the output signal is the voltage signal u at the output terminal_out(t) output terminal current signal i_out(t) and real-time measurement signal of inductor current i_L(t); the inductive current real-time measurement signal i_L(t) feeding back to a comparison control unit of the phase inversion driving system, the output terminal voltage signal u_out(t) and an output terminal current signal i_out(t) is fed back to a feedback control unit of the phase inversion driving system.

In some embodiments, the power switch circuit is a half-bridge power switch circuit or a full-bridge power switch circuit, depending on the application requirements.

In some embodiments, the power switching circuits are half-bridge power switching circuits, each of which includes a high-side switching device SW1, a low-side switching device SW2, auxiliary switching capacitors C1 and C2 connected in parallel with the high-side switching device SW1 and the low-side switching device SW2, respectively, an inductor L1, and output capacitors C3 and C4; positive and negative ends + U of DC power supply input end of each half-bridge power switch circuit_inand-U_inThe high-side switching device SW1 and the low-side switching device SW2 are connected in series between the positive end and the negative end of the input end of the direct-current power supply to form a half-bridge switching circuit, an inductance coil L1 is connected between the output end of the half-bridge switching circuit and output capacitors C3 and C4, and output capacitors C3 and C4 are connected in series between the positive end and the negative end of the input end of the direct-current power supply;

both the high-side switching device SW1 and the low-side switching device SW2 are controlled by zero-voltage switching (ZVS) gate drivers.

In some embodiments, each of the comparison control units, its input signal further comprises an output terminal voltage signal u_out(t)；

Each half-bridge power switch circuit also comprises a plurality of intermediate direct-current power supply input ends, and the intermediate direct-current power supply input ends are connected with a plurality of intermediate direct-current power supplies; the input voltage of the intermediate DC power supply input end is positioned at + U_inand-U_inEach half-bridge power switch circuit further comprises a plurality of bidirectional cut-off type switch devices SWM and corresponding auxiliary switch capacitors CM, each middle direct-current power supply input end is connected with one end of the high-side switch device SW1, one end of the low-side switch device SW2 and one end of the inductor L1 through one bidirectional cut-off type switch device SWM, and each bidirectional cut-off type switch device SWM is connected with one auxiliary switch capacitor CM in parallel; the bidirectional turn-off switching device SWM is controlled by a Zero Voltage Switching (ZVS) gate driver.

In some embodiments, the power switch circuits are full bridge power switch circuits, each of which includes a switchDevices SW1, SW2, SW3, SW4, SW5, auxiliary switching capacitors C1, C2, C3, C4, C5 connected in parallel with the switching devices SW1, SW2, SW3, SW4, SW5, respectively, an inductor L1, and output capacitors C6, C7; the switching devices SW1 and SW2 are connected in series between the positive end and the negative end of the input end of the direct-current power supply, and the switching devices SW3 and SW4 are connected in series between the positive end and the negative end of the input end of the direct-current power supply to form a left half bridge and a right half bridge in a full-bridge switching circuit respectively; positive and negative ends + U of direct-current power supply input end of full-bridge power switch circuit_inand-U_inThe inductance coil L1 is connected between the output ends of the half-bridges at the two sides in the full-bridge switching circuit; the switching device SW5 of the output end is connected between the output capacitors C6 and C7 and the output end of the right half bridge in the full bridge switching circuit; the output capacitors C6 and C7 are connected in series between the positive end and the negative end of the input end of the direct-current power supply;

switching devices SW1, SW2, SW3, SW4, SW5 are all controlled by Zero Voltage Switching (ZVS) gate drivers.

In some embodiments, when the full-bridge power switch circuit does not need to support boost output, the switch device SW5 is a bidirectional cut-off power switch device, and the switch devices SW1, SW2, SW3 and SW4 are all unidirectional cut-off power switch devices; when the full-bridge power switch circuit supports boost output, the switching devices SW3, SW4 and SW5 are all bidirectional cut-off type power switching devices, and the switching devices SW1 and SW2 are all unidirectional cut-off type power switching devices.

In some embodiments, each of the comparison control units, its input signal further comprises an output terminal voltage signal u_out(t)；

Each full-bridge power switch circuit also comprises a plurality of intermediate direct-current power supply input ends, and the intermediate direct-current power supply input ends are connected with a plurality of intermediate direct-current power supplies; the input voltage of the intermediate DC power supply input end is positioned at + U_inand-U_inEach full-bridge power switch circuit further includes a plurality of bidirectional cut-off type switch devices SWM and corresponding auxiliary switch capacitors CM, and each intermediate dc power input terminal passes through one of the bidirectional cut-off type switch devices SWM, the switch devices SW1 and SW2, and one of the inductor L1The terminals are connected, and each bidirectional cut-off type switch device SWM is connected in parallel with an auxiliary switch capacitor CM; the bidirectional turn-off switching device SWM is controlled by a Zero Voltage Switching (ZVS) gate driver.

In some embodiments, the power input of each of the power switching circuits is: positive and negative ends (+ U) of DC power supply input end_inand-U_in) An output terminal voltage u of each of the power switch circuits_out(t), i.e. the output terminal voltage u of the inverse drive system for each phase_out(t) is;

wherein, U_AThe reference potential of (2) is the middle point potential of the voltage at the input end of the direct current power supply, namely half of the voltage of the input direct current power supply.

In some embodiments, each of the feedback control units is driven by an external input signal u_sin(t) output terminal voltage signal u_out(t) output terminal current signal i_out(t) establishing a feedback control network to calculate the required output set current i for that phase_set(t), namely:

i_set(t)＝G(u_sin(t),u_out(t),i_out(t))

the output voltage and current can be expressed as:

wherein C is_outIs the capacity of the output capacitor.

In some embodiments, the feedback control unit comprises a PID controller; the specific working process for establishing the feedback control network comprises the following steps:

(1) by applying an external input signal u_sin(t) and the output voltage signal u_out(t) are compared toOutputting a voltage difference signal and inputting the voltage difference signal to a PID controller;

(2) by calculating the external input signal u_sin(t) the derivative with respect to time is multiplied by the output capacitance to give the output capacitance C_outCharging and discharging current;

(3) feeding back incremental current by the voltage difference output by the PID controller in (1) and the output capacitor charging and discharging current obtained in (2) and the current output end current i_out(t) adding, the result being an output set current i_set(t) and input to the comparison control unit.

Compared with the prior art, the invention has the beneficial effects that:

in the present invention, the power switches (SW1 and SW2, or SW1, SW2, SW3, SW4 and SW5) pass through the inductor L and the output capacitor C_outThe low-frequency switch is connected with the output end, has the function similar to a low-pass filter, and obtains the required low-frequency output voltage by filtering high-frequency switch components; only very low high-frequency components exist at the output end, and electromagnetic interference of the ultra-low output end is realized; the shielding requirement for connecting the cable and the motor is reduced.

Because the inductor and the output end are connected with the output capacitor C_outSo that the inductor current i is in each switching cycle_L(t) and the output current i_out(t) has no direct relationship; in principle by means of an output capacitor C_outThe voltage across the capacitor provides energy to the inductor during the switching cycle to achieve reverse inductor current, thereby achieving Zero Voltage Switching (ZVS) through an auxiliary switching capacitor connected in parallel across the power switching device. Therefore, the characteristics of ultralow switching loss of the power switching device and ultralow output end high-frequency electromagnetic interference are realized.

Drawings

FIGS. 1 a-1 b are schematic block diagrams of the circuit of the present invention;

FIG. 2 is a schematic circuit diagram of a feedback control unit according to the present invention;

fig. 3 is a circuit schematic of a half-bridge power switching circuit in a first embodiment;

FIGS. 4 a-4 b show inductor current versus switch state and switch terminal voltage for the first embodiment;

FIG. 5 is a circuit schematic of a full bridge power switch circuit in a second embodiment;

6 a-6 b are inductor current and switch states for the second embodiment without support for boost output;

FIG. 7 is a graph of output voltages at the output end of the inverter driving system of each phase when the boost output is supported in the second embodiment;

FIG. 8 is a graph of inductor current in a second embodiment;

FIGS. 9 a-9 d are diagrams of inductor current and switch states for the second embodiment with boost output supported;

fig. 10 is a schematic circuit diagram of a half-bridge power switching circuit in a third embodiment;

11 a-11 d are inductor current and switch states in a third embodiment;

fig. 12 is a schematic circuit diagram of a half-bridge power switching circuit in a fourth embodiment;

FIGS. 13 a-13 b illustrate the inductor current and switching state in a fourth embodiment;

fig. 14 is a circuit schematic of a full bridge power switching circuit in a fifth embodiment;

FIGS. 15 a-15 d are diagrams of inductor current and switch states for the fifth embodiment without support for boost output;

fig. 16 is a circuit schematic of a full bridge power switching circuit in a sixth embodiment;

FIGS. 17 a-17 b illustrate inductor current and switch states for the sixth embodiment without support for boost output;

fig. 18a and 18b are schematic diagrams of a unidirectional cut-off type switching device and a bidirectional cut-off type switching device, respectively.

Detailed Description

In order to make the technical means, the creation features, the achievement purposes and the effects of the invention easy to understand, the following description further explains how the invention is implemented by combining the attached drawings and the detailed implementation modes.

As shown in fig. 1a, the present invention provides an inverter driving system with ultra-low switching power consumption and ultra-low electromagnetic interference at the output end, which includes a multi-phase inverter driving system, such as a three-phase inverter driving system; each phase of the inverse transformation driving system is an independent system, the output end of each phase of the inverse transformation driving system is an alternating current waveform, such as sinusoidal alternating current, required to be output, the output end is connected with an external load, and the load can be a motor; each phase of the inverse variable driving system comprises the following parts: the device comprises a feedback control unit, a comparison control unit and a power switch circuit;

each feedback control unit, through input signals: external input signal (which may be a sinusoidal voltage signal) u_sin(t) output terminal voltage signal u_out(t) and an output terminal current signal i_out(t) to calculate the output set current i required for that phase_set(t) and setting the output of the phase required output as a current i_set(t) a comparison control unit outputting to the phase inversion driving system;

each comparison control unit has its input signal including output setting current i output by feedback control unit of the phase inversion driving system_set(t) and real-time measured inductor current i_L(t); setting a current i by an output from a feedback control unit_set(t) calculating the inductance peak current I required by switching of the switch state according to the structural characteristics of the power switch circuit_peak(t) intermediate comparative Current I_comp(t) and setting a switching current I for the zero-voltage switch_constThe direction of the switching current is opposite to the direction of the inductor peak current and is equal to the inductor current i measured in real time_L(t) comparing, determining the corresponding switch state of the power switch device through logic calculation, and outputting a switch state signal to a power switch circuit of the phase inversion driving system;

the input signal of each power switch circuit is a switch state signal output by a comparison control unit of the phase inversion driving system; the output signal is the voltage signal u at the output terminal_out(t) output terminal current signal i_out(t) and real-time measurement signal of inductor current i_L(t) of (d). When the power switch works, the inductive current i obtained by real-time measurement is measured by an inductive current measuring circuit in the power switch circuit_L(t) comparative control fed back to the phase inversion drive systemA unit for measuring output voltage and current in the power switch circuit_out(t) and output terminal current i_out(t) is fed back to a feedback control unit of the phase inversion driving system.

Specifically, the power input terminal of the power switch circuit is: positive and negative ends (+ U) of DC power supply input end_in、-U_in) The power output end of each power switch circuit is sine voltage output, namely the voltage u at the output end of each phase of inverse variation driving system_out(t) of (d). Namely:

where ω is angular velocity, t is actual time, U_AThe reference potential of the voltage reference circuit is the middle point potential of the voltage of the input end of the direct current power supply, namely half of the voltage of the input direct current power supply; for example, the output voltage curve (see fig. 7) of the output terminal of each phase driving system in the full bridge circuit supporting the boost output is the time variation of the output voltage of the output terminal of each phase driving system and the dc input voltage.

In the invention, an output terminal voltage signal u input by a feedback control unit_out(t) is the output terminal voltage u for output to the load_out(t) digital quantization on one sensor acquisition.

In the invention, the power switch circuit comprises a switch device, an auxiliary switch capacitor, an inductance coil and an output capacitor, wherein the capacity of the auxiliary switch capacitor is far smaller than that of the output capacitor; the gate driving module of the switching device realizes Zero Voltage Switching (ZVS) of the switching device by acquiring a switching state signal and real-time voltages at two ends of the switching device.

As shown in fig. 2, the feedback control unit has a built-in feedback control system, which inputs a signal u via an external sinusoidal voltage_sin(t) output terminal voltage signal u_out(t) output terminal current signal i_out(t) establishing a feedback control network to calculate the required output set current i for that phase_set(t), namely:

i_set(t)＝G(u_sin(t),u_out(t),i_out(t))

the output voltage and current can be expressed as:

wherein C is_outIs the capacity of the output capacitor;

the feedback control system comprises a PID controller; the specific working process comprises the following steps:

(1) by inputting a signal u to a sinusoidal voltage_sin(t) and the output voltage signal u_out(t) comparing to obtain a voltage difference signal, and inputting the voltage difference signal to a PID controller;

(2) by calculating a sinusoidal voltage input signal u_sin(t) the derivative with respect to time is multiplied by the output capacitance to give the output capacitance C_outCharging and discharging current;

(3) feeding back incremental current by the voltage difference output by the PID controller in (1) and the output capacitor charging and discharging current obtained in (2) and the current output end current i_out(t) adding, the result being an output set current i_set(t) and input to the comparison control unit.

In the invention, the feedback control unit structure is a basic structure, the PID controller is a standard feedback controller, and the parameters are matched and set according to the parameters when the specific circuit is designed; with the development of control system technology and the application of advanced control systems and adaptive control systems, the feedback control unit can be upgraded and optimized accordingly. But its role in the overall system remains the same as that of the above described feedback control unit, namely:

by input signal-sinusoidal voltage input signal u_sin(t) output terminal voltage signal u_out(t) output terminal current signal i_out(t); calculating output signal-output set currenti_set(t); and inputs it to the comparison control unit. Thereby stabilizing the whole system and outputting a sine voltage input signal u_sin(t) corresponding output terminal voltage signal u_out(t)。

According to application requirements, the power switch circuit is divided into a half-bridge power switch circuit (half-bridge circuit for short) and a full-bridge power switch circuit (full-bridge circuit for short). For example, fig. 8 shows the real-time measured inductor current i in the full-bridge power switch circuit_L(t) curve. Several embodiments of the inverter driving system provided by the present invention under different conditions of the power switch circuit are described below.

In a first embodiment, the power switching circuit is a half-bridge power switching circuit.

The overall schematic block diagram is shown in fig. 1a, the schematic of the power switching circuits is shown in fig. 3, each of the half-bridge power switching circuits includes a high-side switching device SW1, a low-side switching device SW2, auxiliary switching capacitors C1 and C2 respectively connected in parallel with the high-side switching device SW1 and the low-side switching device SW2, an inductor L1, and output capacitors C3 and C4; the direct-current power supply input end of the half-bridge power switching circuit is connected with a direct-current power supply, the high-side switching device SW1 and the low-side switching device SW2 are connected in series between the positive end and the negative end of the direct-current power supply input end to form a half-bridge switching circuit, the inductance coil L1 is connected between the output end of the half-bridge switching circuit and the output capacitors C3 and C4, and the output capacitors C3 and C4 are connected in series between the positive end and the negative end of the direct-current power; both the high-side switching device SW1 and the low-side switching device SW2 are controlled by zero-voltage switching (ZVS) gate drivers.

Each comparison control unit is internally provided with a comparator and a logic calculation unit and is provided with a switching current I for a zero-voltage switch_const(ii) a Setting a current i by an output from a feedback control unit_set(t) calculating the inductance peak current I required by switching of the switch state according to the structural characteristics of the power switch circuit_peak(t) intermediate comparative Current I_comp(t) and a switching current I_constAnd the measured inductance current i in real time_L(t) comparing, determining corresponding to the structure of the half-bridge power switch circuitTo the power switching circuit;

to output a set current i_set(t) is a positive current (i)_set(t) > 0A) as an example (as shown in FIG. 4 a), the time and the change of the inductor current during the Zero Voltage Switching (ZVS) are negligible due to the very small capacitance of the auxiliary switch capacitor. The whole switching process can be simplified into the following two parts:

in each half-bridge power switch circuit in the first embodiment, the peak inductor current I_peak(t) and the output set current i_setThe calculation relationship of (t) is shown in Table 1:

TABLE 1 inductance Peak Current I_peak(t) and the output set current i_set(t) relational Table

	Peak current of inductor	Inductor reverse switching current
			iset(t)＞0A	Ipeak(t)＝2·iset(t)+Iconst	-Iconst
iset(t)＝0A	Ipeak(t)＝Iconst	-Iconst
			iset(t)<0A	Ipeak(t)＝2·iset(t)-Iconst	Iconst

The corresponding switch states are shown in fig. 4a and 4b, and the specific statistics are shown in table 2: [ State 0 is OFF and 1 is ON ]

Table 2 the corresponding switch states are determined by the structure of the half bridge circuit in the first embodiment

The working sequence of the circuit in one switching period is shown in table 3: [ State 0 is OFF and 1 is ON ]

TABLE 3 operating timing and Zero Voltage Switching (ZVS) procedure for one switching cycle of the half-bridge circuit in the first embodiment

In a second embodiment, the power switch circuit is a full bridge power switch circuit.

The overall schematic block diagram is shown in fig. 1a, the schematic diagram of the power switch circuits is shown in fig. 5, each of the full-bridge power switch circuits includes a switch device SW1, SW2, SW3, SW4, SW5, an auxiliary switch capacitor C1, C2, C3, C4, C5, an inductor L1, and an output capacitor C6, C7, which are respectively connected in parallel with the switch devices SW1, SW2, SW3, SW4, SW 5; the switching devices SW1 and SW2 are connected in series between the positive end and the negative end of the input end of the direct-current power supply, and the switching devices SW3 and SW4 are connected in series between the positive end and the negative end of the input end of the direct-current power supply to form a left half bridge and a right half bridge in a full-bridge switching circuit respectively; the direct-current power supply input end of the full-bridge power switching circuit is connected with a direct-current power supply, and the inductance coil L1 is connected between the output ends of the half-bridges at two sides in the full-bridge power switching circuit; the switching device SW5 of the output end is connected between the output capacitors C6 and C7 and the output end of the right half bridge in the full bridge switching circuit; the output capacitors C6 and C7 are connected in series between the positive and negative ends of the DC power input end.

The second embodiment is divided into two sub-embodiments: when the full-bridge power switch circuit does not need to support boost output, the switch device SW5 is a bidirectional cut-off switch device, and the switch devices SW1, SW2, SW3 and SW4 are all unidirectional cut-off switch devices; for example, each of the switching devices SW1, SW2, SW3 and SW4 is a MOSFET or IGBT and a freewheeling diode, the switching device SW5 is two MOSFETs or IGBTs connected in series in opposite directions and respectively connected with a freewheeling diode, and each MOSFET or IGBT is respectively connected with an auxiliary switching capacitor in parallel. The structures of the unidirectional cut-off type switching device and the bidirectional cut-off type switching device described in the present invention are shown in fig. 18a and 18b, respectively.

When the full-bridge power switch circuit supports boost output, the switching devices SW3, SW4 and SW5 are all bidirectional cut-off type power switching devices, and the switching devices SW1 and SW2 are all unidirectional cut-off type power switching devices; for example, each of the switching devices SW1 and SW2 is a MOSFET or an IGBT cooperating with a freewheeling diode, the switching devices SW3, SW4 and SW5 are two MOSFETs or IGBTs connected in series in opposite directions and cooperating with freewheeling diodes, respectively, and each MOSFET or IGBT is connected in parallel with an auxiliary switching capacitor, respectively.

In the present invention, as shown in fig. 18a and 18b, the bidirectional cut-off power switch device is generally two MOSFETs or IGBTs connected in series in opposite directions and matching with a freewheeling diode; the unidirectional cut-off type power switch device is a common MOSFET or IGBT matched with a freewheeling diode; the on-resistance of the bidirectional cut-off type power switch device is larger than that of the ordinary unidirectional cut-off type power switch device in principle, so that the unidirectional cut-off type power switch device is used as much as possible if no boosting output is required.

The switching devices SW1, SW2, SW3, SW4, SW5 are all controlled by Zero Voltage Switching (ZVS) gate drivers, the combination of switches through which high inductor average current can be achieved during the switching cycle.

To output a set current i_set(t) is a positive current (i)_set(t) > 0A) as an example (as shown in FIG. 6 a), the time and the change of the inductor current during the Zero Voltage Switching (ZVS) are negligible due to the very small capacitance of the auxiliary switch capacitor. The whole switching process can be simplified into the following four parts:

in the second embodiment, the full-bridge power switch circuit can normally turn on SW3 and SW4 (off) and normally turn off SW5 (on) under the working condition of smaller output power to achieve the same working effect as the half-bridge power switch circuit, and the state control manner is the same as that of the half-bridge power switch circuit.

Each comparison control unit is internally provided with a comparator and a logic calculation unit and is provided with a switching current I for a zero-voltage switch_const(ii) a The logic calculation unit sets a current i according to the output by the feedback control unit_set(t) calculating the inductance peak current I required by the switch state switching according to the structural characteristics of the full-bridge power switch circuit_peak(t) and an intermediate comparative current I_comp(t) and the inductance current i obtained by real-time measurement_L(t) comparing by a comparator, and determining a corresponding switch state to the power switch circuit according to the structure of the full-bridge power switch circuit, specifically:

in each full-bridge power switch circuit, the DC input voltage U is applied to the inductor_inMake the inductor current i_L(t) short-time slave and slave inputsSet current i_set(t) switching current I in opposite directions_constIntermediate comparison current I increasing to the positive direction_comp(t) so as to pass a lower peak inductor current I_peak(t) higher inductor average current is achieved during the switching cycle; wherein the intermediate comparison current I_comp(t) magnitude is at switching current I_constAnd I_peak(t) between, direction and inductance peak current I_peakThe direction of (t) is the same.

Due to the switching of the inductor current from the reverse direction_constIntermediate comparison current I increasing to the positive direction_compThe time of (t) is very short, the influence on the average current of the inductor in the whole switching period can be ignored in the process, and the peak current I of the inductor_peak(t) and the output set current i_setThe calculation relationship of (t) is shown in Table 4:

TABLE 4 inductance Peak Current I_peak(t) and the output set current i_set(t) relational Table

	Peak current of inductor	Reverse current of inductor
			iset(t)＞0A	Ipeak(t)≈2·iset(t)-Icomp(t)	-Iconst
iset(t)＝0A	Ipeak(t)＝Iconst	-Iconst
			iset(t)<0A	Ipeak(t)≈2·iset(t)-Icomp(t)	Iconst

In the second embodiment, the switch states corresponding to the structure of the full-bridge power switch circuit without supporting the boost output are shown in fig. 6a and 6b, and the specific statistics are shown in table 5: [ State 0 is OFF and 1 is ON ]

TABLE 5 switching states corresponding to the configuration of a full bridge power switching circuit without supporting boost output in the second embodiment

The working sequence of the circuit in one switching period is shown in the table 6: [ State 0 is OFF and 1 is ON ]

TABLE 6 working timing and Zero Voltage Switching (ZVS) procedure in one switching cycle in the second embodiment of the full bridge power switching circuit without boost support output

In the second embodiment, the switch states corresponding to the structure of the full-bridge power switch circuit supporting boost output are shown in fig. 9a, 9b, 9c and 9d, and the specific situations are shown in table 7 and table 8: [ State 0 is OFF and 1 is ON ]

TABLE 7 switching states (I) corresponding to the structure of the full bridge power switching circuit supporting boost output in the second embodiment

TABLE 8 switching states (two) corresponding to the structure of the full bridge power switching circuit supporting boost output in the second embodiment

In a third embodiment, the power switching circuit is a half-bridge power switching circuit.

The overall schematic block diagram is shown in fig. 1b, and fig. 1b differs from fig. 1a in that each of the comparison control units has an input signal further including an output terminal voltage signal u_out(t)。

The principle of the power switch circuit is shown in fig. 10, and the difference from the half-bridge power switch circuit in the first embodiment is that each half-bridge power switch circuit further includes a plurality of intermediate dc power input terminals, the intermediate dc power input terminals are connected to a plurality of intermediate dc power supplies, in this embodiment, one intermediate dc power input terminal is used, and U is used_inM1Represents; input voltage U of intermediate DC power supply input end_inM1At + U_inand-U_inEach half-bridge power switch circuit further comprises a bidirectional cut-off type switch device SWM1 and a corresponding auxiliary switch capacitor CM1, each intermediate dc power supply input terminal is connected to one end of the high-side switch device SW1, the low-side switch device SW2 and the inductor L1 through a bidirectional cut-off type switch device SWM1, and each bidirectional cut-off type switch device SWM1 is connected in parallel to one auxiliary switch capacitor CM 1; the bidirectional off-type switching device SWM1 is controlled by a Zero Voltage Switching (ZVS) gate driver.

The working principle is similar to that of the first embodiment, but because an intermediate dc power supply U is added_inM1Comparing the inductor current i in real time_L(t) and inductance peak current I_peak(t) intermediate comparative Current I_comp(t) and the switching current I_constWhen the voltage of the output end u is larger or smaller, the voltage of the output end u is also required to be combined_out(t) the voltage range in which it is located.

Specifically, the switching state in one switching cycle is:

when i is_set(t) > 0A and u_out(t)＞U_inM1At this time I_peak(t)＞0A、I_comp(t) > 0A, switching current of-I_constAs shown in fig. 11a and table 9:

TABLE 9 arrangement of half-bridge power switch circuits in the third embodiment corresponds to switch states (I)

Time interval	Comparing trigger conditions	Range of inductive current	SW1	SWM1	SW2
						(0,t0]	iL(t)≤-Iconst	-Iconst<iL(t)≤Ipeak(t)	1	0	0
(t0,t1]	iL(t)≥Ipeak(t)	Icompt≤iL(t)<Ipeak(t)	0	1	0
						(t1,T]	iL(t)≤Icomp(t)	-Iconst≤iL(t)<Icomp(t)	0	0	1

When i is_set(t)<0A and u_out(t)＞U_inM1At this time I_peak(t)<0A、I_comp(t)<0A, switching current of I_constAs shown in fig. 11b and table 10:

TABLE 10 arrangement of half-bridge power switch circuits in the third embodiment for the corresponding switch states (two)

Time interval	Comparing trigger conditions	Range of inductive current	SW1	SWM1	SW2
						(0,t0]	iL(t)≥Iconst	Icomp(t)≤iL(t)<Iconst	0	0	1
(t0,t1]	iL(t)≤Icomp(t)	Ipeak(t)≤iL(t)<Icomp(t)	0	1	0
						(t1,T]	iL(t)≤Ipeak(t)	Ipeak(t)<iL(t)≤Iconst	1	0	0

When i is_set(t) > 0A and u_out(t)<U_inM1At this time I_peak(t)＞0A、I_comp(t) > 0A, switching current of-I_constAs shown in fig. 11c and table 11:

TABLE 11 arrangement of half-bridge power switch circuits in the third embodiment corresponds to switch state (III)

Time interval	Comparing trigger conditions	Range of inductive current	SW1	SWM1	SW2
						(0,t0]	iL(t)≤-Iconst	-Iconst<iL(t)≤Icomp(t)	1	0	0
(t0,t1]	iL(t)≥Icomp(t)	Icomp(t)<iL(t)≤Ipeak(t)	0	1	0
						(t1,T]	iL(t)≥Ipeak(t)	-Iconst≤iL(t)<Ipeak(t)	0	0	1

When i is_set(t)<0A and u_out(t)<U_inM1At this time I_peak(t)<0A、I_comp(t)<0A, switching current of I_constAs shown in fig. 11d and table 12:

TABLE 12 arrangement of half-bridge power switch circuits in the third embodiment for the corresponding switch states (IV)

Time interval	Comparing trigger conditions	Range of inductive current	SW1	SWM1	SW2
						(0,t0]	iL(t)≥Iconst	Ipeak(t)≤iL(t)<Iconst	0	0	1
(t0,t1]	iL(t)≤Ipeak(t)	Ipeakt<iL(t)≤Icomp(t)	0	1	0
						(t1,T]	iL(t)≥Icomp(t)	Icomp(t)<iL(t)≤Iconst	1	0	0

In a fourth embodiment, the power switching circuit is a half-bridge power switching circuit.

The overall schematic block diagram is shown in fig. 1b, the power switch circuit principle is shown in fig. 12, and the difference from the third embodiment is that each half-bridge power switch circuit comprises two intermediate dc power input terminals U_inM1And U_inM2And are respectively connected with two intermediate DC power supplies with input voltage U_inM1And U_inM2Are all located at + U_inand-U_inAnd U is_inM1＞U_inM2Each half-bridge power switch circuit comprises two bidirectional cut-off type switch devices SWM1 and SWM2 and two corresponding auxiliary switch capacitors CM1 and CM2, two middle direct current power supply input ends are respectively connected with one end of a high-side switch device SW1, one end of a low-side switch device SW2 and one end of an inductance coil L1 through one bidirectional cut-off type switch device, and each bidirectional cut-off type switch device is connected with one auxiliary switch capacitor in parallel; the bidirectional off-type switching devices SWM1, SWM2 are controlled by Zero Voltage Switching (ZVS) gate drivers.

It can be understood that in other embodiments, the number of the intermediate dc power input terminals may also be other than 2, for example, n, the circuit structure is also changed correspondingly, and the number of the bidirectional blocking type switching devices and the auxiliary switching capacitors is also n; as long as the requirement that the input voltage of the input ends of the n intermediate direct-current power supplies is all positioned at + U_inand-U_inThe method can be implemented in the following steps.

In the fourth embodiment, when the output voltage u is_out(t) when the voltage value of the input terminal of each intermediate dc power supply is greater than or less than the voltage value of the input terminal of each intermediate dc power supply, selecting the intermediate dc power supply adjacent to the voltage value of the output terminal as the intermediate dc power supply, and controlling the power switch circuit in the same manner as the power switch circuit having a single intermediate dc power supply input terminal in the third embodiment.

In other cases, the switching state in one switching cycle is:

when i is_set(t) > 0A and U_inM2<u_out(t)<U_inM1At this time I_peak(t)＞0A、 I_comp(t) > 0A, switching current of-I_constAs shown in fig. 13a and table 13:

TABLE 13 arrangement of half-bridge power switch circuits in the fourth embodiment corresponds to switch states (I)

Time interval	Comparing trigger conditions	Range of inductive current	SW1	SWM1	SWM2	SW2
							(0,t0]	iL(t)≤-Iconst	-Iconst<iL(t)≤Icomp(t)	1	0	0	0
(t0,t1]	iL(t)≥Icomp(t)	Icomp(t)<iL(t)≤Ipeak(t)	0	1	0	0
							(t1,t2]	iL(t)≥Ipeak(t)	Icomp(t)≤iL(t)<Ipeak(t)	0	0	1	0
(t2,T]	iL(t)≤Icomp(t)	-Iconst≤iL(t)<Icomp(t)	0	0	0	1

When i is_set(t)<0A and U_inM2<u_out(t)<U_inM1At this time I_peak(t)<0A、 I_comp(t)<0A, switching current of I_constAs shown in fig. 13b and table 14:

TABLE 14 switching states (two) corresponding to the configuration of the half-bridge power switching circuit in the fourth embodiment

Time interval	Comparing trigger conditions	Range of inductive current	SW1	SWM1	SWM2	SW2
							(0,t0]	iL(t)≥Iconst	Icomp(t)≤iL(t)<Iconst	0	0	0	1
(t0,t1]	iL(t)≤Icomp(t)	Ipeak(t)≤iL(t)<Icomp(t)	0	0	1	0
							(t1,t2]	iL(t)≤Ipeak(t)	Ipeak(t)<iL(t)≤Icomp(t)	0	1	0	0
(t2,T]	iL(t)≥Icomp(t)	Icomp(t)<iL(t)≤Iconst	1	0	0	0

The voltage u of each terminal point potential is based on the potential of the middle point of the input end of the direct current power supply_out(t)、U_inM1、U_inM2Are all the voltages from all ends to the middle point between the positive end and the negative end of the input end of the direct current power supply, and the voltage height relation is-U_in/2<U_inM2<U_inM1<+U_in/2。

In a fifth embodiment, the power switch circuit is a full bridge power switch circuit.

The overall schematic block diagram is shown in fig. 1b, the power switch circuit principle is shown in fig. 14, and the difference from the second embodiment is that each full bridge powerThe switch circuit further comprises a plurality of intermediate direct current power supply input ends, the intermediate direct current power supply input ends are connected with the plurality of intermediate direct current power supplies, in the embodiment, one intermediate direct current power supply input end is used for connecting the plurality of intermediate direct current power supplies, and the number of the intermediate direct current power supply input ends is U_inM1Represents; input voltage U of intermediate DC power supply input end_inM1At + U_inand-U_inEach full-bridge power switch circuit also comprises a bidirectional cut-off type switch device SWM1 and a corresponding auxiliary switch capacitor CM1, the input end of the middle direct-current power supply is connected with one end of the switch devices SW1 and SW2 and one end of the inductance coil L1 through the bidirectional cut-off type switch device SWM1, and the bidirectional cut-off type switch device SWM1 is connected with the auxiliary switch capacitor CM1 in parallel; the bidirectional off-type switching device SWM1 is controlled by a Zero Voltage Switching (ZVS) gate driver. And in this embodiment, the full bridge power switch circuit need not support boost output.

The working principle is similar to that of the second embodiment, but because an intermediate DC power supply U is added_inM1Comparing the inductor current i in real time_L(t) and inductance peak current I_peak(t) intermediate comparative Current I_comp(t) and the switching current I_constWhen the voltage of the output end u is larger or smaller, the voltage of the output end u is also required to be combined_out(t) the voltage range in which it is located.

Specifically, the switching state in one switching cycle is:

when i is_set(t) > 0A and u_out(t)＞U_inM1At this time I_peak(t)＞0A、I_comp(t) > 0A, switching current of-I_constAs shown in fig. 15a and table 15:

TABLE 15 switching states (I) corresponding to the configuration of the full bridge power switching circuit in the fifth embodiment

When i is_set(t)<0A and u_out(t)＞U_inM1At this time I_peak(t)<0A、I_comp(t)<0A, switching current of I_constAs shown in fig. 15b and table 16:

TABLE 16 switching states (two) corresponding to the configuration of the full-bridge power switching circuit in the fifth embodiment

When i is_set(t) > 0A and u_out(t)<U_inM1At this time I_peak(t)＞0A、I_comp(t) > 0A, switching current of-I_constAs shown in fig. 15c and table 17:

TABLE 17 switching states (III) corresponding to the configuration of the full bridge power switching circuit in the fifth embodiment

When i is_set(t)<0A and u_out(t)<U_inM1At this time I_peak(t)<0A、I_comp(t)<0A, switching current of I_constAs shown in fig. 15d and table 18:

TABLE 18 switching states (IV) corresponding to the configuration of the full bridge power switching circuit in the fifth embodiment

In a sixth embodiment, the power switch circuit is a full bridge power switch circuit.

The overall schematic block diagram is shown in fig. 1b, the power switch circuit principle is shown in fig. 16, and the difference from the fifth embodiment is that each full-bridge power switch circuit includes two intermediate dc power input terminals U_inM1And U_inM2And are respectively connected with two intermediate DC power supplies with input voltage U_inM1And U_inM2Are all located at + U_inand-U_inAnd U is_inM1＞U_inM2Each full-bridge power switch circuit comprises two bidirectional cut-off type switch devices SWM1 and SWM2 and two corresponding auxiliary switch capacitors CM1 and CM2, and two middle direct current power supply input ends are respectively connected with the two auxiliary switch capacitors CM1 and CM2 through one bidirectional cut-off type switch device and one bidirectional cut-off type switch deviceSW1, SW2 and one end of the inductance coil L1 are connected, and each bidirectional cut-off type switch device is connected with an auxiliary switch capacitor in parallel; the bidirectional off-type switching devices SWM1, SWM2 are controlled by Zero Voltage Switching (ZVS) gate drivers. And in this embodiment, the full bridge power switch circuit need not support boost output.

It can be understood that in other embodiments, the number of the intermediate dc power input terminals may also be other than 2, for example, n, the circuit structure is also changed correspondingly, and the number of the bidirectional blocking type switching devices and the auxiliary switching capacitors is also n; as long as the requirement that the input voltage of the input ends of the n intermediate direct-current power supplies is all positioned at + U_inand-U_inThe method can be implemented in the following steps.

In the sixth embodiment, when the output terminal voltage u_out(t) when the voltage value of the input terminal of each intermediate dc power supply is greater than or less than the voltage value of the input terminal of each intermediate dc power supply, selecting the intermediate dc power supply adjacent to the voltage value of the output terminal as the intermediate dc power supply, and controlling the power switch circuit in the same manner as the power switch circuit having a single intermediate dc power supply input terminal in the fifth embodiment.

In other cases, the switching state in one switching cycle is:

when i is_set(t) > 0A and U_inM2<u_out(t)<U_inM1At this time I_peak(t)＞0A、 I_comp(t) > 0A, switching current of-I_constAs shown in fig. 17a and table 19:

TABLE 19 switching states (I) corresponding to the configuration of the full bridge power switching circuit in the sixth embodiment

When i is_set(t)<0A and U_inM2<u_out(t)<U_inM1At this time I_peak(t)<0A、 I_comp(t)<0A, switching current of I_constAs shown in fig. 17b and table 20:

TABLE 20 switching states (two) corresponding to the configuration of the full bridge power switching circuit in the sixth embodiment

The voltage u of each terminal point potential is based on the potential of the middle point of the input end of the direct current power supply_out(t)、U_inM1、U_inM2Are all the voltages from all ends to the middle point between the positive end and the negative end of the input end of the direct current power supply, and the voltage height relation is-U_in/2<U_inM2<U_inM1<+U_in/2。

In summary, the present invention provides the required current to the output capacitor and the output load in a high frequency switching manner by regarding the combination of the power switch device and the inductor as a controllable current source, and the output end voltage is obtained by integrating the difference value of the current supplied by the inductor and the current flowing out of the load on the capacitor with respect to time.

Through the control of the change rate of the output voltage by the capacitor and the decoupling of the instantaneous current and the output current of the inductor, the power switch circuit works in a boundary transfer mode (BCM), and the characteristics of low switching loss and low output end high-frequency electromagnetic interference are realized simultaneously in principle. The method has good compatibility for power switching devices (such as Superjunction-MOSFET) with larger parasitic capacitance, and plays an auxiliary role in the wide application of future faster power switching devices (such as SiC-MOSFET and GaN-FET).

In the third to sixth embodiments, the intermediate dc power input, the corresponding bidirectional turn-off switch device, and the corresponding auxiliary switch capacitor are added to the circuit, and in such a structure, the voltage across the inductor is switched, so that a higher average inductor current can be achieved with a lower peak inductor current, and the turn-on loss of the system is reduced.

Finally, the above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, which should be covered by the claims of the present invention.