阅读说明：本技术 半导体工艺所用的方法 (Method for semiconductor processing ) 是由 林宗达 侯承浩 张哲豪 于雄飞 于 2019-04-09 设计创作，主要内容包括：一种半导体工艺所用的方法。此处所述的实施例关于形成装置的栅极结构的方法,比如置换栅极工艺与其形成的装置。在一实施例中,方法包括顺应性地形成栅极介电层于自基板延伸的鳍状物上,且栅极介电层沿着鳍状物上的栅极间隔物的侧壁；在采用含硅前驱物与含氟、氘、或上述的组合的掺质气体的沉积工艺时,顺应性地沉积虚置层于栅极介电层上,且沉积的虚置层包括氟、氘、或上述的组合的掺质；进行热工艺,以自虚置层驱动掺质至栅极介电层中；移除虚置层；以及形成一或多个含金属层于栅极介电层上。(A method for semiconductor processing. Embodiments described herein relate to methods of forming gate structures for devices, such as replacement gate processes and devices formed thereby. In one embodiment, a method includes conformably forming a gate dielectric layer on a fin extending from a substrate, the gate dielectric layer along sidewalls of gate spacers on the fin; conformably depositing a dummy layer over the gate dielectric layer using a deposition process employing a silicon-containing precursor and a dopant gas comprising fluorine, deuterium, or a combination thereof, wherein the deposited dummy layer comprises a dopant of fluorine, deuterium, or a combination thereof; performing a thermal process to drive dopants from the dummy layer into the gate dielectric layer; removing the dummy layer; and forming one or more metal-containing layers on the gate dielectric layer.)

1. A method for semiconductor processing, comprising:

conformably forming a gate dielectric layer on a fin extending from a substrate, the gate dielectric layer along sidewalls of gate spacers on the fin;

conformably depositing a dummy layer over the gate dielectric layer using a deposition process of a silicon-containing precursor and a dopant gas comprising fluorine, deuterium, or a combination thereof, the deposited dummy layer comprising a dopant of fluorine, deuterium, or a combination thereof;

performing a thermal process to drive the dopants from the dummy layer into the gate dielectric layer;

removing the dummy layer; and

one or more metal-containing layers are formed on the gate dielectric layer.

Technical Field

Embodiments of the present invention relate to methods of forming gate structures of devices, such as replacement gate processes and devices formed thereby.

Background

In fabricating field effect transistors, such as fin field effect transistors, metal gates may be used instead of polysilicon gates to improve device performance. The step of forming the metal gate may include sequentially forming a gate dielectric layer, a barrier layer, a work function layer, and a metal liner layer in the high aspect ratio trench, and then filling the trench with a fill material. The high-k dielectric material maintains the desired gate capacitance while reducing gate oxide leakage. However, high-k dielectrics may have a high density of defects, which may offset device performance. However, scaling also presents new challenges.

Disclosure of Invention

The method for the semiconductor process provided by the embodiment of the invention comprises the following steps: conformably forming a gate dielectric layer on the fin extending from the substrate, the gate dielectric layer along sidewalls of the plurality of gate spacers on the fin; conformably depositing a dummy layer over the gate dielectric layer using a deposition process employing a silicon-containing precursor and a dopant gas comprising fluorine, deuterium, or a combination thereof, wherein the deposited dummy layer comprises a dopant of fluorine, deuterium, or a combination thereof; performing a thermal process to drive dopants from the dummy layer into the gate dielectric layer; removing the dummy layer; and forming one or more metal-containing layers on the gate dielectric layer.

Drawings

Figure 1 is a three-dimensional view of an intermediate structure of a finfet in some embodiments.

Fig. 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, and 9B are cross-sectional views along the cross-sectional lines a-a and B-B of fig. 1 of respective intermediate structures in a method of forming a semiconductor device in some embodiments.

Description of reference numerals:

A-A, B-B section line

T1 first thickness

T2 second thickness

Intermediate structure of 40 fin field effect transistor

42 semiconductor substrate

44 isolation region

46 fin

62. 80 interfacial dielectric layer

64 dummy gate layer

66 mask layer

68 gate spacer

52a, 52b, 70 source/drain regions

72 first interlayer dielectric layer

73 side wall

74 recess

82 gate dielectric layer

86 barrier layer

87 inactivating species

88 virtual layer

89. Insert 91, 93

95 surface region

100 first work function adjusting layer

102 second work function adjusting layer

104 barrier/adhesion layer

106 gate metal filling layer

110 second interlayer dielectric layer

112 cushion layer

114 silicide region

116 conductive material

Detailed Description

The different embodiments or examples provided below may implement different configurations of the present invention. The particular arrangements and examples shown are meant to simplify the present invention and not to limit the invention. For example, the formation of a first element on a second element is described as including direct contact between the two elements, or the separation of additional elements other than direct contact between the two elements. Moreover, the various examples of the present disclosure may be repeated with reference numbers, but such repetition is merely intended to simplify and clarify the description and does not imply that there is a similar correspondence between elements having the same reference numbers in different embodiments and/or arrangements.

Moreover, spatially relative terms such as "below," "lower," "above," "upper," or the like may be used for ease of description to describe one element's relative relationship to another element in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings.

Generally, embodiments of the present invention relate to methods of forming gate structures of devices, such as replacement gate processes and devices formed thereby. More specifically, some examples conformally form a dummy layer containing a passivation species (e.g., fluorine or deuterium) on the gate dielectric layer after deposition of the gate dielectric layer, and perform a thermal process to diffuse the passivation species from the dummy layer into the gate dielectric layer to passivate the gate dielectric layer. The dummy layer is removed, and subsequent layers of the gate structure, such as one or more work function adjusting layers and a gate fill metal, are formed. Among other advantages, device degradation, such as time-dependent dielectric breakdown, is improved, and device performance is improved.

Figure 1 is a three-dimensional view of an intermediate structure 40 of a finfet in some embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be modified to implement other content. Although the figures and the content illustrate various steps, the illustrations do not limit the order of the steps, nor do they imply whether there are additional intermediate steps between the steps. Unless otherwise indicated, the sequential steps in the description are for explanatory purposes only and do not exclude the case where the individual steps are actually performed simultaneously or at least partially (not completely) overlapped when performed.

Intermediate structure 40 of finfet includes fin 46 on semiconductor substrate 42. Fins 46 may extend upward from the surface of semiconductor substrate 42. Semiconductor substrate 42 includes isolation regions 44, and fins 46 project through and above isolation regions 44. In the illustrated example, fins 46 project from between adjacent isolation regions 44. Dummy gate stack, which is located along sidewalls of fin 46 and on an upper surface of fin 46, includes an interfacial dielectric layer 62, a dummy gate layer 64 over interfacial dielectric layer 62, and a mask layer 66 over dummy gate layer 64. Source/drain regions 52a and 52b are located in regions on both sides of fin 46 (relative to the dummy gate stack). Fig. 1 also shows a reference section used in subsequent figures. The cross-section including section line a-a is along the channel region in fin 46 between source/drain regions 52a and 52b on either side. The cross-section containing section line B-B is perpendicular to the cross-section containing section line a-a and along the gate structure above the channel region in fin 46. For clarity, the subsequent figures correspond to these reference sections. The end of the following figures is labeled "A" and refers to a cross-section corresponding to line A-A for various examples of processes. The end of the following figures, labeled "B", refer to the cross-section corresponding to line B-B for various examples of processes. In some drawings, some reference numerals of elements or structures may be omitted to avoid obscuring other elements or structures.

Fig. 2A and 2B through 9A and 9B are cross-sectional views of respective intermediate structures in forming a semiconductor device in some embodiments. The semiconductor device may be a field effect transistor such as the finfet shown in fig. 1, a planar fet, a horizontal all-around gate fet, or any suitable device. As shown in fig. 2A and 2B, at least a portion of the semiconductor substrate 42 has semiconductor devices formed thereon. The semiconductor substrate 42 may be or include a bulk semiconductor, a semiconductor-on-insulator substrate, or the like, and may be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 42 may include a semiconductor element such as silicon or germanium, a semiconductor compound, a semiconductor alloy, or a combination thereof. Generally, fins 46 are formed in semiconductor substrate 42 by etching trenches in semiconductor substrate 42 using photolithography and etching processes. An insulating material, such as silicon oxide, silicon nitride, the like, multiple layers thereof, or combinations thereof, may then be deposited in the trenches and recessed to form isolation regions 44, with fins 46 protruding from between isolation regions 44.

The individual layers of interfacial dielectric layer 62, dummy gate layer 64, and mask layer 66 for the dummy gate stack may be sequentially formed or deposited by any suitable process, followed by patterning of these layers to form the dummy gate stack. For example, interfacial dielectric layer 62 may comprise or may be silicon oxide, silicon nitride, the like, or multiple layers thereof. Dummy gate layer 64 may comprise or may be silicon (amorphous silicon or polysilicon) or any suitable material. The masking layer 66 may comprise or may be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. The layers of interfacial dielectric 62, dummy gate 64, and mask layer 66 may then be patterned to form a dummy gate stack. For example, the patterning of the layer may be performed by photolithography and one or more etching processes.

As shown in fig. 2A and 2B, gate spacers 68 are formed along sidewalls of the dummy gate stack (e.g., sidewalls of interfacial dielectric layer 62, dummy gate layer 64, and mask layer 66), and gate spacers 68 are also formed on fin 46 on semiconductor substrate 42. For example, the gate spacers 68 may be formed by conformably depositing one or more layers used for the gate spacers 68, rather than isotropically etching one or more layers. The one or more layers used for the gate spacers 68 may comprise or may be silicon nitride, silicon oxynitride, silicon carbonitride, the like, multilayers thereof, or combinations thereof.

Source/drain regions 70 are then formed in fin 46 on both sides of the dummy gate stack. In some examples, source/drain regions 70 are formed by masking dummy gate stack and gate spacers 68 and implanting dopants into fin 46. In other examples, as shown, fin 46 may be etched and recessed using dummy gate stack and gate spacers 68 as a mask, and epitaxial source/drain regions 70 may be epitaxially grown in the recess. The epitaxial source/drain regions 70 may comprise or may be silicon germanium, silicon carbide, silicon phosphide, germanium, a group III-V semiconductor compound, a group II-VI semiconductor compound, or the like. Epitaxial source/drain regions 70 may be raised structures as shown with respect to fin 46. The source/drain regions 70 may be doped in-situ as the source/drain regions 70 are epitaxially grown, and/or the epitaxial source/drain regions 70 may be implanted after the epitaxial growth. The source/drain regions 70 may thus be formed by epitaxial growth on both sides of the dummy gate stack, possibly with implantation.

As shown in fig. 3A and 3B, a first interlayer dielectric layer 72 is formed on fin 46 of semiconductor substrate 42 and along gate spacers 68. Although not specifically shown, in some examples a contact etch stop layer may be conformally formed on fin 46 of semiconductor substrate 42 and along gate spacers 68, and first interlayer dielectric layer 72 may be formed on the contact etch stop layer. Generally, the etch stop layer provides a mechanism for stopping the etching process when forming contacts or vias. The contact etch stop layer may be comprised of a dielectric material and may have an etch selectivity different from that of an adjacent layer, such as the first interlayer dielectric layer 72. For example, a contact etch stop layer may be conformally deposited on fin 46, dummy gate stack, and gate spacer 68. The contact etch stop layer may comprise or may be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof. For example, a first interlevel dielectric layer 72 is then deposited over the contact etch stop layer. The first interlayer dielectric layer 72 may comprise or may be silicon oxide, a low-k dielectric material (e.g., a material having a dielectric constant lower than that of silicon oxide), silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, organosilicate glass, silicon oxycarbide, spin-on glass, spin-on polymer, carbon-silicon material, combinations thereof, the like, or combinations thereof.

After the first interlayer dielectric layer 72 is deposited, the first interlayer dielectric layer 72 may be planarized by chemical mechanical polishing or the like. The top surface of the first interlayer dielectric layer 72 may be planarized to be coplanar with the top surface of the dummy gate layer 64, i.e., the dummy gate layer 64 is exposed from the first interlayer dielectric layer 72. The planarization step may remove the masking layer 66 of the dummy gate stack (and in some cases the upper portion of the gate spacers 68). In summary, the upper surface of the dummy gate layer 64 of the dummy gate stack is exposed through the first interlayer dielectric layer 72.

As shown in fig. 4A and 4B, the dummy gate stack is removed to form recesses 74 between the gate spacers 68. Once the dummy gate layer 64 and the interfacial dielectric layer 62 of the dummy gate stack are exposed through the first interlayer dielectric layer 72, the exposed dummy gate layer 64 and the interfacial dielectric layer 62 are removed, and the removing process may be one or more etching processes.

As shown in fig. 5A and 5B, an interfacial dielectric layer 80, a gate dielectric layer 82, and a barrier layer 86 are formed in the recess 74. In some examples as shown, interfacial dielectric layer 80 is formed on fin 46 of semiconductor substrate 42 exposed by recess 74 and between gate spacers 68. For example, the interfacial dielectric layer 80 may be an oxide formed by thermal oxidation or chemical oxidation. In some examples, interfacial dielectric layer 62 of the dummy gate stack may be left in place of interfacial dielectric layer 80. In other examples, the interfacial dielectric layer 80 is formed from a native oxide formed by various process steps, such as a cleaning process. In other examples, the interfacial dielectric layer 80 may be omitted.

A gate dielectric layer 82 is conformally deposited in the recess 74. For example, gate dielectric layer 82 is deposited on interfacial dielectric layer 80, along sidewalls 73 of gate spacers 68, and on the upper surfaces of gate spacers 68 and first interlayer dielectric layer 72. Gate dielectric layer 82 and interfacial dielectric layer 80 may be described as a high-k gate stack. The gate dielectric layer 82 may be or include silicon oxide, silicon nitride, a high-k dielectric material, multiple layers thereof, or other dielectric materials. The high dielectric constant material has a dielectric constant greater than or equal to about 4, such as greater than or equal to about 7.0, and may comprise a metal oxide or metal silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or combinations thereof. Examples of some materials for gate dielectric layer 82 may include, but are not limited to, titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, or the like. In some embodiments, gate dielectric layer 82 is hafnium oxide. The deposition method for gate dielectric layer 82 may be atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique. The thickness of gate dielectric layer 82 may be between aboutTo aboutIn the meantime.

A barrier layer 86 is conformally deposited over the gate dielectric layer 82. The barrier layer 86 may comprise or may be tantalum nitride, tantalum silicon nitride, tantalum carbon nitride, tantalum aluminum nitride, titanium silicon nitride, titanium carbonitride, titanium aluminum nitride, the like, or combinations thereof, and may be deposited by atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or the like. In some embodiments, the barrier layer 86 is titanium silicon nitride.

As shown in fig. 5A and 5B, a dummy layer 88 is conformally deposited on the barrier layer 86. A high density of interface and bulk defects may be found in gate dielectric layer 82 during the formation of gate dielectric layer 82 or subsequent high temperature processes. These high density interface and bulk defects increase carrier scattering, degrade mobility, and reduce drain current for subsequent gates. Various embodiments may provide a compliant dummy layer 88 on the gate dielectric layer 82, which may address these issues. Dummy layer 88 contains passivation species 87 and may drive diffusion of dopant species 87 into gate dielectric layer 82 to passivate interface and/or bulk defects of any of the layers comprising the replacement gate structure. A subsequent thermal process, such as a rapid thermal anneal process, may be performed to assist in the incorporation of the passivation species 87 into the gate dielectric layer 82. The compliance of dummy layer 88 helps to ensure that the passivation species can be uniformly distributed throughout gate dielectric layer 82, conformably deposited on interfacial dielectric layer 80, along sidewalls 73 of gate spacers 68, and on the upper surfaces of gate spacers 68 and first interlayer dielectric layer 72. For example, the passivating species in the gate dielectric layer 82 may passivate the interfacial dangling bonds and the bulk oxygen vacancies in or on the gate dielectric layer 82 to effectively reduce the defect density, thereby reducing the oxide leakage current, improving the threshold voltage stability, and improving the device performance.

The examples described herein use fluorine, deuterium, or both as dopant or passivation species, and thus the dummy layer 88 may include fluorine, deuterium, or both. The description relating to fluorine or deuterium may be applied more broadly to any suitable passivating species. In some embodiments, dummy layer 88 is conformally deposited over barrier layer 86. The dummy layer may be in-situ doped with dopants or passivating species during deposition or formation. For example, fluorine and/or deuterium may be incorporated into the dummy layer 88 during deposition of the dummy layer 88. A dummy layer 88 containing fluorine, deuterium, or both may be deposited. Inset 89 of fig. 5A is an enlarged view of a portion of passivation species 87 (shown as black squares) formed in the dummy layer 88. Dummy layer 88 may comprise or may be a silicon layer, such as a polysilicon layer or an amorphous silicon layer containing passivation species 87. In some embodiments, the dummy layer 88 is an amorphous silicon layer containing a passivation species 87.

The deposition method for dummy layer 88 may be a chemical vapor deposition process (e.g., thermal chemical vapor deposition, cyclic chemical vapor deposition, plasma-enhanced chemical vapor deposition, or cyclic plasma-enhanced chemical vapor deposition), an atomic layer deposition process (e.g., thermal atomic layer deposition, plasma-enhanced atomic layer deposition, or radical-enhanced atomic layer deposition), or any other deposition technique suitable for forming a conformal film. In various embodiments, the dummy layer 88 may have a thickness of between aboutTo aboutBetween, such as aboutTo aboutIn the meantime. The thickness of the dummy layer 88 affects the amount of fluorine or deuterium that can diffuse from the dummy layer 88 into the gate dielectric layer 82, and the thickness of the dummy layer 88 determines the volume of the dummy layer 88 and the concentration of fluorine and/or deuterium in the dummy layer 88. The greater the amount of fluorine or deuterium available for diffusion, the greater the amount of fluorine or deuterium that can diffuse into the gate dielectric layer 82.

Dummy layer 88 may be formed by exposing the substrate surface of intermediate structure 40 of the finfet to a gas mixture of a silicon-containing precursor and a dopant gas at an elevated temperature. In the embodiments of the present invention, the term "substrate surfaceMay include an exposed surface of a film/layer or portion thereof deposited on a substrate, such as semiconductor substrate 42, and the exposed surface of the newly deposited film/layer may also serve as the substrate surface prior to any subsequent processing. In this example, the substrate surface at this stage of the process may be referred to as the exposed surface of dummy layer 88. Suitable silicon-containing precursors may include silanes, halogenated silanes, or any combination of the above. The silane may comprise Silane (SiH)₄) With higher silanes (Si)_xH_(2x+2)) Such as disilane, trisilane, or butylsilane. The halogenated silane may include, but is not limited to, a chlorinated silane such as monochlorosilane, dichlorosilane, trichlorosilane, tetrachlorosilane, hexachlorodisilane, or octachloropropylsilane. In some embodiments, the silicon-containing precursor may employ an organosilane (R)_ySi_xH_(2x+2-y)Where R is independently methyl, ethyl, propyl, or butyl), such as methylsilane, dimethylsilane, ethylsilane, methyldisilane, hexamethyldisilane, tris (dimethylamino) silane, or a combination of any of the foregoing.

The dopant gas may be a fluorine-containing gas, a deuterium-containing gas, or both, depending on the dopant desired for the dummy layer 88. Suitable fluorine-containing gases may include, but are not limited to, silicon tetrafluoride, fluorine, nitrogen trifluoride, tetraflurodiamide, trifluoromethane, fluorocarbons (C)_xF_y，x>1, and y>1) An analog, or any suitable combination of the foregoing. In some examples, the fluorine-containing gas is free of carbon. In some embodiments, the fluorine-containing gas is silicon tetrafluoride. For some applications, silicon tetrafluoride is advantageous. Since silicon tetrafluoride has the least etching capability at high temperatures compared to other fluorine-containing gases. Suitable deuterium-containing gases may include, but are not limited to, deuterium gas, tetradeuterated silane, hexadeuterated disilane, dichlorodideuterized silane, trichlorodeuterated silane, chlorotrieuterized silane, or any suitable combination of the foregoing. In some embodiments, the deuterium containing gas is silicon tetradeuteride.

In some embodiments, the silicon-containing precursor is flowed into the process chamber at a first volumetric flow rate, and the process chamber has an intermediate structure 40 of a finfet. The dopant gas flows into the process chamber at a second volumetric rate. The ratio between the first volumetric flow rate and the second volumetric flow rate may be controlled between about 8: 1 to about 20: 1, such as between about 10: 1 to about 18: 1, for example between about 12: 1 to about 15: 1.

In some embodiments, the dummy layer 88 is fluorine-doped silicon deposited by a chemical vapor deposition process. An example of a chemical vapor deposition process may include providing a wafer, such as a semiconductor substrate 42, into a chemical vapor deposition chamber maintained at a temperature between about 350 c and about 550 c, such as between about 400 c and about 450 c, and a chamber pressure between about 1mTorr and about 100Torr, such as between about 1.5mTorr and about 50 mTorr. A silicon-containing precursor, such as silane, and a fluorine-containing precursor, such as silicon tetrafluoride, may be introduced into the chemical vapor deposition chamber simultaneously or sequentially. The silicon-containing precursor and the fluorine-containing precursor may be pre-mixed and the gas mixture may be introduced into the chemical vapor deposition chamber, in some examples, the silicon-containing precursor and the fluorine-containing precursor may be introduced separately into the chemical vapor deposition chamber. The process time for fluorine may be between about 2 seconds and about 180 seconds, such as between about 15 seconds and about 60 seconds, for example between about 20 seconds and about 35 seconds. Generally, the time and temperature at which dummy layer 88 is formed in the intermediate structure affects the amount of fluorine that diffuses into gate dielectric layer 82. Higher temperature processes and/or longer time processes may increase the amount of fluorine diffused into the gate dielectric layer 82. This process may be repeated for a number of cycles until the dummy layer 88 reaches a desired thickness.

Varying the thickness of dummy layer 88 may increase or decrease the amount of passivation species (e.g., fluorine or deuterium) that may diffuse into gate dielectric layer 82, and thus increase or decrease the amount of passivation species that may diffuse into gate dielectric layer 82. Similarly, increasing or decreasing the thickness of the barrier layer 86 also increases or decreases the ability of passivation species to diffuse through the barrier layer 86 and increases or decreases the amount of passivation species that diffuses into the gate dielectric layer 82. In various embodiments, the dummy layer 88 may have a thickness of between aboutTo aboutAnd the thickness of the barrier layer 86 may be between aboutTo aboutIn the meantime.

In some embodiments, the silicon-containing precursor and the fluorine-containing precursor are introduced sequentially, and the reactants may be introduced into the chemical vapor deposition chamber in any order. For example, a pulse of a silicon-containing precursor may be introduced followed by a pulse of a fluorine-containing precursor, or vice versa. In any case, a purge gas (e.g., an inert gas such as argon) and/or a vacuum may be introduced between the silicon-containing precursor and the fluorine-containing precursor. In this example, the silicon-containing precursor may be introduced into the chemical vapor deposition chamber with a pulse of between about 2 seconds and about 30 seconds, such as between about 5 seconds and about 20 seconds. A purge gas and/or a vacuum is then introduced for between about 5 seconds and about 10 seconds. The fluorine-containing precursor is then introduced into the chemical vapor deposition chamber with a pulse of between about 1 second and about 10 seconds, such as between about 2 seconds and about 8 seconds, for example between about 3 seconds and about 5 seconds. This process may be repeated for a number of cycles until the dummy layer 88 reaches a predetermined thickness.

In some embodiments, dummy layer 88 is fluorine-doped silicon deposited by an atomic layer deposition process. Examples of atomic layer deposition processes may include: a wafer, such as a semiconductor substrate 42, is provided to an atomic layer deposition chamber and the chamber temperature is maintained between about 220 c and about 450 c (e.g., between about 250 c and about 400 c) and the chamber pressure is maintained between about 1mTorr to about 10Torr (e.g., between about 1.5mTorr to about 5 Torr). An atomic layer deposition process may include sequentially introducing pulses of a first precursor, such as a silicon-containing precursor, and a second precursor, such as a dopant gas. For example, a cycle in which the first precursor and the second precursor are introduced sequentially may include a pulse of the first precursor followed by a pulse of purge gas and/or an evacuation,Followed by a pulse of a second precursor, and then a pulse of a purge gas and/or an evacuation. Similarly, the cycle may be repeated until the dummy layer 88 reaches a predetermined thickness (e.g., between aboutTo aboutIn between).

In a chemical vapor deposition or atomic layer deposition process, a plasma may be employed to facilitate dissociation of the precursor into species or radicals. In a chemical vapor deposition or atomic layer deposition process, electromagnetic power (e.g., radio frequency power) may be coupled to a gas mixture (e.g., a silicon-containing precursor and a fluorine-containing precursor) or pulses of individual precursors to generate a plasma. The rf power may be turned off and only the purge gas supplied to the process chamber. If a plasma is used, the RF power may be operated at a frequency of between about 1MHz and about 60MHz, such as about 13.56MHz, between about 5 watts and about 5000 watts, such as between about 150 watts and about 1000 watts. The plasma power density may be between about 1 watt/cm²To about 10 watts/cm²Between, for example, about 2 watts/cm²To about 8 watts/cm²In the meantime.

It will be appreciated by those skilled in the art that the above-described processes and parameters may also be applied to form the dummy layer 88 of deuterium doped silicon. The above parameters may vary depending on the application and/or the size of the individual features on the surface of the semiconductor device.

After conformably depositing dummy layer 88 on barrier layer 86, one or more thermal processes may be performed to drive passivation species 87 from dummy layer 88 to diffuse into gate dielectric layer 82. The gate dielectric layer 82 thereafter comprises fluorine, deuterium, or both. In this manner, a conformal fluorinated or deuterated gate dielectric layer 82 may be formed. Passivation species 87 may fill oxygen vacancies in gate dielectric layer 82 and/or link to dangling bonds to passivate gate dielectric layer 82. Charge trapping and interface charge scattering can be reduced. Specifically, as compared to conventional ion implantation processes (in which the sides and bottom of the gate dielectric layer do not receive the full dose of dopant implantation due to the three-dimensional geometry of the finfet device), fluorine and/or deuterium may be more conformally and more blanket doped into the gate dielectric layer 82 as fluorine and/or deuterium diffuses from the conformal dummy layer 88 into the gate dielectric layer 82. The conventional ion implantation process is not effective in reducing defects in the gate stack along the sides or bottom of the gate dielectric layer.

As shown in fig. 6A and 6B, the intermediate structure 40 of the finfet at an intermediate stage of the process, wherein the passivation species 87 has diffused from the dummy layer 88 into the gate dielectric layer 82. The main passivating species 87 may remain in the dummy layer 88 at a concentration that decreases from the interface between the dummy layer 88 and the barrier layer 86 toward the gate dielectric layer 82, depending on the process time. In some examples, passivation species 87 may diffuse through gate dielectric layer 82 after one or more thermal processes. An inset 91 in fig. 6A is an enlarged view of a portion of the dummy layer 88 and barrier layer 86 in some examples having a detectable amount of passivation species 87 after one or more thermal processes.

The gate dielectric layer 82 typically contains a lower amount of passivation species 87 than the amount of passivation species 87 in the dummy layer 88, since the barrier layer 86 and dummy layer 88 may trap or retain a small portion of the passivation species. In some embodiments, the gate dielectric layer 82 may include fluorine or deuterium (passivation species 87) at a concentration of between about 1 atomic% and about 15 atomic%, such as between about 3 atomic% and about 12 atomic%, for example between about 6 atomic% and about 10 atomic%. In some embodiments, the gate dielectric layer 82 may comprise a mixture of fluorine and deuterium, each at a respective concentration between about 1 atomic% and about 15 atomic%. If the fluorine or deuterium concentration in the gate dielectric layer 82 is less than about 1 atomic%, the effect of passivating the gate dielectric layer 82 is insufficient. Controlling the concentration of fluorine or deuterium in gate dielectric layer 82 to between about 1 atomic% and about 15 atomic% passivates interface and/or substrate defects. Fluorine or deuterium concentrations greater than 15 atomic percent may be problematic because too much fluorine and/or deuterium may displace and react with oxygen atoms in the lattice structure of the gate dielectric layer 82. The interfacial dielectric layer 80 may become thicker, thereby reducing the dielectric constant of the interfacial dielectric layer 80 and/or the gate-to-channel capacitance, and/or causing unwanted effects on device electrical performance.

In gate dielectric layer 82, the concentration of passivation species 87 may be graded along the thickness of gate dielectric layer 82. For example, portions of the gate dielectric layer 82 inward to the gate replacement structure (such as portions away from the respective gate spacers 68 having vertical portions of the gate dielectric layer 82 thereon; and portions away from the semiconductor substrate 42 having vertical portions of the gate dielectric layer 82 thereon) may have a maximum concentration in the gate dielectric layer 82. As gate dielectric layer 82 moves away from the portion having the greatest concentration (e.g., away in an outward direction of the replacement gate structure), the concentration of passivation species 87 also decreases. The concentration gradient of the passivating species may result from diffusion caused by one or more of the thermal processes described herein.

In some embodiments, the passivating species 87 may also diffuse into the top of the interfacial dielectric layer 80. Inset 93 in fig. 6A is a partial magnified view showing that a small amount of passivation species 87 (represented by black squares) is present in the top of interfacial dielectric layer 80 after one or more thermal processes. Passivation species 87 may diffuse into interfacial dielectric layer 80 to form surface region 95 having a first thickness T1 and interfacial dielectric layer 80 having a second thickness T2, and the ratio of first thickness T1 to second thickness T2 (T1: T2) is between about 1: 10to about 1: 60, such as about 1: 20 to about 1: between 40, for example about 1: 30.

the one or more thermal processes may be in-situ processes, such as performing one or more thermal processes in the same process chamber used to form dummy layer 88 while maintaining a vacuum in the process chamber. In some examples, the wafer (e.g., finfet intermediate structure 40) may be transferred to another process chamber for performing one or more thermal processes, and the other process chamber is fluidly connected to the process chamber in which dummy layer 88 is deposited. During the above transfer step, the wafer is maintained under vacuum. In an example of a thermal process, the temperature is between about 300 ℃ to about 850 ℃, such as between about 350 ℃ to about 450 ℃, and for between about 15 seconds to about 240 seconds, such as between about 60 seconds to about 100 seconds.

In some embodiments, the thermal process is a rapid thermal annealing process, such as spike annealing, pulse annealing, laser annealing, or flash assist annealing. In this example, the time of the rapid thermal annealing process may be on the order of microseconds, such as between about 0.1 microseconds and about 500 microseconds, for example between about 1 microsecond and about 100 microseconds. In some examples, the time for the rapid thermal annealing process may be between about 1 second to about 10 seconds. The temperature of the rapid thermal annealing process may be between about 800 ℃ to about 1200 ℃, such as about 900 ℃. The rapid thermal annealing process has an advantage in that the process temperature and time can be precisely controlled without damaging the semiconductor device.

As shown in fig. 7A and 7B, the dummy layer 88 is removed after the thermal process. The dummy layer 88 may be removed by one or more etching processes and cleaning processes. For example, dummy layer 88 may be removed by an etch process that is selective to the material of dummy layer 88. For example, the one or more etching processes may be an isotropic etching process such as a wet etch using phosphoric acid, or any suitable etching process. After the dummy layer 88 is removed, the underlying layer, such as the barrier layer 86, is exposed.

As shown in fig. 8A and 8B, a first work function adjusting layer 100, a second work function adjusting layer 102, a barrier/adhesion layer 104, and a gate metal fill 106 are sequentially formed on the barrier layer 86. The first work function adjusting layer 100 may be conformably deposited on the barrier layer 86. The first work function adjusting layer 100 may comprise or may be titanium nitride, titanium silicon nitride, titanium carbonitride, titanium aluminum nitride, tantalum silicon nitride, tantalum carbonitride, tungsten nitride, tungsten carbide, tungsten carbonitride, cobalt, platinum, the like, or combinations thereof, and may be deposited by atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique. The thickness of the first work function adjusting layer 100 may be between aboutTo aboutIn the meantime. Second oneThe work function adjusting layer 102 may be conformally deposited on the first work function adjusting layer 100. The second work function adjusting layer 102 may comprise or may be titanium aluminum carbide, titanium aluminum alloy, tantalum aluminum carbide, the like, or combinations thereof, and may be deposited by atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique. The thickness of the second work function adjusting layer 102 may be between aboutTo aboutIn the meantime. In some examples, the first and second work function adjusting layers 100, 102 may be omitted. Other examples may have other arrangements of work function adjusting layers to achieve the desired performance of the device to be formed. For example, any number of work function layers of various materials and/or thicknesses may be employed. In some examples, the p-type field effect transistor and the n-type field effect transistor may have different work function adjusting layers.

A barrier/adhesion layer 104 is conformally deposited over the second work function adjusting layer 102. The barrier/adhesion layer 104 may comprise or may be titanium nitride, titanium silicon nitride, titanium carbonitride, titanium aluminum nitride, tantalum silicon nitride, tantalum carbonitride, tungsten nitride, tungsten carbide, tungsten carbonitride, the like, or combinations thereof, and may be deposited by atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, or any suitable deposition technique. The thickness of the barrier/adhesion layer 104 may be between aboutTo aboutIn the meantime. A gate metal fill layer 106 is then deposited over the barrier/adhesion layer 104. The gate metal fill 106 may fill the remaining recess 74, i.e., where the dummy gate stack is removed. The gate metal fill layer 106 may be or include a metal-containing material, such as tungsten, cobalt, ruthenium, aluminum, copper, or combinations thereofOr combinations thereof. The deposition method of the gate metal filling layer 106 may be atomic layer deposition, plasma enhanced chemical vapor deposition, molecular beam deposition, physical vapor deposition, or any suitable deposition technique.

Since the gate metal fill layer 106, the barrier/adhesion layer 104, the second work function tuning layer 102, and the first work function tuning layer 100 are formed after the gate dielectric layer 82 is fluorinated or deuterated, these layers may be substantially free of fluorine or deuterium (e.g., free of trace amounts of fluorine or deuterium). Since these layers do not have significant fluorine content (and are not significantly affected by fluorine), the workfunction of the transistor can be more easily adjusted. Thus, transistor performance may be increased, such as by improving threshold voltage. In some examples, the gate metal fill layer 106, the barrier/adhesion layer 104, the second work function adjustment layer 102, and the first work function adjustment layer 100 may have insubstantial amounts of fluorine and/or deuterium resulting from natural diffusion reactions between layers such as the barrier layer 86 and the gate dielectric layer 82.

As shown in fig. 9A and 9B, the excess portions of the gate metal fill layer 106, the barrier/adhesion layer 104, the second work function tuning layer 102, the first work function tuning layer 100, the barrier layer 86, and the gate dielectric layer 82 over the upper surfaces of the first interlayer dielectric layer 72 and the gate spacers 68 are removed. For example, a planarization process, such as chemical mechanical polishing, may be employed to remove portions of the gate metal fill layer 106, the barrier/adhesion layer 104, the second work function tuning layer 102, the first work function tuning layer 100, the barrier layer 86, and the gate dielectric layer 82 over the upper surfaces of the first interlayer dielectric 72 and the gate spacers 68. A replacement gate structure comprising the gate metal fill layer 106, the barrier/adhesion layer 104, the second work function adjustment layer 102, the first work function adjustment layer 100, the barrier layer 86, and the gate dielectric layer 82 (e.g., a fluorinated or deuterated gate dielectric) may thus be formed.

As shown in fig. 9A and 9B, a second interlayer dielectric layer 110 is formed. A second interlayer dielectric layer 110 is deposited over the first interlayer dielectric layer 72, the replacement gate structure, and the gate spacers 68. Between the first interlayer dielectric layer 72 and the second interlayer dielectric layer 110, an etch stop layer may be formed. For example, an etch stop layer may be deposited on the first interlayer dielectric layer 72, the replacement gate structure, and the gate spacers 68. For example, a second interlayer dielectric layer 110 is then deposited over the etch stop layer. The etch stop layer and the second interlayer dielectric layer 110 may be or comprise the same or similar materials and may be deposited using any acceptable technique, such as those described above for forming the contact etch stop layer and the first interlayer dielectric layer 72, respectively. After the second interlayer dielectric layer 110 is deposited, the second interlayer dielectric layer 110 may be planarized by chemical mechanical polishing or the like.

As shown in fig. 9A and 9B, a conductive structure is formed through the second interlayer dielectric layer 110 and the first interlayer dielectric layer 72 to the source/drain region 70. An opening is formed through the second interlayer dielectric layer 110 and the first interlayer dielectric layer 72. Each opening exposes a respective source/drain region 70. The method of forming the opening may be, for example, a suitable photolithography and etching process. A liner layer 112 may be formed in the opening. Liner layer 112 may be conformally deposited along the sidewalls of the opening and the upper surface of source/drain region 70. Liner layer 112 may be a diffusion barrier layer, adhesion layer, or the like. Liner layer 112 may comprise or may be titanium, titanium nitride, tantalum nitride, or the like, and may be deposited by any suitable deposition technique. An annealing process may be performed to facilitate a reaction between at least respective portions of the liner layer 112 and the source/drain regions 70 to form silicide regions 114 in the respective source/drain regions 70. A conductive material 116 is then formed on the pad layer 112 in the opening. The conductive material 116 may be or include a metal such as cobalt, tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or combinations thereof, and may be deposited by any suitable deposition technique. A planarization process, such as chemical mechanical polishing, may be performed to remove the excess conductive material 116 and the pad layer 112 from the top surface of the second interlayer dielectric 110. The remaining spacers 112, silicide regions 114, and conductive material 116 form conductive structures to the respective source/drain regions 70.

Embodiments of the present invention relate to methods of forming gate structures of devices, such as replacement gate processes and devices formed thereby. Some examples conformably form a dummy layer containing a passivating species (e.g., fluorine or deuterium) on the gate dielectric layer after deposition of the gate dielectric layer. The thermal process may allow the passivation species to diffuse from the dummy layer into the gate dielectric layer to passivate the gate dielectric layer. The fluorinated or deuterated gate dielectric may fill oxygen vacancies in the gate dielectric and/or the channel in the semiconductor substrate and bond dangling bonds to the surface of the gate dielectric and/or the channel in the semiconductor substrate to passivate the gate dielectric. Fluorinated or deuterated gate dielectric layers can reduce charge trapping and interface charge scattering. As described above, the diffusion of fluorine or deuterium from the conformal dummy layer into the gate dielectric layer allows for more conformal and more covering doping of fluorine or deuterium into the gate dielectric layer, which is particularly advantageous for smaller technology nodes (e.g., 7nm or less), and particularly advantageous for three-dimensional technologies such as finfet. Improved fluorination or deuteration compliance, reduced time-dependent dielectric breakdown degradation, and increased reliability. Furthermore, since some work function adjusting layers may be formed after fluorinating or deuterating the gate dielectric layer, the work function of the transistor may be more easily adjusted because these layers do not have significant fluorine content (and are not significantly affected by fluorine). Thus, transistor performance may be increased, such as by improving threshold voltage.

One embodiment is a method for semiconductor processing. The method includes conformably forming a gate dielectric layer on a fin extending from a substrate, the gate dielectric layer along sidewalls of gate spacers on the fin; conformably depositing a dummy layer over the gate dielectric layer using a deposition process employing a silicon-containing precursor and a dopant gas comprising fluorine, deuterium, or a combination thereof, wherein the deposited dummy layer comprises a dopant of fluorine, deuterium, or a combination thereof; performing a thermal process to drive dopants from the dummy layer into the gate dielectric layer; removing the dummy layer; and forming one or more metal-containing layers on the gate dielectric layer.

In some embodiments, the dummy layer is an amorphous silicon layer.

In some embodiments, the gate dielectric layer comprises a fluorine concentration of between about 1 atomic% and about 15 atomic% after the metal-containing layer is formed.

In some embodiments, the gate dielectric layer comprises deuterium at a concentration of between about 1 atomic% and about 15 atomic% after the metal-containing layer is formed.

In some embodiments, after forming the metal-containing layer, the gate dielectric layer comprises fluorine and deuterium, each at a respective concentration of between about 1 atomic% and about 15 atomic%.

In some embodiments, the dummy layer is formed by sequentially exposing the substrate to (i) pulses of a gas mixture of a silicon-containing precursor and a dopant gas, and (ii) pulses of a purge gas until the dummy layer reaches a predetermined thickness.

In some embodiments, the dummy layer is formed by sequentially exposing the substrate to a pulse of a silicon-containing precursor, a pulse of a purge gas, and a pulse of a dopant gas until the dummy layer reaches a predetermined thickness.

In some embodiments, the silicon-containing precursor comprises silane, halogenated silane, or a combination thereof, and the dopant gas comprises silicon tetrafluoride, tetradeuterated silane, or a combination thereof.

Another embodiment is a method for semiconductor processing. The method includes forming an interfacial dielectric layer along a surface of a fin extending from a substrate; forming a gate dielectric layer on the interfacial dielectric layer; conformably depositing a dummy layer on the gate dielectric layer using a deposition process employing a silicon-containing precursor and a dopant gas comprising fluorine, deuterium, or a combination thereof, the deposited dummy layer comprising a passivating species; driving a passivating species from the dummy layer into the gate dielectric layer and the interfacial dielectric layer to form a surface region containing the passivating species; removing the dummy layer; and forming a metal gate on the gate dielectric layer.

In some embodiments, the method further comprises forming a barrier layer between the gate dielectric layer and the dummy layer.

In some embodiments, the interfacial dielectric layer has a first thickness and the surface region has a second thickness, and a ratio between the second thickness and the first thickness is between 1: 20 to 1: 40 of the total weight of the powder.

In some embodiments, the dummy layer is a fluorine-doped amorphous silicon layer deposited by a cyclic chemical vapor deposition process or an atomic layer deposition process.

In some embodiments, the dummy layer is deuterium-doped amorphous silicon and the deposition method is a cyclic chemical vapor deposition process or an atomic layer deposition process.

In some embodiments, the gate dielectric layer comprises a concentration of the passivation species between about 1 atomic% and about 15 atomic% after the metal gate is formed.

In some embodiments, the step of driving the passivation species from the dummy layer into the gate dielectric layer and the interfacial dielectric layer is a rapid thermal anneal.

Yet another embodiment is a structure. The structure includes a substrate having fins extending from the substrate; and a gate structure on the fin. The gate structure includes: a gate dielectric layer containing deuterium. The peak concentration of deuterium in the gate dielectric layer in regions away from the fin is between 1 atomic% and 15 atomic%. The graded concentration of deuterium in the gate dielectric layer decreases from the peak concentration towards the fin.

In some embodiments, the structure further comprises a work function adjusting layer on the gate dielectric layer; and a gate metal fill layer over the work function adjusting layer, wherein at least one of the work function adjusting layer and the gate metal fill layer is substantially free of fluorine.

In some embodiments, the gate structure is located between a first gate spacer and a second gate spacer located on the fin, the gate dielectric also along respective sidewalls of the first gate spacer and the second gate spacer, and the gate structure further comprises a barrier layer on the gate dielectric, a work function adjusting layer on the barrier layer, a barrier/adhesion layer on the work function adjusting layer, and a gate metal fill layer on the barrier/adhesion layer.

In some embodiments, the barrier layer comprises titanium silicon nitride or tantalum silicon nitride.

In some embodiments, the above structure further comprises: an interfacial dielectric layer along a surface of the fin; a gate dielectric layer on the interfacial dielectric layer; and the interface dielectric layer has a surface region containing deuterium, wherein the surface region has a first thickness, the interface dielectric layer has a second thickness, and the ratio of the first thickness to the second thickness is 1: 20 to 1: 40 of the total weight of the powder.

The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that these equivalents may be substituted and/or modified without departing from the spirit and scope of the present invention.