阅读说明：本技术 集成电路的逻辑瓦片的时钟分配和生成体系架构及其操作方法 (Clock distribution and generation architecture for logic tiles of an integrated circuit and method of operation thereof ) 是由 成·C·王 N·U·纳图 于 2018-06-02 设计创作，主要内容包括：包含以行和列的阵列布置的逻辑瓦片阵列的集成电路。该逻辑瓦片阵列包括：第一逻辑瓦片,以接收第一外部时钟信号,其中,第一多个逻辑瓦片中的每个逻辑瓦片使用以下来生成瓦片时钟：(i)第一外部时钟信号或(ii)来自第一多个的逻辑瓦片的多个输出时钟路径中的一个输出时钟路径的第一外部时钟信号的延迟版本；以及第二逻辑瓦片,以接收第二外部时钟信号,其中,第二多个逻辑瓦片中的每个逻辑瓦片使用以下来生成瓦片时钟：(i)第二外部时钟信号或(ii)来自第二多个的逻辑瓦片的多个输出时钟路径中的一个输出时钟路径的第二外部时钟信号的延迟版本,其中,第一外部时钟信号和第二外部时钟信号是相同的时钟信号。(An integrated circuit including an array of logic tiles arranged in an array of rows and columns. The array of logical tiles includes: a first logical tile to receive a first external clock signal, wherein each logical tile of the first plurality of logical tiles generates a tile clock using: (i) a first external clock signal or (ii) a delayed version of the first external clock signal from one of a plurality of output clock paths of a logic tile of the first plurality; and a second logical tile to receive a second external clock signal, wherein each logical tile of the second plurality of logical tiles generates a tile clock using: (i) a second external clock signal or (ii) a delayed version of the second external clock signal from one of a plurality of output clock paths of a logic tile of the second plurality, wherein the first external clock signal and the second external clock signal are the same clock signal.)

1. An integrated circuit, comprising:

an array of logic tiles arranged in an array of rows and columns, wherein, during operation, each logic tile is configurable to connect to at least one logic tile adjacent thereto, and wherein each logic tile of the array of logic tiles comprises:

at least one input clock path, wherein the input clock path comprises circuitry configurable to receive an input clock signal;

a plurality of output clock paths, wherein each output clock path comprises circuitry configurable to send a tile output clock signal to one or more logic tiles of the array of logic tiles adjacent thereto,

tile clock generation circuitry, coupled to the input clock path, configurable to generate a tile clock having an offset using the input clock signal, wherein the offset of the tile clock is balanced with respect to a tile clock generated by the tile clock generation circuitry for each logic tile of the array of logic tiles, an

Circuitry coupled to the tile clock generation circuitry to perform operations using or based on the tile clock; and is

Wherein the logical tile array comprises:

a first logic tile to receive a first external clock signal at an input of an associated at least one input clock path, wherein each logic tile of a first plurality of logic tiles of an array of logic tiles generates a tile clock using: (i) a first external clock signal received by the first logic tile, or (ii) a delayed version of the first external clock signal from one of the plurality of output clock paths of a logic tile of the first plurality of logic tiles, an

A second logical tile to receive a second external clock signal at an input of the associated at least one input clock path, wherein each logical tile of a second plurality of logical tiles of the array of logical tiles generates the tile clock using: (i) a second external clock signal received by a second logic tile, or (ii) a delayed version of the second external clock signal from one of the plurality of output clock paths of a logic tile of a second plurality of logic tiles,

wherein:

a logical tile in the first plurality of logical tiles is different from a logical tile in the second plurality of logical tiles, and

the first external clock signal and the second external clock signal are the same clock signal.

2. The integrated circuit of claim 1, wherein each of the plurality of output clock paths of each logic tile of the array of logic tiles includes at least one U-turn circuit.

3. The integrated circuit of claim 2, wherein the at least one of the U-turn circuits comprises one or more buffers.

4. The integrated circuit of claim 1 wherein a first logic tile is located on a perimeter of a first side of the array of logic tiles and a second logic tile is located on a perimeter of a second side of the array of logic tiles.

5. The integrated circuit of claim 4 wherein the first side of the array of logic tiles is opposite the second side of the array of logic tiles.

6. The integrated circuit of claim 5 wherein a first logical tile is located in a first column on a first side of the array of logical tiles and a second logical tile is located in a last column on a second side of the array of logical tiles.

7. The integrated circuit of claim 1, wherein the tile clock generation circuitry for each logic tile includes one or more buffers.

8. The integrated circuit of claim 1 wherein at least one of the plurality of logic tiles is rectangular in shape.

9. An integrated circuit, comprising:

an array of logic tiles arranged in an array of rows and columns, wherein, during operation, each logic tile is configurable to connect to at least one logic tile adjacent thereto, and wherein each logic tile of the array of logic tiles comprises:

at least one input clock path, wherein the input clock path comprises circuitry configurable to receive an input clock signal;

a plurality of output clock paths, wherein each output clock path comprises circuitry configurable to send a tile output clock signal to one or more logic tiles of the array of logic tiles adjacent thereto,

tile clock generation circuitry, coupled to the input clock path, configurable to generate a tile clock having an offset using the input clock signal, wherein the offset of the tile clock is balanced with respect to a tile clock generated by the tile clock generation circuitry for each logic tile of the array of logic tiles, an

Circuitry coupled to the tile clock generation circuitry to perform operations using or based on the tile clock; and is

Wherein the array of logic tiles comprises a plurality of columns of logic tiles and a plurality of rows of logic tiles, including:

a first column of logical tiles to receive a first external clock signal, wherein each logical tile of the first column of logical tiles receives the first external clock signal at an input of an associated at least one input clock path, and wherein each logical tile of a first plurality of logical tiles of the array of logical tiles generates a tile clock using: (i) a first external clock signal received by the first logic tile, or (ii) a delayed version of the first external clock signal from one of the plurality of output clock paths of a logic tile of the first plurality of logic tiles, an

A second column of logical tiles to receive a second external clock signal, wherein each logical tile of the second column of logical tiles receives the second external clock signal at an input of the associated at least one input clock path, and wherein each logical tile of a second plurality of logical tiles of the array of logical tiles generates a tile clock using: (i) a second external clock signal received by a second logic tile, or (ii) a delayed version of the second external clock signal from one of the plurality of output clock paths of a logic tile of a second plurality of logic tiles, wherein:

a logical tile in the first plurality of logical tiles is different from a logical tile in the second plurality of logical tiles, and

the first external clock signal and the second external clock signal are the same clock signal.

10. The integrated circuit of claim 9 wherein a first column of logic tiles is located on a perimeter of a first side of the array of logic tiles and a second column of logic tiles is located on a perimeter of a second side of the array of logic tiles.

11. The integrated circuit of claim 10 wherein the first side of the array of logic tiles is opposite the second side of the array of logic tiles.

12. The integrated circuit of claim 9, wherein:

wherein each logical tile of the first plurality of logical tiles of the array of logical tiles further generates a tile clock using: (i) a second external clock signal received by the first logic tile, or (ii) a delayed version of the second external clock signal,

wherein each logical tile of a second plurality of logical tiles of the array of logical tiles further generates a tile clock using: (i) a first external clock signal received by the first logic tile, or (ii) a delayed version of the first external clock signal.

13. The integrated circuit of claim 12, wherein:

the tile clock generation circuitry of each of the first and second plurality of logic tiles of the array of logic tiles electrically shorts (i) the first external clock signal or the delayed version of the first external clock signal received by the first logic tile and (ii) the second external clock signal or the delayed version of the second external clock signal received by the first logic tile to generate the tile clock for the logic tile.

14. The integrated circuit of claim 12, wherein:

the tile clock generation circuitry of each of the first and second pluralities of logic tiles of the array of logic tiles includes a multiplexer that electrically shorts (i) the first external clock signal or the delayed version of the first external clock signal received by the first logic tile and (ii) the second external clock signal or the delayed version of the second external clock signal received by the first logic tile to generate the tile clock for the logic tile.

15. The integrated circuit of claim 9, wherein each of the plurality of output clock paths of each logic tile of the array of logic tiles includes at least one U-turn circuit.

16. The integrated circuit of claim 9 wherein at least one of the plurality of logic tiles is rectangular in shape.

17. An integrated circuit, comprising:

an array of logic tiles arranged in an array of rows and columns, wherein, during operation, each logic tile is configurable to connect to at least one logic tile adjacent thereto, and wherein each logic tile of the array of logic tiles comprises:

at least one input clock path, wherein the input clock path comprises circuitry configurable to receive an input clock signal;

a plurality of output clock paths, wherein each output clock path comprises circuitry configurable to send a tile output clock signal to one or more logic tiles of the array of logic tiles adjacent thereto,

tile clock generation circuitry, coupled to the input clock path, configurable to generate a tile clock with an offset using the input clock signal and a path that generates an amount of delay of the input clock signal to provide a zero offset between the tile clocks of each logic tile of the array of logic tiles, an

Circuitry coupled to the tile clock generation circuitry to perform operations using or based on the tile clock; and is

Wherein the logical tile array comprises:

a first logic tile to receive a first external clock signal at an input of an associated at least one input clock path, wherein each logic tile of a first plurality of logic tiles of an array of logic tiles generates a tile clock using: (i) a first external clock signal received by the first logic tile, or (ii) a delayed version of the first external clock signal from one of the plurality of output clock paths of a logic tile of the first plurality of logic tiles, an

A second logical tile to receive a second external clock signal at an input of the associated at least one input clock path, wherein each logical tile of a second plurality of logical tiles of the array of logical tiles generates the tile clock using: (i) a second external clock signal received by a second logic tile, or (ii) a delayed version of the second external clock signal from one of the plurality of output clock paths of a logic tile of a second plurality of logic tiles,

wherein:

a logical tile in the first plurality of logical tiles is different from a logical tile in the second plurality of logical tiles, and

the first external clock signal and the second external clock signal are the same clock signal.

18. The integrated circuit of claim 17 wherein a first logic tile is located on a perimeter of a first side of the array of logic tiles and a second logic tile is located on a perimeter of a second side of the array of logic tiles.

19. The integrated circuit of claim 18 wherein the first side of the array of logic tiles is opposite the second side of the array of logic tiles.

20. The integrated circuit of claim 19 wherein a first logical tile is located in a first column on a first side of the array of logical tiles and a second logical tile is located in a last column on a second side of the array of logical tiles.

Background

The present invention relates to circuitry and techniques for clock signal distribution and transmission between logic tiles of integrated circuits, such as processors, controllers, state machines, gate arrays, Programmable Gate Arrays (PGAs), Field Programmable Gate Arrays (FPGAs), and systems on a chip (SOCs). Although the present invention and/or embodiments of the present invention are often described below in the context of an FPGA, such discussion, invention, and/or embodiments are also applicable to programmable or configurable logic blocks, logic array blocks, or logic tile circuitry employed in processors, controllers, state machines, gate arrays, PGAs, and SOCs. For the sake of brevity, no separate discussion is provided for each integrated circuit; however, based on the present disclosure, applicability to, for example, processors, controllers, state machines, gate arrays, PGAs, FPGAs, and SOCs will be apparent to those of ordinary skill in the art.

In short, an FPGA is an integrated circuit that can be configured and/or reconfigured by, for example, a user, customer, and/or designer before, during, and/or after manufacture (hereinafter, collectively referred to as "configuration" and the like (e.g., "configure (configure)", and "configurable")) unless otherwise noted. In one embodiment, an FPGA includes, among other components, a plurality of tiles having programmable components ("tiles" commonly referred to as "configurable logic blocks" (CLBs), "logic array blocks" (LABs), or "logic tiles" -hereinafter collectively referred to as "logic tiles") and a network of configurable interconnects that facilitate communication between and within the logic tiles. Each logic tile has a plurality of inputs and outputs. For example, programmable interconnects are used to connect the inputs and outputs of a logic tile to other logic tiles and to external inputs and outputs of the FPGA (which may be connected to circuitry external to the FPGA).

Each logic tile typically includes thousands of transistors that can be configured to perform a combinatorial function (simple and/or complex). A logic tile may also include memory elements, e.g., blocks/arrays of flip-flops, registers, memory, etc., and/or any kind or type of smaller logic tile. Logic tiles typically include circuitry for synchronizing clock signals that, in operation, facilitate orderly implementation of functions or operations of the logic tiles (e.g., synchronously) and/or communication with other logic tiles and/or external inputs and outputs of the FPGA.

Drawings

The invention may be practiced in conjunction with the embodiments illustrated in the drawings. The figures illustrate different aspects of the invention and, where appropriate, reference numerals or names illustrating similar structures, components, materials and/or elements in different figures are similarly labeled. It is to be understood that various combinations of structures, components, materials and/or elements other than those specifically shown are contemplated and are within the scope of the present invention.

In addition, many inventions are described and illustrated herein. The present invention is not limited to any single aspect or embodiment thereof, nor to any combination and/or permutation of such aspects and/or embodiments. Moreover, each aspect of the present invention and/or embodiments thereof may be employed alone or in combination with one or more other aspects of the present invention and/or embodiments thereof. For the sake of brevity, certain permutations and combinations are not discussed and/or illustrated separately herein. It is worthy to note that embodiments or implementations described herein as "exemplary" are not to be construed as preferred or advantageous, for example, over other embodiments or implementations; but is intended to reflect or indicate that the embodiment(s) is (are) an "example" embodiment(s).

Fig. 1A illustrates a block diagram representation of an integrated circuit, for example, including control circuitry, clock or timing circuitry, and programmable/configurable logic circuitry (which may include one or more logic tiles (each logic tile including (i) logic transistors and (ii) clock distribution and transmission circuitry)); in an illustrative embodiment, the clock/timing circuitry is provided "on-chip", e.g., clock/timing circuitry fabricated in/on a die of an integrated circuit or integrated generates one or more clock signals (the same clock signal or a derivative thereof) and outputs the clock signal(s) to the programmable/configurable logic circuitry (and its physical array of logic tiles); each clock signal is input to multiple (or all) logic tiles (e.g., logic tiles located on a periphery of the programmable/configurable logic circuitry), and in one embodiment, each clock signal is employed by a logic tile of the programmable/configurable logic circuitry to generate a tile clock having a desired or programmable offset (e.g., substantially no offset or zero offset) and/or phase (e.g., 0 degrees or 180 degrees) relative to tile clocks of other logic tiles of the programmable/configurable logic circuitry; notably, the clock circuitry may be partially or completely off-chip (i.e., external to the die of the integrated circuit);

FIG. 1B illustrates a block diagram representation of a plurality of interconnected logic tiles of programmable/configurable logic circuitry (e.g., an FPGA), wherein input/outputs of the logic tiles may facilitate communication between the logic tiles and/or circuitry external to the programmable/configurable logic circuitry; notably, the programmable/configurable logic circuitry includes an array of logic tiles interconnected via one or more configurable interconnects, wherein the array of logic tiles includes a plurality of clock signal inputs to receive clock signals output by the clock circuitry (see fig. 1A); also, a logical tile (e.g., all logical tiles) includes clock distribution and transmission circuitry to (i) generate a tile clock (i.e., a clock employed by the logic circuitry in the tile) using the clock tree of the tile (e.g., see "tile clock" in fig. 2A-2C) and (ii) distribute or send the tile clock or related clock signals to one or more neighboring logical tiles; in one embodiment, a tile clock signal is employed to generate a tile clock for use by logic circuitry (and/or memory) of an associated logic tile to perform, for example, operations therein (see, e.g., fig. 2A-2C, 13A, and 13B);

FIG. 1C illustrates waveforms of clock signals reflecting an offset (delay) therebetween when traveling from a clock source to a clock destination; for example, a clock signal may skew when it travels from one clock buffer to another, or from one clock buffer to a logic element such as a flip-flop or logic tile;

2A-2C illustrate, in schematic block diagram form, exemplary embodiments of clock distribution and transmission circuitry for logic tiles, wherein in these exemplary embodiments the clock distribution and transmission circuitry includes a plurality of input and output paths (four paths-labeled "North clock path," "east clock path," "south clock path," and "West clock path" in this illustrated embodiment) to generate tile clock signals having desired or programmable offsets, and in some embodiments to distribute or send one or more tile clocks or related clock signals to one or more adjacent logic tiles of the programmable/configurable logic circuitry; each of the input and output paths may include one input/output and U-turn (U-turn) circuit (fig. 2A), or more than one input/output and U-turn circuits (fig. 2B and 2C), or a combination thereof; notably, in this exemplary embodiment, the U-turn circuitry includes one or more buffers and their associated wires/conductor routing that may be employed, in whole or in part, in the clock signal distribution path to generate a tile clock signal (with a desired, appropriate, or programmable offset relative to the tile clock signal of other logic tiles-see, e.g., fig. 3A) that, in one embodiment, is employed to generate a tile clock (i.e., the local clock of the logic tile); as described above, this tile clock may be employed by, for example, logic circuitry (and/or memory) to implement the function or operation of the associated logic tile and/or to synchronize communication with external inputs and outputs of other logic tiles and/or programmable/configurable logic circuitry;

FIG. 3A illustrates a block diagram representation of an exemplary embodiment of a plurality of interconnected logic tiles of an exemplary 5x5 logic tile array of programmable/configurable logic circuitry (e.g., an FPGA) in accordance with at least one aspect of the present invention, wherein, in this embodiment, the logic tile array includes a plurality of clock signal inputs (i.e., the clock input of logic tile 1 and the clock input of logic tile 25), each clock input configured to receive a clock signal having known or predetermined characteristics (e.g., frequency and phase) relative to the other clock signal(s), and in one embodiment, each clock signal input configured to receive the same clock signal (i.e., clock 1 signal) or a derived clock signal; notably, each logic tile of the array includes clock distribution and transmission circuitry (illustrated by the blocks disposed within each block of logic tiles) capable of distributing a clock signal to one or more adjacent logic tiles and configured to generate a clock signal having characteristics (e.g., including the same frequency and phase) related in one embodiment to the clock signals of other logic tiles; as described above, in one embodiment, the tile clock signal is employed to generate the tile clock (see fig. 2A-2C);

fig. 3B and 3C illustrate block diagram representations of a plurality of interconnected logic tiles of an MxN logic tile array of programmable/configurable logic circuitry (e.g., an FPGA) in accordance with at least one aspect of the present invention, wherein, in this embodiment, the logic tile array includes a plurality of clock signal inputs (in fig. 3B, the clock inputs of logic tile 1 and logic tile M x N, and in fig. 3C, the clock inputs of logic tile N and logic tile M), each clock input configured to receive a clock signal having known characteristics (e.g., frequency and phase) relative to the other clock signal(s), and in one embodiment, each clock signal input configured to receive the same clock signal (i.e., clock 1 signal) or a derived clock signal; notably, each logic tile of the array includes clock distribution and transmission circuitry (illustrated by the blocks disposed within each block of logic tiles) capable of distributing a clock signal to one or more adjacent logic tiles and configured to generate a clock signal having characteristics (e.g., including the same frequency and phase) related in one embodiment to the clock signals of other logic tiles; as described above, in one embodiment, the tile clock signal is employed to generate the tile clock (see fig. 2A-2C);

3D-3G illustrate block diagram representations of a plurality of interconnected logic tiles of an MxN array of logic tiles of programmable/configurable logic circuitry (e.g., an FPGA) in accordance with at least one aspect of the present invention, wherein, in such embodiments, the array of logic tiles includes more than two clock signal inputs; as described above, each clock input is configured to receive a clock signal having known characteristics (e.g., frequency and phase) relative to the other clock signal(s), and in one embodiment, each clock signal input is configured to receive the same clock signal (i.e., clock 1 signal) or a derived clock signal; notably, each logic tile of the array includes clock distribution and transmission circuitry (illustrated by the blocks disposed within each block of logic tiles) capable of distributing a clock signal to one or more adjacent logic tiles and configured to generate a clock signal having characteristics (e.g., including the same frequency and phase) related in one embodiment to the clock signals of other logic tiles of the array; as described above, in one embodiment, the tile clock signal is employed to generate the tile clock (see fig. 2A-2C); for example, in one embodiment, each logic tile on the perimeter of the opposite side of the array of logic tiles receives a clock signal and sends or distributes the clock signal to other logic tiles in an associated row (see FIG. 3D) or associated column (see FIG. 3E); in another embodiment, each logic tile on the perimeter of the non-opposing side of the array of logic tiles receives a clock signal and sends or distributes the clock signal to other logic tiles in the associated row and associated column (see fig. 3F); in yet another embodiment, each tile clock on the perimeter of all sides of the array of logical tiles receives the clock signal and sends or distributes the clock signal to other logical tiles in the associated row and associated column (see FIG. 3G); notably, in one embodiment, a logic tile of the array employs two or more clock signals (e.g., two or more clock 1 signals received from different clock signal inputs) to generate a tile clock (i.e., a local clock for the logic tile) having a desired or programmable offset (e.g., substantially no offset or zero offset) and/or phase (e.g., 0 degrees or 180 degrees) relative to tile clocks of other logic tiles of the programmable/configurable logic circuitry; as described above, for example, logic circuitry (and/or memory) may employ a tile clock to implement the function or operation of an associated logic tile and/or to synchronize communication with external inputs and outputs of other tiles and/or programmable/configurable logic circuitry;

FIGS. 4A and 4B illustrate exemplary block diagram representations of a plurality of interconnected logic tiles, such as the logic tile type shown in FIG. 2A, in which a tile clock signal is generated in each logic tile via exemplary clock distribution and transmission circuitry of the associated logic tile; exemplary clock distribution and distribution paths and their directions are indicated by bold lines (solid lines in fig. 4A and dashed lines in fig. 4B) and arrows, wherein the clock distribution and transmission circuitry of each logic tile is configured or programmed to provide a clock distribution and distribution path that provides a programmed relationship (e.g., substantially no offset or zero offset) of the tile clock signals employed by each logic tile; in the exemplary embodiment of FIG. 4A, clock 1 signal input is received by logic tile 1, in addition to distributing and sending the clock signal to logic tile 2, also adds a delay that provides a predetermined relationship of the clock signal employed by logic tile 1 to the clock signals of logic tiles 2-5 (and, in some embodiments, one other logic tile, some other logic tile, or all other logic tiles of the programmable/configurable logic circuitry); in the exemplary embodiment of FIG. 4B, clock 2 signal input is received by logic tile 2, and logic tile 2, in addition to distributing and sending the clock signal to logic tiles 1, 3, and 4, adds a delay that provides a predetermined relationship of the clock signal employed by logic tile 2 to the clock signals of logic tiles 1 and 3-5 (and, in some embodiments, one other logic tile, some other logic tile, or all other logic tiles of the programmable/configurable logic circuitry); notably, the one or more clock signal inputs may originate directly or indirectly from clock circuitry disposed "on-chip," e.g., clock circuitry integrated in/on a die of an integrated circuit (see, e.g., fig. 1A) or partially or completely external to the die of the integrated circuit (e.g., clock 1 and/or clock 2 may originate from another logic tile and/or clock alignment circuitry (e.g., a DLL or PLL) partially or completely on or off-chip;

fig. 5A and 5B illustrate block diagram representations of example embodiments of clock distribution and transmission circuitry, e.g., logic tile 4 of the example architectures of fig. 4A and 4B, respectively, in which the clock distribution and transmission circuitry may employ zero, one, or more U-turn circuits associated with the west clock path (thereby adding sufficient clock or signal delay) to generate tile clock signal 4 (with an appropriate or programmable offset (here, substantially no offset or zero offset) relative to the tile clock signals of other logic tiles) -see, e.g., fig. 4A and 4B); in this embodiment, tile clock signal 4 generates one or more tile clocks employed by, for example, logic circuitry (and memory) to implement functions or operations of the logic tiles and/or synchronize communication with external inputs and outputs of other logic tiles and/or programmable/configurable logic circuitry;

FIG. 6A illustrates a block diagram representation of an exemplary embodiment of a plurality of interconnected logic tiles of an exemplary 7x7 array of logic tiles of programmable/configurable logic circuitry (e.g., an FPGA) in accordance with at least one aspect of the present invention, wherein in this embodiment the array of logic tiles includes a plurality of clock signal inputs at each logic tile on a periphery or perimeter of two opposing sides of the array of logic tiles; in this embodiment, the clock signal is sent or allocated to/from adjacent logic tiles in the associated row of the array of logic tiles, and delaying the matching clock 1 signal by 7 "input/output paths" provides a zero (or substantially zero) offset from the tile clock signal of other logic tiles in the associated row; notably, delaying the match clock 1 signal by 7 horizontal "input/output paths" provides a zero offset with respect to the tile clock signals of the other logic tiles in the associated row, in the case where the horizontal input/output paths are not equal to the vertical input/output paths; notably, delay matching of a clock signal received or employed by any particular logic tile may be accomplished via the input/output path(s) in that particular logic tile or of that particular logic tile and/or via the input/output path(s) in other logic tiles of the array or of other logic tiles of the array (e.g., logic tile 1 provides logic tile 2 with a signal having a delay of 2 horizontal "input/output paths" and, based on the provided signal, receives from logic tile 2a signal having a delay of 6 horizontal "input/output paths" from logic tile 2, and thereafter adds 1 additional horizontal "input/output path" delay to the paths to delay matching clock signal 1 for a total of 7 horizontal "input/output paths", generating, providing, and/or employing a zero (or substantially zero) offset with respect to a tile clock signal used by other logic tiles in the associated row (e.g., logic tile 2, logic tile 3, and logic tile 4);

FIG. 6B illustrates a block diagram representation of a plurality of interconnected logic tiles of a 7x7 logic tile array of programmable/configurable logic circuitry (e.g., an FPGA) in accordance with at least one aspect of the present invention, wherein, in this embodiment, the logic tile array includes a plurality of clock signal inputs at each logic tile located on the periphery of two opposite sides of the logic tile array other than the opposite sides discussed in FIG. 6A; in this embodiment, the clock signal is sent and allocated to/from adjacent logic tiles in the associated column of the array of logic tiles, and delaying the matching clock 1 signal by 7 "input/output paths" provides a zero (or substantially zero) offset from the tile clock signals of other logic tiles in the associated column; as mentioned in the context of fig. 6B, delaying the match clock 1 signal by 7 vertical "input/output paths" provides a zero offset with respect to the tile clock signals of the other logic tiles in the associated column, in the case where the horizontal input/output path is not equal to the vertical input/output path; notably, delay matching of a clock signal received or employed by any particular logic tile may be accomplished via the input/output path(s) in that particular logic tile or of that particular logic tile and/or via the input/output path(s) in other logic tiles of the array or of other logic tiles of the array (e.g., logic tile 8 receives a signal from logic tile 1 having 2 vertical input/output path "delays and adds 5 additional vertical input/output path" delays to obtain a total of 7 vertical input/output path "delays, while logic tile 15 receives a signal having 4 vertical input/output paths (introduced by the" input/output paths "in logic tiles 1 and 8), and 3 additional vertical input/output path delays are added to obtain a total of 7 vertical input/output path delays; in this example embodiment, each of logic tiles 8 and 15 (and other tiles in a column) delays match clock signal 1 by a total of 7 vertical "input/output paths" to generate, provide, and/or employ a zero (or substantially zero) offset with respect to the tile clock signals used by the other logic tiles in the associated column (e.g., logic tile 1 and logic tile 22);

FIGS. 6C and 6D illustrate in block diagram form representations of a plurality of interconnected logic tiles (e.g., a 7x7 array of logic tiles) of programmable/configurable logic circuitry in accordance with at least one aspect of the present invention, wherein in one embodiment the array of logic tiles includes a plurality of clock signal inputs located at logic tiles on a periphery of two non-opposing sides of the array of logic tiles (see sides A and B in FIG. 6C), and in another embodiment the plurality of clock signal inputs are located at logic tiles on a periphery of all sides of the array of logic tiles (see sides A-D in FIG. 6D); notably, in one embodiment, the clock signal inputs at/on the a-side and/or C-side correspond to the embodiment of fig. 6B, and the clock signal inputs at/on the B-side and/or D-side correspond to the embodiment of fig. 6A;

FIG. 7A illustrates in block diagram form an exemplary embodiment of at least a portion of tile clock generation circuitry of clock distribution and transmission circuitry for logic tiles in accordance with at least one aspect of the present invention, wherein, in operation, the tile clock generation circuitry receives at an input a plurality of clock signals delay matched to include an appropriate and/or programmable offset (e.g., substantially no offset or zero offset) relative to the tile clock signals of other logic tiles, each clock signal being associated with a clock signal applied to a clock signal input of an array of logic tiles, and employs such clock signals to generate a tile clock for the associated logic tile;

FIGS. 7B and 7C illustrate exemplary embodiments of at least a portion of tile clock generation circuitry of clock distribution and transmission circuitry for logic tiles in accordance with at least one aspect of the present invention, wherein in these exemplary embodiments there are N-input inverting and N-input non-inverting multiplexers (where N ≧ 2), respectively, wherein in operation such multiplexers receive at inputs a plurality of clock signals each associated with a clock signal applied to a clock signal input of an array of logic tiles, wherein a control signal applied to the multiplexer in operation selects one input to send to an output of the multiplexer in one embodiment or selects two or more of the inputs such that at least two of the clock signals applied to the inputs of the multiplexer in operation short-circuit at the output of the multiplexer Effectively creating a clock grid structure distributed over the array of logical tiles; notably, for the avoidance of doubt, the present invention may employ multiplexers such as those illustrated in fig. 4A and 4B of U.S. patent 9,786,361, wherein the multiplexers may be programmed such that multiple input selections are enabled, wherein multiple inputs are electrically connected to the multiplexer outputs via the input-output path(s) of or of the multiplexers;

FIG. 8 illustrates an exemplary block diagram representation of a plurality of interconnected logic tiles (of the type shown in FIG. 2B), such as FPGAs, wherein each logic tile includes a plurality of input/outputs (here two) at each input/output path; in this exemplary embodiment, logic tiles 1-5 receive and distribute/output two clock signals (i.e., a clock 1 signal and a clock 2 signal-which may be the same clock signal (i.e., have the same characteristics, such as frequency and phase)) allocated to/from the logic tiles and via the exemplary clock distribution and transmission circuitry of each logic tile to generate a tile clock signal associated with each clock signal of the logic tiles, as shown in fig. 2A-2C; exemplary clock distribution and distribution paths and their directions are indicated by bold or dashed lines and arrows, wherein the clock distribution and transmission circuitry of each logic tile is configured or programmed to provide a clock distribution and distribution path that provides a programmed relationship (e.g., substantially no offset or zero offset) of the tile clock signals employed by the logic tiles; in an exemplary embodiment, clock 1 is input to logic tile 1 and clock 2 is input to logic tile 2; in both cases, the clock signal is distributed/routed to add a delay that provides a predetermined relationship of the clock signal employed internally by the logic tiles 1-5 (and potentially one other logic tile, some other logic tile, or all other logic tiles of the programmable/configurable logic circuitry); as described herein, clock 1 may be the same clock signal (i.e., have the same characteristics, such as frequency and phase) as clock 2, and may be generated and output by timing circuitry (see fig. 1A);

FIG. 9 illustrates a block diagram representation of example clock distribution and transmission circuitry of logic tile 4 of the example architecture of FIG. 8, where in this example embodiment the clock distribution and transmission circuitry may employ zero, one, or more U-turn circuits associated with the West clock path to generate tile clock signal 4 (with an appropriate or programmable offset (here, substantially no offset or zero offset) relative to the tile clock signals of other logic tiles), the clock distribution and transmission circuitry of logic tile 4 includes multiple inputs/outputs (two in this example embodiment) at each input/output path that are employed to generate one or more tile clocks associated with clock 1 or clock 2, e.g., based on whether clock 1 and clock 2 are synchronous or asynchronous, such tile clocks may be synchronous or asynchronous; each tile clock may be employed by, for example, logic circuitry (and memory) to implement the functions or operations of the logic tile and/or to communicate with other tiles and/or external inputs and outputs of programmable/configurable logic circuitry;

FIG. 10 illustrates a block diagram representation of a plurality of interconnected logic tiles (of the type shown in FIG. 2B), such as FPGAs, where each logic tile includes a plurality of input/outputs (two in this exemplary embodiment) at each input/output path; in this exemplary embodiment, logic tiles 1-3 each receive two clock signals (i.e., a clock 1 signal and a clock 2 signal) that are distributed to some, but not all, of the logic tiles; via the exemplary clock distribution and transmission circuitry of each logic tile, the logic tile generates tile clock signals associated with one or both of the clock signals; exemplary clock distribution and distribution paths and their directions are indicated by bold or dashed lines and arrows, wherein the clock distribution and transmission circuitry of each logic tile is configured or programmed to provide a clock distribution and distribution path that provides a programmed relationship (e.g., substantially no offset or zero offset) of the tile clock signals employed by the logic tiles; in an exemplary embodiment, clock 1 is input to logic tile 1 and clock 2 is input to logic tile 2; in both cases, the clock signal is distributed/routed to add or create a delay that provides or generates a predetermined relationship of the clock signal employed by one, some, or all of the logic tiles 1-5 internally;

FIG. 11 illustrates a block diagram representation of exemplary clock distribution and transmission circuitry for rectangular shaped logic tiles, wherein in this exemplary embodiment the clock distribution and transmission circuitry includes a plurality of input and output paths (four paths-labeled "North clock path," "east clock path," "south clock path," and "West clock path" in this illustrated embodiment) to generate tile clock signals having desired or programmable offsets, and in some cases, to distribute or send one or more tile clocks or related clock signals to one or more adjacent logic tiles of the programmable/configurable logic circuitry; each of the input and output paths may include an input/output and U-turn circuit to introduce additional vertical and horizontal propagation delay components of the clock signal path (where the vertical path is of a different length than the horizontal path); notably, in this exemplary embodiment, the U-turn circuitry includes one or more buffers and their associated wires/conductor routing that may be employed, in whole or in part, in the clock signal distribution path to generate the tile clock signal (with an appropriate or programmable offset relative to the tile clock signal of other logic tiles-see, e.g., fig. 12), and in one embodiment, such circuitry to generate the tile clock (i.e., the local clock of that logic tile); as described above, this tile clock may be employed by, for example, logic circuitry (and/or memory) to implement the function or operation of the associated logic tile and/or to synchronize communication with external inputs and/or outputs of other logic tiles and/or programmable/configurable logic circuitry;

FIG. 12 illustrates an exemplary block diagram representation of a plurality of interconnected logic tiles, such as the logic tile type shown in FIG. 11, with a tile clock signal generated in each logic tile via exemplary clock distribution and transmission circuitry of the associated logic tile; exemplary clock distribution and distribution paths and their directions are indicated by bold lines and arrows, wherein the clock distribution and transmission circuitry of each logic tile is configured or programmed to provide clock distribution and distribution paths (each having the same vertical and horizontal propagation delay components-i.e., 5 horizontal propagation delay components and 2 vertical propagation delay components in this exemplary embodiment) that provide the programmed relationship of the tile clock signals employed by each logic tile (here, substantially no offset or zero offset); in this exemplary embodiment, clock 1 signal input is received by logic tile 1, which logic tile 1, in addition to distributing and sending the clock signal to logic tile 2, also adds a delay (including the vertical and horizontal components of the propagation delay) that provides a predetermined relationship of the clock signal employed by logic tile 1 to the clock signal of logic tiles 2-5 (and, in some embodiments, one other logic tile, some other logic tile, or all other logic tiles of the programmable/configurable logic circuitry); notably, although not shown in fig. 12, one or more clock tiles may receive more than one clock signal input, as described and illustrated herein; the one or more clock signal inputs may originate directly or indirectly from clock circuitry disposed "on-chip," e.g., clock circuitry integrated in/on a die of an integrated circuit (see, e.g., fig. 1A) or partially or fully external to a die of an integrated circuit (e.g., the clock signal inputs may originate from additional logic tiles and/or clock alignment circuitry (e.g., a DLL or PLL) partially or fully on or off-chip;

FIG. 13A illustrates in schematic block diagram form an exemplary embodiment of clock distribution and transmission circuitry for a logic tile, wherein the clock distribution and transmission circuitry includes a plurality of input and output paths (four paths in this illustrated embodiment-labeled "North clock path," "east clock path," "south clock path," and "West clock path") to generate tile clock signals with desired or programmable offsets (as discussed above with respect to the embodiments of FIGS. 2A-2C); furthermore, the clock distribution and transmission circuitry also includes tile clock enable/disable circuitry to responsively enable or disable generation and/or output of local tile clocks (i.e., tile clocks) of the logic tiles (which, as discussed herein, may be employed by, for example, logic circuitry (and/or memory) to implement functions or operations of the associated logic tiles and/or synchronize communication with external inputs and outputs of other logic tiles and/or programmable/configurable logic circuitry); control circuitry (e.g., in the logic tiles and/or external to the array of logic tiles (e.g., see fig. 1A)) may generate one or more control signals to control such tile clock enable/disable circuitry; notably, while in this illustrative embodiment the tile clock enable/disable circuitry is an AND (AND) logic gate, any logic or circuitry may be employed to responsively enable or disable the generation AND/or output of the local tile clock; moreover, the clock enable/disable circuitry may be implemented in any of the embodiments described and illustrated herein;

figure 13B illustrates in schematic block diagram form another exemplary embodiment of clock distribution and transmission circuitry for logic tiles of the logic tile array in accordance with at least one aspect of the present invention, wherein the clock distribution and transmission circuitry generates and/or selects one or more tile clock signals having a desired or programmable offset, and in this embodiment the clock distribution and transmission circuitry includes a plurality of input and output paths (four paths in this illustrated embodiment-labeled "north clock path", "east clock path", "south clock path", and "west clock path") to generate one or more tile clock signals having a desired or programmable offset), a receive clock grid (for sending the grid clock signals to the logic tiles of the array), and clock selection circuitry to select a clock signal to be employed in the logic tiles; in one exemplary embodiment, the clock selection circuitry includes clock selection multiplexer(s) that receive the tile clock signal and the grid clock signal (and any other clock signals); the desired clock signal may be used for circuitry of the logic tile (e.g., to implement operations (e.g., memory, functions, etc.) therein, e.g., via selectively enabling one of the clock inputs of the clock selection multiplexer(s) to connect the selected input to the output of the clock selection multiplexer(s), in one embodiment, such clock selection multiplexer responsively outputs a grid clock signal or an internally generated/derived clock signal as a tile clock used by circuitry of the logic tile to perform or perform, e.g., a function and/or operation, control circuitry (e.g., in the logic tile and/or external to the array of logic tiles) may enable use of the grid clock (in place of other clock signals) via control of such clock selection multiplexer(s), notably, the clock grid of FIG. 13B (and its associated circuitry and/or controls) may be implemented in conjunction with the tile clock enable/disable circuitry of FIG. 13A; indeed, in those cases where/when a logic tile employs a grid clock, the tile clock enable/disable circuitry may disable the generation and output of local tile clocks generated from or using the transmitted/distributed and delay-matched clock signals input to the logic tiles on one or more peripherals or perimeters of the logic tile array (see, e.g., fig. 3A-3G)); and

13C and 13D illustrate in block diagram and schematic form an exemplary embodiment of clock selection circuitry in accordance with at least one aspect of the present invention; in particular, fig. 13C illustrates in block diagram form an exemplary embodiment of clock selection circuitry of clock distribution and transmission circuitry of a logic tile in accordance with at least one aspect of the present invention, wherein, in operation, tile clock generation circuitry receives at inputs a plurality of clock signals (e.g., one or more grid clock signals and one or more delay matched clock signals that include an appropriate or programmable offset (e.g., substantially no offset or zero offset) relative to the tile clock signals of other logic tiles), and fig. 13D illustrates in schematic form clock selection circuitry that implements a clock selection multiplexer to select one or more inputs to connect to an output.

Again, a number of inventions are described and illustrated herein. The present invention is not limited to any single aspect or embodiment thereof, nor to any combination and/or permutation of such aspects and/or embodiments. Each aspect of the invention and/or embodiments thereof may be employed alone or in combination with one or more other aspects of the invention and/or embodiments thereof. For the sake of brevity, many of those combinations and permutations are not discussed individually herein.

Detailed Description

In one aspect, the present invention relates to circuitry and methods for using, providing, distributing, generating and/or sending clock signals in and/or between arrays of logic tiles in integrated circuits, such as processors, controllers, state machines, gate arrays, PGAs, FPGAs and SOCs. In one embodiment, the present architecture, circuitry, and techniques distribute and/or send a plurality of input clock signals in and/or among an array of logic tiles of an integrated circuit to generate a tile clock within each logic tile, wherein the tile clock of each logic tile includes a desired or programmable offset relative to the tile clocks of other logic tiles of programmable/configurable logic circuitry of the integrated circuit. For example, in one embodiment, two or more logic tiles of an array of logic tiles receive the same (or derived) clock signal and distribute and/or send the clock signal to adjacent logic tiles, wherein circuitry in the clock distribution and transmission circuitry of each logic tile facilitates or enables delay matching of the clock signal sent or distributed from logic tile to logic tile such that each logic tile generates a local clock signal (i.e., a tile clock) that is balanced and/or synchronized and substantially offset and/or phase-shifted or zero-offset and/or phase-shifted with respect to the clock signals generated and employed in or by other logic tiles of the array of logic tiles of the integrated circuit.

In one embodiment, such two or more logical tiles are located on two or more (or all) of the perimeter of the logical tile array. That is, in one embodiment, two or more logic tiles are disposed on or form opposite perimeters of the array (e.g., the logic tiles are located at opposite corners of the opposite perimeters), and the two or more logic tiles include clock inputs that receive the same clock signal. Thereafter, the circuitry of the logic tile distributes and/or sends the clock signal to adjacent logic tiles in associated rows and/or columns of the array of logic tiles/associated rows and/or columns of the array of logic tiles. Circuitry in the clock distribution and transmission circuitry of each logic tile enables delay matching of a clock signal sent or distributed from the logic tile to the logic tile such that each logic tile of the array receives, generates, and/or employs a clock signal having a predetermined offset relative to clock signals of other logic tiles (e.g., synchronous and substantially no offset and/or phase difference or zero offset and/or phase difference relative to clock signals generated or employed in or by other logic tiles of an array of logic tiles of an integrated circuit). Such clock signals are employed by circuitry in the logic tiles to generate a local clock signal (i.e., a tile clock) that is balanced with respect to other clock signals of other logic tiles of the array. Circuitry in a logic tile may employ a local clock signal (i.e., a tile clock) to facilitate implementation of functions or operations of the logic tile and/or communication with other logic tiles and external inputs and outputs.

In yet another embodiment, logic tiles located on or forming two non-opposing perimeters of the array of logic tiles (e.g., all of the logic tiles disposed on or forming two non-opposing perimeters of the array of logic tiles) include a clock input that receives a clock signal. Here, such clock inputs may receive the same (or derived) clock signal. Thereafter, a clock signal is provided, distributed, and/or sent to adjacent logic tiles in associated rows and columns of the array of logic tiles. In this embodiment, the clock distribution and transmission circuitry of each logic tile receives two clock signals-one from the adjacent logic tile of the associated row and one from the adjacent logic tile of the associated column. In one embodiment, circuitry in the clock distribution and transmission circuitry uses the two clock signals to generate the local clock signal in addition to implementing delay matching of the clock signals sent or distributed from logic tile to logic tile. That is, on a tile-by-tile basis, clock signals sent to or distributed from logic tiles in the row direction after delay matching and clock signals sent to or distributed from logic tiles in the column direction after delay matching are employed to generate local clock signals (i.e., tile clocks) that are balanced with respect to the tile clocks of other logic tiles. The tile clock is used by circuitry in the logic tile to facilitate implementation of functions or operations of the logic tile and/or communication with other logic tiles and external inputs and outputs. For example, in one embodiment, two delay matched clock signals are "shorted" to generate one or more local clock signals (e.g., tile clocks for associated logic tiles). In one embodiment, two delay matched clock signals are "shorted" via a multiplexer, where the inputs are independently controlled, allowing more than one input to be connected to the output at the same time through the multiplexer input to output paths.

Indeed, in another embodiment, all of the logic tiles of or forming a perimeter of the array of logic tiles (e.g., all four perimeters of the array of logic tiles) include a clock signal input that receives the same clock signal (and/or derived clock signal). In this embodiment, clock signals are distributed and/or sent from opposite sides of the array of logic tiles to adjacent logic tiles for both the row and column directions of the array. Here, the circuitry of the clock distribution and transmission circuitry of each logic tile may employ one, two, three, or four of the delay matched clock signals received by the clock distribution and transmission circuitry of the logic tile in generating the local clock signal(s). For example, such circuitry may generate a local clock signal using clock signals (i.e., four delay-matched clock signals) that are distributed and/or transmitted (i.e., from two opposing sides) to/from logic tiles in the same row and (ii) from two sides to/from logic tiles in the same column. As described above, on a tile-by-tile basis, two clock signals (one clock signal sent or distributed from each side of the array along an associated row) sent or distributed to/from the logic tiles in the row direction are, after delay matching, one or both employed to generate one or more local clock signals (or derivatives thereof) employed by circuitry in the logic tiles. Similarly, two clock signals sent or distributed to/from a logic tile in the column direction (one clock signal sent or distributed from each side of the array along the associated column) after delay matching, one or both are employed to generate one or more local clock signals (or derivatives thereof) employed by circuitry in the logic tile. For example, in one embodiment, the delay matched clock signals are "shorted out" to generate one or more local clock signals (e.g., the tile clocks of the associated logic tiles, effectively creating a clock grid structure for the delay matched clock signals between the array of tiles). In one embodiment, the same circuitry is used to short all delay matched clock signals together; in another embodiment, the delay matched clock signals from the row direction and the column direction are each first shorted, and thereafter, the short circuit signal from the row direction and the short circuit signal from the column direction are then shorted to generate one or more local clock signals. It should be noted that all circuitry and techniques for shorting clock signals are intended to fall within the scope of the present invention, including, for example, multiplexers in which the inputs are independently controlled, thereby allowing more than one input to be simultaneously connected to an output through a multiplexer input to output path.

Referring to fig. 1A and 1B, in one embodiment, an integrated circuit includes control circuitry, clock circuitry, and programmable/configurable logic circuitry that may include one or more logic tiles. Each of the logic tiles may include logic and/or memory transistors (not shown) and clock distribution and transmission circuitry that may be configured to, among other things, generate tile clock signal(s) having a desired or programmable offset (e.g., substantially no offset or zero offset) and/or phase (e.g., 0 degrees or 180 degrees) relative to tile clock signal(s) of other logic tiles of the programmable/configurable logic circuitry. For example, circuitry in the clock distribution and transmission circuitry of each logic tile enables delay matching of a clock signal sent or distributed from the logic tile to the logic tile, such that each logic tile of the array generates a local clock signal (i.e., a tile clock) that is synchronous and substantially offset and/or phase-difference or zero-offset and/or phase-difference with respect to the clock signal generated and employed in or by other logic tiles of the array of logic tiles. Such local clock signals (i.e., tile clocks) (and/or derivatives thereof) may be employed by circuitry in the logic tiles to facilitate implementation of functions or operations of the logic tiles and/or communication with other logic tiles and external inputs and outputs.

In short, "clock skew" refers to a delay caused by a clock signal when the clock signal travels from a clock source to a clock destination (see fig. 1C). For example, clock skew may occur when traveling from one clock buffer to another, or from one clock buffer to a logic or memory element (such as a flip-flop, CLB, and/or logic tile). In this application, clock skew refers to the delay in a clock signal as it travels from one logic tile to another.

Referring to fig. 1A, 1B, and 2A-2C, in one embodiment, clock distribution and transmission circuitry of a logic tile generates a tile clock for logic circuitry (and/or memory) of an associated logic tile (see, e.g., fig. 2A), and further distributes or sends the tile clock signal or related clock signals to one or more adjacent or collocated logic tiles of programmable/configurable logic circuitry via one or more clock paths. In one embodiment, the clock distribution and transmission circuitry of a logic tile includes multiple output paths (four paths-labeled "north clock path," "east clock path," "south clock path," and "west clock path" in this illustrated embodiment) to generate tile clock signals having desired or programmable offsets, and in some cases, to distribute or send one or more tile clock signals or related clock signals to one or more adjacent logic tiles of the array of logic tiles. Notably, in the exemplary embodiment of FIG. 2A, each of the four clock paths has one tile output clock path, one tile input clock path, and one tile U-turn circuit; while in the exemplary embodiment of fig. 2B and 2C, each of the four clock paths has two or more tile output clock paths, two or more tile input clock paths, and two or more tile U-turn circuits.

In one embodiment, each clock path includes a plurality of transistors (configured and illustrated as a plurality of buffers in the exemplary embodiment of fig. 2A-2C). Here, exemplary clock distribution and transmission circuitry includes one or more U-turn circuits that can be selectively added to a clock signal distribution path of a logic tile to generate a tile clock signal having a desired or programmable offset (e.g., substantially no offset or zero offset) and/or phase (e.g., 0 degrees or 180 degrees) relative to the tile clock signals of other logic tiles of programmable/configurable logic circuitry of the integrated circuit. In this exemplary embodiment, a U-turn circuit is provided at each output path to provide flexibility in the design and layout of the architecture for clock generation of one, some or all of the logic tiles of the programmable/configurable logic circuitry. The U-turn circuits in the logic tiles may be made up of the same or different types of circuits or elements-for example, the U-turn circuit of a first output path may be made up of one buffer and the U-turn circuit of a second output path may be made up of two or more buffers. However, it may be advantageous to construct a U-turn circuit having the same type of circuitry (e.g., buffers and associated conductors) and/or the same or similar electrical characteristics as the input and output paths. In this way, delay matching of clock signals from logic tile to logic tile may be facilitated. For example, it may be advantageous to design paths with the same resistive and capacitive loads, the same wire lengths and shields, the same type of clock buffer, and the same transistors of such clock buffers to more completely match the delay of the clock signal from logic tile to logic tile. It is noted that although in the illustrative embodiment, U-turn circuitry is located at all output paths of a logic tile, one or more logic tiles may include output paths that do not include U-turn circuitry at one output path, some output paths, or all output paths.

As mentioned above, the layout of the clock distribution and transmission of one, some, or all of the logic tiles of the programmable/configurable logic circuitry may provide a desired or programmable offset of the clock signal associated with the logic tiles of the programmable/configurable logic circuitry of the integrated circuit. In one embodiment, the clock distribution and transmission circuitry in each logic tile generates a local clock signal that is synchronized and substantially offset-free or zero-offset relative to tile clock signals employed in or by other logic tiles of the programmable/configurable logic circuitry.

Referring to fig. 3A-3G, the array of logic tiles receives a plurality of clock signals having the same or substantially the same characteristics (e.g., frequency and phase) at the clock signal input. For example, referring to fig. 3A-3C, in one embodiment, the array of logic tiles includes two clock inputs to receive the clock 1 signal. In one embodiment, two clock signals are provided to the logic tiles located at or diagonal to opposite sides of the perimeter of the array of logic tiles (see, e.g., logic tile 1 and logic tile 25 of the 5x5 array of logic tiles of fig. 3A). In another embodiment, a clock signal is provided to each logic tile on opposite sides of the perimeter of the array of logic tiles (see, e.g., fig. 3D and 3E). In yet another embodiment, a clock signal is provided to each logic tile of the perimeter of the array (see, e.g., fig. 3G). In one embodiment, each clock 1 signal is routed or sent to/from an adjacent logical tile of the array of logical tiles such that each logical tile receives a clock 1 signal. In addition to routing or sending such clock signals to adjacent logic tiles, clock distribution and transmission circuitry of a logic tile adds, provides, or implements appropriate delay matching (e.g., via U-turn circuitry) to provide, generate, and/or employ clock signals that are substantially offset and/or phase or zero offset and/or phase difference relative to clock signals provided, generated, and/or employed in or by other logic tiles of an array of logic tiles of an integrated circuit.

For example, referring to fig. 4A, 4B, 5A, and 5B, in one embodiment, the clock distribution and transmission paths of logical tiles 1-5 provide substantially no offset or zero offset between the tile 1-5 clock signals and/or the tile clocks of logical tiles 1-5. The clock signal distribution path and its direction are indicated by the bold lines and arrows. The clock distribution and transmission circuitry of each logical tile 1-5 is programmed to provide a tile clock signal and/or a tile clock that is substantially or zero offset with respect to the other tile clock signals and/or tile clocks, respectively.

In particular, with reference to the exemplary embodiment of FIG. 4A, a clock signal input ("clock 1 signal") is applied to and received by logic tile 1. The total delay introduced by each logical tile is 7 "units". For: (i) the clock signal distribution path for the tile 1 clock signal associated with logic tile 1 adds three U-turn circuits (thereby providing a total of 7 units of delay), (ii) the clock signal distribution path for the tile 2 clock signal associated with logic tile 2 adds two U-turn circuits (thereby providing a total of 7 units of delay), (iii) the clock signal distribution path for the tile 3 clock signal associated with logic tile 3 adds one U-turn circuit (thereby providing a total of 7 units of delay), (iv) the clock signal distribution path for the tile 4 clock signal associated with logic tile 4 adds one U-turn circuit (thereby providing a total of 7 units of delay), and (v) the clock signal distribution path for the tile 5 clock signal associated with logic tile 5 does not incorporate U-turn circuitry (thereby providing a total delay of 7 units). In this manner, there is substantially no skew between the tile clock signals of logic tiles 1-5 of FIG. 4A (in this exemplary embodiment, each tile clock signal includes 7 units of delay in the clock distribution path, where each unit represents the equivalent delay of 1 clock branch, which in this exemplary embodiment is the delay of one clock buffer plus its associated wire routing).

In the exemplary embodiment of FIG. 4B, a clock signal input (labeled "clock 2 signal") is applied to and received by logic tile 2, which logic tile 2 incorporates two U-turn circuits in generating the tile 2 clock signal. The total delay introduced by logical tile 2 is 5 units. In addition, the clock generation path associated with tile 1 adds one U-turn circuit in generating the tile 1 clock signal (providing a total of 5 units of delay-2 units in logic tile 2 and 3 units on logic tile 1). The tile clock signals for logic tiles 3-5 also include a total delay of 5 units. In this manner, there is substantially no skew between the tile clock signals of the logic tiles of FIG. 4B (in this exemplary embodiment, each tile clock signal includes 5 units of delay in the clock generation path, where each unit represents the equivalent delay of 1 clock branch, which in this exemplary embodiment is the delay of one clock buffer plus its associated wire/conductor wiring).

Referring to fig. 3D-3G and 6A-6C, in one embodiment, all of the logic tiles forming or on one or more (or all) of the perimeters of the array of logic tiles receive the same clock signal (or a derived clock signal thereof). For example, referring to fig. 3D, 3E, 6A, and 6B, in one embodiment, logic tiles disposed on or forming opposing perimeters of the array of logic tiles include a clock signal input to receive the same clock signal and distribute and/or send the clock signal to adjacent logic tiles in associated rows of the array of logic tiles (see sides B and D of fig. 3D and 6A) or adjacent logic tiles in associated columns of the array of logic tiles (see sides a and C of fig. 3E and 6B). Clock distribution and transmission circuitry of logic tiles enables delay matching of clock signals sent or distributed from adjacent logic tiles of associated rows and associated columns to adjacent logic tiles. For example, referring to fig. 3D, logic tile 2 receives a clock signal (i.e., clock 1 signal) from adjacent logic tile 1 and from logic tile N via the logic tile of row 1 disposed between logic tile N and logic tile 2. The clock distribution and transmission circuitry of logic tile 2 enables proper delay matching of the clock 1 signal received from the D-side (i.e., logic tile 1) and/or enables proper delay matching of the clock 1 signal received from the B-side (i.e., via logic tile N of the logic tile disposed therebetween). Clock distribution and transmission circuitry in each logic tile of the array generates one or more local clock signals (i.e., one or more tile clocks) that are synchronized and substantially offset and/or phase difference or zero offset and/or phase difference with respect to clock signals generated or employed in or by other logic tiles of the array of logic tiles of the integrated circuit using one or more delay matched clock signals.

In one embodiment, a logic tile may generate one or more local clocks using clock signals input to logic tiles located on two opposite sides of the array of logic tiles. For example, referring to fig. 3D and 7A, logic tile 2 receives clock signals (clock 1 signals) from both the B-side and D-side. After delay matching of the clock signals (relative to other logic tiles of the array), the clock distribution and transmission circuitry of logic tile 2 may generate one or more local tile clocks based on and/or using one or both of the clock signals. For example, in one embodiment, after each clock signal received from a logic tile of an associated row is properly delay matched, the clock distribution and transmission circuitry of logic tile 2 electrically "shorts" the plurality of clock 1 signals to generate the local clock signal. That is, the clock distribution and transmission circuitry of the logic tiles includes multiplexers to receive delay matched clock signals (from adjacent logic tiles in (i) the associated row and/or (ii) the associated column) and to electrically short the clock signals at the outputs of the multiplexers (see fig. 7B and 7C). Here, the multiplexer receives at an input a plurality of clock signals, each clock signal being associable with a clock signal applied to a clock signal input of the array of logic tiles, wherein a control signal applied to the multiplexer selects in operation two or more inputs to be simultaneously connected to the output such that at least two clock signals applied to the inputs of the multiplexer are short-circuited in operation at the output of the multiplexer. As discussed above, the local tile clock(s) may be employed by the circuitry to perform or perform functions or operations of the logical tiles.

Notably, the present invention may employ multiplexers such as those illustrated in fig. 4A and 4B of U.S. patent 9,786,361, where the multiplexers may be programmed such that multiple inputs are selected/enabled, thereby simultaneously connecting multiple multiplexer inputs to a multiplexer output via input-output path(s) of or of the multiplexers. Here, the control signals applied to the select inputs of the multiplexers independently control whether a given multiplexer input is connected to an output, such that in operation more than one (or all) of the inputs of the multiplexers may be connected to the output at the same time, thereby electrically shorting the selected/enabled input at the output of the multiplexer.

In this example embodiment, each logic tile (e.g., logic tile 2) employs two delay-matched clock signals to generate one or more tile clocks having a desired or programmable offset (e.g., substantially no offset or zero offset) and/or phase (e.g., 0 degrees or 180 degrees) relative to the tile clocks of other logic tiles of the programmable/configurable logic circuitry that may be employed by (or derivatives of) the circuitry in the logic tile to facilitate implementation and/or communication of functions or operations of the logic tile. Thus, in one embodiment, a two-input multiplexer (N-2) may be implemented, where both multiplexer inputs are selected/enabled, thereby simultaneously connecting inputs to the output of the multiplexer via the input-output path(s) in or of the multiplexer and shorting such inputs at the output of the multiplexer.

(see fig. 7B and 7C).

Notably, in another embodiment, each logic tile employs one of the delay matched clock signals to generate one or more tile clocks having a desired or programmable offset (e.g., substantially no offset or zero offset) and/or phase (e.g., 0 degrees or 180 degrees) relative to the tile clocks of other logic tiles of the programmable/configurable logic circuitry that may be employed to implement the function or operation of the logic tile and/or to communicate external to other tiles or arrays of logic tiles. Thus, in this exemplary embodiment, a two-input multiplexer (N ═ 2) may be implemented, where one of the inputs is selected and applied to the output of the multiplexer. (see fig. 7B and 7C).

Referring to fig. 3F and 6C, in another embodiment, all of the logic tiles forming one or more (or all) of the perimeters of the array of logic tiles, or one or more (or all) of the perimeters of the array of logic tiles, on two non-opposing perimeters of the array of logic tiles receive a clock signal. (see, e.g., sides A and D of FIG. 3F and sides A and B of FIG. 6C). In this embodiment, a clock signal is input to the logic tiles forming or on the perimeters of the a-side and D-side of the array of fig. 3F, and is allocated and/or sent to adjacent logic tiles of the associated rows/associated columns of the logic tiles of the array of logic tiles (e.g., from logic tile 1 to logic tile 2, etc., to logic tile N) and to adjacent logic tiles of the associated columns/associated columns of the array (e.g., from logic tile 1 to all logic tiles in the same column-including logic tile M). The clock distribution and transmission circuitry of each logic tile of the logic tile array of fig. 3F and 6C, in addition to enabling delay matching of the clock signals sent or distributed from logic tile to reduce skew and/or phase differences relative to the clock signals generated and employed in or by other logic tiles of the array, also uses the clock signals to generate local clock signals that are both (i) distributed and/or sent to/from logic tiles in the same/associated row and (ii) distributed and/or sent to/from logic tiles in the same/associated column (e.g., see fig. 7A). Here, the tile clock generation circuitry of the clock distribution and transmission circuitry of each logic tile generates one or more local tile clocks based on and/or using delay matched clock signals input into the array of logic tiles. As discussed above, such local tile clock(s) (i.e., tile clock (s)) may be employed by circuitry to perform or perform functions or operations of a logic tile.

For example, similar to the embodiments of fig. 3D, 3E, 6A, and 6B, in one embodiment, after delay matching the clock 1 signal to reduce or eliminate skew and/or phase differences relative to the clock signal (i.e., delay matching the clock signal), the clock distribution and transmission circuitry of logic tile 1 may "short" the clock signal to generate a clock signal based on the two delay matched clock 1 signals. Referring to fig. 7B and 7C, the clock distribution and transmission circuitry in a logic tile may include one or more multiplexers to receive the delay matched clock signal (from adjacent logic tiles in (i) the associated row and (ii) the associated column) and to electrically short the clock signal at the multiplexer output. In operation, the multiplexer receives at an input a plurality of clock signals, each clock signal being associable with a clock signal applied to a clock signal input of the array of logic tiles, wherein a control signal applied to the multiplexer selects in operation two or more inputs such that at least two clock signals applied to the inputs of the multiplexer are short-circuited in operation at the output of the multiplexer.

Again, each logic tile (e.g., logic tile 1) employs at least two delay-matched clock signals to generate one or more local clock signals that may be employed by (or derivatives of) circuitry in the logic tile to facilitate implementation and/or communication of the functions or operations of the logic tile. Thus, a two-input multiplexer (N ═ 2) can be implemented. (see fig. 7B and 7C).

Notably, delay matching of a clock signal received or employed by any particular logic tile may be achieved via input/output path(s) in or of that particular logic tile and/or via input/output path(s) in or of other logic tiles of the array. For example, referring to fig. 6A, in one embodiment, logic tile 1 provides a delayed signal having 2 horizontal "input/output paths" to logic tile 2 and receives a delayed signal having 6 horizontal "input/output paths" from logic tile 2. Logic tile 1 also adds 1 additional horizontal "input/output path" delay to the received signal, delaying matching clock signal 1 with a total of 7 horizontal "input/output path" delays. Here, the logic tiles in all columns are delayed by 7 horizontal "input/output path" delays by matching clock signal 1 in order to generate, provide, and/or employ a zero (or substantially zero) offset with respect to the tile clock signals used by other logic tiles in the associated row (e.g., logic tile 2, logic tile 3, and logic tile 4). The logic tiles of other rows of the array achieve the same delay matching.

Similarly, referring to fig. 6B, logic tile 15 receives a signal with a delay of 4 vertical "input/output paths" (added via the "input/output paths" of logic tiles 1 and 8/of logic tiles 1 and 8) and also adds 3 vertical "input/output path" delays to obtain a total delay of 7 vertical "input/output paths". Here, the logic tiles in all columns are delayed by 7 vertical "input/output path" delays by matching clock signal 1 in order to generate, provide and/or employ a zero (or substantially zero) offset with respect to the tile clock signal used by the other logic tiles in the associated column. The logic tiles of other columns of the array achieve the same delay matching.

Referring to fig. 3G and 6D, in yet another embodiment, all of the logic tiles forming or on the perimeter of the array of logic tiles include at least one clock input to receive a clock signal. In the illustrated embodiment, the clock signal is input to the logic tiles forming or on the perimeters of the a, B, C and D sides of the array of logic tiles, and is allocated and/or sent to adjacent logic tiles of associated rows/associated columns of the logic tiles of the array of logic tiles, and to adjacent logic tiles of associated columns/associated columns of the array of logic tiles. For example, with respect to the embodiment of fig. 6D (which refers to fig. 6A and 6B), in the context of the row "direction" (see fig. 6A), a clock 1 signal is input into logical tile 1, a delayed version is sent to logical tile 2, a further delayed version is sent to logical tile 3, and so on, with the still further delayed version being sent to logical tile 7 and received by logical tile 7. Similarly, the clock 1 signal is also input to logic tile 7, the delayed version is sent to logic tile 6, the further delayed version is sent to logic tile 5, and so on, with the further delayed version being sent to logic tile 1. In this embodiment, a clock signal is input to each logic tile on the periphery of each row of the array of logic tiles and thereafter transmitted and/or distributed to the respective adjacent logic tiles in/of the associated row. Thus, clock signals input into the logic tiles on the perimeter are received, sent and/or distributed to adjacent logic tiles in/of the associated row.

In the context of the column "direction" (see FIG. 6B), the clock 1 signal is input into logical tile 1, the delayed version is sent to logical tile 8, the further delayed version is sent to logical tile 15, and so on, with the still further delayed version being sent to logical tile 43 and received by logical tile 43. Similarly, the clock 1 signal is also input to logic tile 43, the delayed version is sent to logic tile 36, the further delayed version is sent to logic tile 29, and so on, with the further delayed version being sent to logic tile 1. In this embodiment, a clock signal is input to each logic tile on the periphery of each column of the array of logic tiles and thereafter transmitted and/or distributed to the respective adjacent logic tiles in/of the associated row. Thus, clock signals input into the logic tiles on the perimeter are received, sent and/or distributed to adjacent logic tiles in/of the associated column.

With continued reference to fig. 3G and 6D, the clock distribution and transmission circuitry of each logic tile appropriately delay matches the clock signals received, transmitted and/or distributed from logic tile to reduce or eliminate skew and/or phase differences relative to the clock signals generated and employed in or by other logic tiles of the array. Tile clock generation circuitry of the clock distribution and transmission circuitry receives the delay matched clock signals and uses one or more (or all) of such clock signals to generate one or more local clock signals ((one or more) tile clocks). (see, e.g., FIG. 7A). That is, in one embodiment, clock signals that are both (i) received, allocated, and/or transmitted to/from logical tiles in the same row, and/or (ii) received, allocated, and/or transmitted to/from logical tiles in the same column are employed to generate one or more local clock signals.

For example, referring to fig. 3G, logic tile 1 may generate a local tile clock using the clock 1 signal input from side a (after appropriate delay matching), the clock 1 signal input from logic tile N on the perimeter of the array on side B (again after appropriate delay matching), the clock 1 signal input from logic tile M on the perimeter of the array on side C (again after appropriate delay matching), and the clock 1 signal input from side D (after appropriate delay matching). Here, tile clock generation circuitry of logical tile 1 generates the tile clock based on and/or using four delay matched clock signals (e.g., via the circuitry of fig. 7A, 7B, and/or 7C). As discussed above, such local tile clocks may be employed by circuitry in logical tile 1 to perform or perform functions or operations of the logical tile. Similar operations are implemented in each of the other logical tiles of the array of FIG. 3G. The same is true in the logical tiles of the array of FIG. 6D. That is, the tile clock generation circuitry of the clock distribution and transmission circuitry of each logic tile generates a local clock signal using clock signals that are (i) distributed and/or transmitted from two opposing sides to/from logic tiles in the same row and (ii) from both sides to/from logic tiles in the same column. As described above, in one embodiment, clock signals received, transmitted, or distributed to/from logic tiles in the row direction are employed by tile clock generation circuitry after delay matching, and clock signals transmitted or distributed to/from logic tiles in the column direction are employed by the tile clock generation circuitry after delay matching to generate (e.g., in one embodiment, an electrical "short" -see fig. 7B and 7C) one or more local clock signals.

Notably, in one embodiment, the logic tiles of the embodiments illustrated in fig. 3G and 6D need not employ all of the input clock signals (i.e., in this illustrated embodiment, four clock signals are input into the logic tiles forming or on the perimeter of the array of logic tiles). In this regard, the tile clock generation circuitry of the clock distribution and transmission circuitry of each logic tile may employ one, two, three, or four of the clock signals input into the array to generate one or more local clock signals. That is, the circuitry of the clock distribution and transmission circuitry of each logic tile may employ one, two, three, or four of the delay matched clock signals received by the clock distribution and transmission circuitry of the logic tile in generating the local clock signal(s).

Thus, in this embodiment, the clock distribution and transmission circuitry of the logic tiles may generate local clock signals using clock signals (i.e., four delay matched clock signals) distributed and/or transmitted (i.e., (i) from one or both opposing sides to/from logic tiles in the same row and/or (ii) from one or both sides to/from logic tiles in the same column. As described above, two clock signals are sent or distributed to/from the logic tiles in the row direction (one clock signal sent or distributed from each side of the array along the associated row) on a tile-by-tile basis, and after delay matching, one or both are employed to generate one or more local clock signals (or derivatives thereof) employed by circuitry in the logic tiles. Similarly, two clock signals are sent or distributed to/from the logic tiles in the column direction (one clock signal sent or distributed from each side of the array along the associated column), with one or both being employed to generate one or more local clock signals (or derivatives thereof) employed by circuitry in the logic tiles after delay matching. For example, in one embodiment, two, three, or four of the delay matched clock signals are "shorted" to generate one or more local clock signals (e.g., tile clocks for the associated logic tiles). (see, e.g., FIG. 7A and the multiplexers of FIGS. 7B and 7C).

It is noted that in one embodiment, all clock signals are shorted together using the same circuitry (e.g., a multiplexer). In another embodiment, delay matched clock signals from the row direction are shorted and delay matched clock signals from the column direction are separately shorted, after which the short signals from the row direction and the short signals from the column direction are then shorted to generate one or more local clock signals. It should be noted that all combinations and permutations of shorting clock signals, as well as circuitry and techniques, are intended to fall within the scope of the present invention.

The layout of the clock distribution and transmission of one, some, or all of the logic tiles of the programmable/configurable logic circuitry may provide a desired or programmable offset of two or more of the same or different input clock signals. In one embodiment, clock distribution and transmission circuitry in one or more logic tiles may generate local clock signals associated with more than one input clock, where the local clock signals associated with each input clock are synchronous and substantially offset-free or zero-offset with respect to tile clock signals employed in one or more other logic tiles of the programmable/configurable logic circuitry. In another embodiment, clock distribution and transmission circuitry in one or more logic tiles may generate asynchronous local clock signals having a fixed or programmable offset relative to tile clock signals employed in one or more other logic tiles of the programmable/configurable logic circuitry. Notably, for each logical tile, the tile clock generated based on an input clock may be synchronous or asynchronous with respect to a tile clock generated based on another, different input clock.

In particular, referring to fig. 8 and 9, in one embodiment, the clock distribution and transmission paths of logical tiles 1-5 (of the type of fig. 2B or 2C) relative to clock 1 provide substantially or zero offset between the tile clocks (associated with clock 1) of logical tiles 1-5. Similarly, the clock distribution and transmission paths for logical tiles 1-5 relative to clock 2 provide substantially no offset or zero offset between the tile clocks (associated with clock 2) for logical tiles 1-5. The clock signal distribution path of the clock 1 and its direction are indicated by the bold lines and arrows. The clock signal distribution path of the clock 2 and its direction are indicated by dotted lines and arrows. In this embodiment, the clock distribution and transmission circuitry of each logical tile 1-5 is programmed to provide a tile clock signal and/or tile signal related to clock 1 that is substantially or zero offset from other tile clock signals and/or tile signals associated with clock 1, respectively. Similarly, the clock distribution and transmission circuitry of each logical tile 1-5 is programmed to provide a tile clock signal and/or tile signal associated with clock 2 that is substantially or zero offset relative to other tile clock signals and/or tile signals associated with clock 2, respectively.

Thus, in those embodiments where one or more logic tiles receive, transmit, distribute, and generate multiple different clock signals based on different input clocks, the clock distribution and transmission circuitry of each logic tile may employ multiple input and output clock buffers per path to generate and distribute such clocks. In this exemplary embodiment, each tile generates, distributes, and supports two tile output clocks, two tile input clocks, and two tile U-turn circuits for each clock path, whereby each logic tile propagates two independent clock signals to those tiles concerned and generates two local clocks (the tile clock signals corresponding to clock 1 signal input and clock 2 signal input — each employed to generate an independent "tile clock" for the associated logic tile).

Notably, the tile clocks generated using clock 1 and/or clock 2 may be employed to generate a plurality of synchronous or asynchronous tile clocks (based on clock 1 and/or clock 2) employed by, for example, logic circuitry (and memory) to implement synchronous or asynchronous functions or operations in or of the logic tiles or/and synchronous or asynchronous communications with other logic tiles and/or external inputs and outputs of programmable/configurable logic circuitry. Such synchronous or asynchronous clocks may be associated with clock 1, or clock 2, or clock 1 and clock 2.

The techniques of this disclosure may be implemented using one or more processors (suitably programmed) of an architecture for executing, enforcing, and/or evaluating clock allocations of one, some, or all of the logic tiles of a programmable/configurable logic circuitry. The clock distribution architecture can selectively add one or more (or, if appropriate, none) U-turn circuits to the clock signal path of one or more logic tiles to generate a tile clock signal having a desired or programmable offset relative to the tile clock signals of other logic tiles of the programmable/configurable logic circuitry of the integrated circuit.

While clock input signals having substantially no skew therebetween after delay matching have been described, illustrated, configured and/or designed, such signals may be configured or designed (and thereafter constructed) to include a predetermined or programmed clock skew with respect to one or more clock signals of other logic tiles of programmable/configurable logic circuitry of the integrated circuit. The architecture of the clock distribution of one, some or all of the logic tiles of the programmable/configurable logic circuitry may be designed to provide a desired or programmable non-zero offset with respect to the clock signals of other logic tiles of the programmable/configurable logic circuitry of the integrated circuit. Notably, the programmable offset can be fixed or programmable/variable (whether one or more times) during (in situ) use and/or based on one or more operating conditions, for example. Moreover, the programmable offset may be fixed and/or programmable after manufacture, deployment, and/or during operation (e.g., in situ by a user and/or operator of an electronic device associated with the control circuitry).

A number of inventions are described and illustrated herein. While certain embodiments, features, attributes and advantages of the inventions have been described and illustrated, it should be understood that many other, as well as different and/or similar embodiments, features, attributes and advantages of the present inventions that are apparent from the description and illustration. Thus, the embodiments, features, attributes and advantages of the inventions described and illustrated herein are not exhaustive and it should be understood that such other, similar, as well as different embodiments, features, attributes and advantages of the present inventions are within the scope of the present inventions.

Indeed, the invention is not limited to any single aspect or embodiment thereof, nor to any combination and/or permutation of such aspects and/or embodiments. Moreover, each aspect of the present invention and/or embodiments thereof may be employed alone or in combination with one or more other aspects of the present invention and/or embodiments thereof.

For example, in the illustrative exemplary embodiment, the clock circuitry is located "on-chip," e.g., clock circuitry integrated in/on a die of an integrated circuit. In one embodiment, a programmable/configurable logic system includes a plurality of logic tiles, each of which includes a plurality of clock signals.

Also, while the U-turn circuitry has been described and illustrated as being located at/in the associated output path, the U-turn circuitry need not be located at/in and associated with the output path — but rather is only associated with the clock distribution and transmission circuitry of the logic tiles.

In addition, as described above, while each clock path of the logic tiles of FIGS. 2A-2C includes at least one U-turn circuit, one or more logic tiles may include a clock path that does not include a U-turn circuit. Also, as described above, the U-turn circuits provided at each output path may be the same or different types of circuits — for example, at a first output path, the U-turn circuit may be composed of one buffer, and at a second output path, the U-turn circuit may be composed of two or more buffers.

In practice, U-turn circuitry in a logic tile may be added to the clock path to program or balance the clock offset and/or phase between the clock signals of the logic tile (e.g., maintain substantially no offset or zero offset). Circuits or circuit configurations other than U-turn circuits may be employed to program or balance clock offsets and/or phases by adding, matching, or providing programmable delays to the clock signals of the logic tiles.

Moreover, while the clock distribution and transmission paths for the logic tiles of one or more programmable/configurable logic circuitry may generate independent tile clocks (e.g., using independent asynchronous input clocks), not all of the logic tiles of the programmable/configurable logic circuitry may generate and/or distribute such independent clocks. For example, referring to fig. 10, logical tile 3 does not generate one or more tile clocks corresponding to clock 1, and logical tile 4 does not generate one or more tile clocks corresponding to clock 2. Similarly, logical tile 2 does not generate one or more tile clocks corresponding to clock 2 — however, the clock distribution path for clock 2 includes logical tile 2.

In addition, it may be advantageous to disable those buffers, transistors (and other active or passive elements) in the unselected portions of the clock paths or portions of the clock distribution and transmission circuitry (hereinafter collectively referred to as "unselected circuitry") that are not added to the logic tiles of the clock distribution, generation, and/or transmission paths. For example, referring to fig. 9, the U-turn circuitry and output buffers of the entire south clock path and/or the north clock path may be disabled (e.g., permanently disabled or if and until the clock path is reconfigured or reprogrammed-e.g., in-situ or during testing). In one embodiment, circuitry may be disabled (e.g., during design and/or manufacturing) by not propagating or providing power to such unselected portions. In another embodiment, the circuitry may be disabled via one or more control signals from, for example, the control circuitry.

The present invention may be used in conjunction with any "shaped" tile, including, for example, square, rectangular, trapezoidal, pentagonal, and/or hexagonal. In the case where the propagation delay of the clock input and output paths in one direction is different from the other direction (e.g., the delay introduced in the vertical direction is different from the delay introduced in the horizontal direction), the control circuitry may program the clock distribution paths to provide the relationship of the horizontal and vertical propagation delay components between the tiles. For example, referring to fig. 11, exemplary clock distribution and transmission circuitry for a logic tile of rectangular shape includes input and output clock signal path lengths that are different in the vertical direction than in the horizontal direction, and thus, the input and output paths for the logic tile may include one input/output and U-turn circuitry to introduce additional vertical and horizontal propagation delay components for the clock signal path (where the vertical path length is different than the horizontal path). In these cases, the relationship of the vertical clock signal line propagation delay and the horizontal clock signal line propagation delay may be separately determined, calculated, and/or compensated by the control circuitry (and/or the clock distribution and transmission circuitry) in determining a predetermined or desired offset (e.g., no offset or zero offset) between the logic tiles.

Referring to fig. 12, exemplary clock distribution and distribution paths and their directions are indicated by bold lines and arrows, wherein the clock distribution and transmission circuitry of each logic tile is configured or programmed to provide clock distribution and distribution paths (each having the same vertical and horizontal propagation delay components-i.e., 5 horizontal propagation delay components and 2 vertical propagation delay components in this exemplary embodiment) that provide exemplary programming relationships (here, substantially no offset or zero offset) of the tile clock signals employed by each logic tile. In this exemplary embodiment, a clock signal input is received by logic tile 1, which logic tile 1, in addition to distributing and sending the clock signal to logic tile 2, also incorporates a delay (which includes both the vertical and horizontal components of the propagation delay) that provides a predetermined relationship of the clock signal employed by logic tile 1 to the clock signals of logic tiles 2-5 (and, in some embodiments, one, some, or all of the other logic tiles of the programmable/configurable logic circuitry). In this exemplary embodiment, each logic tile has added the same clock delay (5 horizontal and 2 vertical) using U-turn circuitry in some cases to balance the clock skew between the logic tiles.

Thus, although many embodiments are described in the context of square shaped tiles (where the vertical and horizontal components of the propagation delay are equal or substantially equal), the invention may be implemented where the lengths of the vertical and horizontal clock signal lines are not equal. In these cases, the relationship of the clock signal line delay to the vertical and horizontal delays may be determined and/or calculated by the control circuitry separately, and thereafter suitably configured to provide a predetermined clock offset (zero in fig. 12). All of the inventions described and illustrated herein are fully applicable to non-square logic tile shapes or logic tiles where the vertical component of the propagation delay is different from the horizontal component of the propagation delay. For the sake of brevity, the discussion of the invention set forth herein in connection with non-square shaped tiles (or logic tiles having an amount of propagation delay in a first direction on the logic tile that is different from an amount of propagation delay in a second direction on the logic tile) will not be repeated. Thus, no separate discussion is provided for each logical tile shape; however, based on the present disclosure, applicability to, for example, squares, rectangles, trapezoids, pentagons, and/or hexagons, and/or logic tiles having different propagation delay components, for example, based on the direction of the clock path, will be clear to one of ordinary skill in the art).

Notably, the present invention is applicable to clock circuitry and architectures beyond the x-y dimension or plane. For example, in the context of a 3-D integrated circuit chip, where tiles may exist on different silicon layers or where a clock architecture passes vertically within the integrated circuit, the clock paths will be matched in the z-dimension or plane. It is believed that the applicability of the invention described and/or illustrated herein to dimensions or planes in excess of the x-y dimension will be apparent to those of ordinary skill in the art in view of this application.

Referring to fig. 13A, the clock distribution and transmission circuitry of a logic tile may include tile clock enable/disable circuitry to responsively enable or disable generation and/or output of a local tile clock (i.e., tile clock) of the logic tile (which local tile clock, as discussed herein, may be employed by, for example, logic circuitry (and/or memory) to implement the functionality or operation of the associated logic tile and/or synchronize communication with external inputs and outputs of other logic tiles and/or programmable/configurable logic circuitry). The tile clock enable/disable circuitry is controlled by control circuitry-e.g., in the logic tiles and/or external to the array of logic tiles (such as, for example, "control circuitry" in fig. 1A). In one embodiment, one or more control signals are applied to tile clock enable/disable circuitry to disable generation and/or output of local tile clocks; here, the default case for the circuitry is to enable the generation and/or output of the local tile clock. It is noted that while in this exemplary embodiment the tile clock enable/disable circuitry is an AND (AND) logic gate, any logic or circuitry may be employed — all of which are intended to fall within the scope of the present invention.

For the avoidance of doubt, the clock distribution and transmission circuitry of the logical tiles of any and all embodiments described and/or illustrated herein may include tile clock enable/disable circuitry. For the sake of brevity, a separate discussion/illustration of each embodiment implementing such clock distribution and transmission circuitry is not provided; however, such implementation will be clear to one of ordinary skill in the art based on this disclosure.

Referring to FIG. 13B, in another embodiment, the clock distribution and transmission circuitry of the logic tiles of the array of logic tiles further includes circuitry for receiving and employing a grid clock signal in the logic tiles related to one or more functions/operations implemented by the one or more logic tiles. Here, the clock grid provides a grid clock signal to the logic tiles. Note that this clock grid is different from the "clock grid" structure in fig. 7B, which is implemented using multiplexer inputs. In a common silicon design, rather than shorting the multiple inputs of the multiplexer together as in fig. 7B and/or 7C, the on-chip clock grids are shorted together using metallization/wiring. For example, in one embodiment, an array of multiple logical tiles receives one or more separate clock signals (as described above) and a grid clock (via a clock grid architecture), which may be assigned to each logical tile and employed by the logical tile to perform various functions/operations. The control circuitry may enable use of the grid clock (in place of other clock signals) within one or more logic tiles of the array and in relation to one or more functions/operations implemented by the one or more logic tiles.

Referring to fig. 13B-13D, in one embodiment, the clock distribution and transmission circuitry includes clock selection circuitry (e.g., one or more clock selection multiplexers) to selectively and responsively output one of the signals for use as a local clock signal (i.e., a tile clock) in an associated logic tile when performing or relating to one or more functions/operations implemented by the one or more logic tiles. With continued reference to FIG. 13B, in one embodiment, the clock selection circuitry includes one or more clock selection multiplexers. Here, the control circuitry selectively enables use of the clock grid signal via control of a clock selection multiplexer that receives a plurality of clock signals (including the clock grid clock). In this embodiment, the clock distribution and transmission circuitry for the logic tiles of the physical array of logic tiles also includes a plurality of input and output paths (four paths in this illustrated embodiment-labeled "north clock path," "east clock path," "south clock path," and "west clock path") to receive and/or generate tile clock signals with desired or programmable offsets, and additionally to receive clock grid signals (via a grid clock layout). The logic tiles employ a given clock signal (e.g., a grid clock signal) by selectively controlling the clock selection multiplexer(s). That is, in one embodiment, the clock selection multiplexer responsively outputs either the grid clock signal or an internally generated/derived clock signal (e.g., a delay matched clock signal generated using any of the circuitry and/or techniques described above) as the tile clock used by the circuitry of the logic tile to perform or perform, for example, a function and/or operation. The control circuitry may enable use of the grid clock (in lieu of other clock signals) within and in relation to one or more functions/operations implemented by one or more logic tiles via control of such clock selection multiplexer(s).

Thus, in one embodiment, the clock selection multiplexer responsively outputs either the grid clock signal or an internally generated/derived clock signal (e.g., a delay matched clock signal) as the tile clock used by the circuitry of the logic tile to perform or perform, for example, a function and/or operation. Notably, in one embodiment, the clock selection multiplexers are controlled separately/independently (e.g., via separate select/control signals applied to one or more clock selection multiplexers) from other clock selection multiplexers in one or more logic tiles; in another embodiment, the clock selection multiplexers of one or more logic tiles are controlled as a group (e.g., via a select/control signal).

In one embodiment, the control circuitry determines the use of a particular clock signal within a given logic tile on a tile-by-tile basis or a tile group-by-tile basis. That is, one or more logic tiles may employ an internally generated tile clock (based on, for example, a delay matched clock signal), and one or more other logic tiles may employ a grid clock signal provided to the logic tiles via a clock grid of the clock grid architecture. The control circuitry may enable use of the grid clock signal (in place of other clock signals) within one or more logic tiles (on a logic tile-by-logic tile basis) individually and/or solely via control of such clock selection multiplexer(s) -e.g., in connection with one or more functions/operations implemented by such one or more logic tiles. For example, the control circuitry may apply control signals to (i) clock selection circuitry (e.g., a clock selection multiplexer) associated with or of a first group of one or more logical tiles to responsively output and employ the grid clock in the first group of one or more logical tiles, and (i) clock selection circuitry (e.g., a clock selection multiplexer) associated with or of a second group of one or more logical tiles to responsively output and employ the internally generated tile clock in the second group of one or more logical tiles (e.g., based on the delay-matched clock signal). Indeed, in one embodiment, the control circuitry may control the clock selection circuitry in the logic tiles individually or solely (e.g., control the clock selection multiplexers via applying different input selection signals to the multiplexers within a given logic tile) in order to facilitate the implementation or use of more than one clock signal within a logic tile.

In yet another embodiment, control circuitry (which may include or be a memory, for example, storing data representing control signals) may apply control signals to clock selection multiplexers associated with all of the logic tiles to responsively output and employ (i) a grid clock signal in a first set of one or more logic tiles, or (ii) an internally generated tile clock (e.g., based on a delay matched clock signal). Notably, such control signals may be stored in memory and applied to one or more clock selection circuitry (e.g., clock selection multiplexers) during configuration or reconfiguration of the associated logic tile (e.g., at startup/initialization). In one embodiment, for a given configuration of logic tiles of the array of logic tiles (i.e., until such logic tiles are reconfigured), the control of the clock selection multiplexer is fixed. In another embodiment, the control signals may be modified in-situ (i.e., during operation of the FPGA or integrated circuit). For example, the clock signal employed by one or more logic tiles (or circuitry within one or more logic tiles) may change during operation, e.g., based on the function of such one or more logic tiles, the performance or performance of the operation, and/or the communication.

It is noted that in the case where the data state of the control signal is stored in memory, such data of the control signal may be fixed (startup/initialization) or dynamic (modifiable after startup/initialization). Here, the control circuitry includes memory that stores the data state(s) of the control signals. Referring to FIG. 13C, in one embodiment, the data state(s) stored in the memory may then be read and applied as control signals to clock selection circuitry (in one embodiment, the clock selection circuitry is or includes an embodiment of one or more clock selection multiplexers — see, e.g., FIG. 13B) to enable the use of one or more particular tile clocks (local clock signals) within the associated logic tile.

It is worthy to note that the clock grid architecture and circuitry may be implemented in any of the embodiments described and/or illustrated herein. For the sake of brevity, a separate discussion/illustration of each embodiment implementing the clock grid architecture is not provided; however, such implementation will be clear to one of ordinary skill in the art based on this disclosure. Moreover, the clock grid and circuitry associated therewith of FIG. 13B may be implemented in conjunction with the tile clock enable/disable circuitry of FIG. 13A, such that in one embodiment, when a logic tile employs a grid clock, the tile clock enable/disable circuitry may disable the generation and output of a local tile clock generated from or using a transmit/distributed and delay matched clock signal input to the logic tile on one or more peripherals of the array (e.g., see FIGS. 3A-3G).

The term "circuitry" means, among other things, a circuit (whether integrated or otherwise), a set of such circuits, one or more processors, one or more state machines, one or more processors implementing software, one or more gate arrays, programmable gate arrays, and/or field programmable gate arrays, or a combination of one or more circuits (whether integrated or otherwise), one or more state machines, one or more processors implementing software, one or more gate arrays, programmable gate arrays, and/or field programmable gate arrays. The term "data" means, among other things, current or voltage signal(s) (plural or singular), whether in analog or digital form, which may be a single bit (or the like) or a plurality of bits (or the like).

The memory storing the data, equations, relationships, and/or lookup tables may be permanent, semi-permanent, or temporary (i.e., until reprogrammed) storage that is discrete or resident (i.e., integrated) in, for example, the control circuitry. In conjunction with the present invention, the memory may store programmable offset relationships (whether zero or non-zero) between tile clock signals and tile clocks for logic tiles of the programmable/configurable logic circuitry. Thus, in one embodiment, the memory may be one-time programmable, or the data, equations, relationships, and/or look-up tables employed by the control circuitry may be one-time programmable (e.g., programmed during testing or at manufacture). In another embodiment, the memory is programmable more than once, so that the predetermined values and/or frequency band ranges employed by the control circuitry can be modified after testing and/or manufacturing.

Notably, the U-turn circuit has been described as being comprised of buffers. However, the U-turn circuitry may be comprised of any now known or later developed active or passive elements that may be employed to generate a desired or programmable offset and/or phase of the tile clock signal relative to other logic tiles of the programmable/configurable logic circuitry of the integrated circuit. For example, in one embodiment, one or more conventional types of buffers may be employed.

As mentioned above, the techniques described herein may be implemented using one or more processors (suitably programmed) that perform, and/or evaluate one or more of the functions or operations described herein to generate the clock signal distribution and transmission network or architecture of the present invention.

It is noted that the various circuits, circuitry, and techniques disclosed herein may be described using computer-aided design tools and expressed (or represented) as data and/or instructions implemented in various computer-readable media in terms of their behavior, register transfer, logic components, transistors, layout geometries, and/or other characteristics. The formats of files and other objects in which such circuits, circuitry, layout, and routing expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog and HLDL, formats supporting register level description languages such as RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES, and any other formats and/or languages now known or later developed. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.).

Indeed, when such data and/or instruction-based expressions of the above-described circuits are received within a computer system via one or more computer-readable media, they may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs, including but not limited to netlist generation programs, place and route programs, and the like, to generate a representation or image of a physical representation (simulation) of such circuits. Such representations or images may thereafter be used in device fabrication, for example, by enabling the generation of one or more masks used to form various components of the circuit during device fabrication.

Moreover, the various circuits and circuitry and techniques disclosed herein may be represented via simulations using computer-aided design and/or testing tools. The simulation of the charging circuitry, control circuitry, and/or monitoring circuitry and/or techniques implemented thereby may be implemented by a computer system, wherein the characteristics and operation of such circuitry, and techniques implemented thereby, are simulated, replicated, and/or predicted via the computer system. The present invention also relates to such simulation of the inventive charging circuitry, control circuitry and/or monitoring circuitry and/or techniques implemented thereby, and is therefore intended to fall within the scope of the present invention. Computer-readable media corresponding to such simulation and/or testing tools are also intended to fall within the scope of the present invention.

It is worthy to note that any reference herein to "one embodiment" or "an embodiment" (or the like) means that a particular feature, structure, or characteristic described in connection with the embodiment can be included, employed, and/or combined in one, some, or all embodiments of the invention. The use or appearance of the phrases "in one embodiment" or "in another embodiment" (or the like) in the specification is not intended to refer to the same embodiment, nor is it intended to refer to a separate or alternative embodiment that is necessarily mutually exclusive of one or more other embodiments, nor is it intended to be limited to a single exclusive embodiment. The same applies to the term "implementation". The present invention is not limited to any single aspect or embodiment thereof, nor to any combination and/or permutation of such aspects and/or embodiments. Moreover, each aspect of the present invention and/or embodiments thereof may be employed alone or in combination with one or more other aspects of the present invention and/or embodiments thereof. For the sake of brevity, certain permutations and combinations are not discussed and/or illustrated separately herein.

Additionally, embodiments or implementations described herein as "exemplary" are not to be construed as preferred or advantageous, for example, over other embodiments or implementations; but is intended to convey or indicate that the embodiment(s) is (are) an example embodiment(s).

Finally, while the invention has been described in certain specific aspects, many additional modifications and variations will be apparent to those skilled in the art. It is therefore to be understood that the invention may be practiced otherwise than as specifically described without departing from the scope and spirit of the present invention. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.

The terms "first," "second," and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Furthermore, the terms "a" and "an" herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced item.

Additionally, the term "logic tile" means a design unit or block of, for example, a plurality of transistors (typically in excess of thousands) connected or configured into a programmable component (e.g., a programmable logic component), which in this application can be connected to one or more adjacent "logic tiles" (e.g., in operation or during operation). The term (i) "integrated circuit" means, among other things, a processor, controller, state machine, gate array, SOC, PGA, and/or FPGA.

Furthermore, the term "data" may mean, among other things, current or voltage signal(s) (which may be a single bit (or the like) or multiple bits (or the like)) whether in analog or digital form. The term "zero offset" means a zero offset or a substantially zero offset (i.e., within 10% of the zero offset).

The terms "comprises," "comprising," "including," "includes," "including," "has," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, circuit, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Throughout this document, the use of the terms "connect (connected)", "connected (connected)", "connecting (connecting)", or "connecting (connecting)" should be interpreted broadly to include direct or indirect (e.g., via one or more conductors and/or intermediate devices/elements (active or passive) and/or via inductive or capacitive coupling)) unless otherwise stated (e.g., using the terms "directly connect" or "directly connected").