Method for reducing chip power consumption by adopting distributed monitoring circuit
阅读说明：本技术 一种采用分布式监测电路降低芯片功耗的方法 (Method for reducing chip power consumption by adopting distributed monitoring circuit ) 是由 陆会贤 王云飞 王鹏 黄胜操 张玉成 陈海华 石晶林 于 2019-08-14 设计创作，主要内容包括：本发明公开了一种采用分布式监测电路降低芯片功耗的方法,一、将芯片按照功能模块划分为多个电压区域,每个电压区域设置多个监测电路；二、对各个监测电路根据各自的功能设置电压阈值,若所监测的电压大于等于自身的电压阈值,则输出1,否则,输出为0；三、对任一电压区域内电压的调节策略：i.当电压区域内所有监测电路的输出均为1时,则降低工作电压；ii.当电压区域内仅有1个监测电路输出为0时,则保持现有电压；iii.当电压区域内有大于1个监测电路输出为0时,则提高工作电压,直到该电压区域内所有监测电路均输出为1,本发明能够获得每个电压区域内详细、准确的电路工作状态,实时调整每个电压区域的电压。(The invention discloses a method for reducing chip power consumption by adopting a distributed monitoring circuit, which comprises the following steps of dividing a chip into a plurality of voltage areas according to a functional module, and arranging a plurality of monitoring circuits in each voltage area; setting a voltage threshold value for each monitoring circuit according to respective functions, if the monitored voltage is greater than or equal to the voltage threshold value of the monitoring circuit, outputting 1, and if not, outputting 0; thirdly, adjusting the voltage in any voltage region: i. when the output of all monitoring circuits in the voltage area is 1, reducing the working voltage; when only 1 monitoring circuit output in the voltage region is 0, maintaining the existing voltage; and iii, when more than 1 monitoring circuit in the voltage region outputs 0, increasing the working voltage until all monitoring circuits in the voltage region output 1.)
1. A method for reducing chip power consumption by adopting a distributed monitoring circuit is characterized by comprising the following steps:
dividing a chip into a plurality of voltage areas according to a functional module, wherein each voltage area is provided with a plurality of monitoring circuits;
step two, setting a voltage threshold value for each monitoring circuit according to respective functions, if the monitored voltage is greater than or equal to the voltage threshold value of the monitoring circuit, outputting 1, and if not, outputting 0;
step three, adjusting the voltage in any voltage area:
i. when the output of all monitoring circuits in the voltage area is 1, reducing the working voltage;
when only 1 monitoring circuit output in the voltage region is 0, maintaining the existing voltage;
and iii, when more than 1 monitoring circuit in the voltage region outputs 0, increasing the working voltage until all monitoring circuits in the voltage region output 1.
2. The method of claim 1, wherein the functional modules comprise a data moving module, a matrix operation module and a memory read-write module.
Technical Field
The invention belongs to the technical field of system chips, and particularly relates to a method for reducing chip power consumption by adopting a distributed monitoring circuit.
Background
With the complication of chip application scenes, various applications have higher and higher requirements on chips, and in order to realize more complex functions, the area of a chip is gradually increased, and the number of transistors on a single chip is increased. With the development of semiconductor process technology, the number of CMOS transistors that a single chip can accommodate has increased substantially according to moore's law. At present, the number of transistors in a complex chip is close to 100 hundred million, and a digital chip is generally manufactured by adopting a CMOS (complementary metal oxide semiconductor) process. The power consumption of semiconductor CMOS circuits mainly comes from three sources: (1) switching power consumption: power consumption for charging a load capacitor when the circuit is turned over; (2) short-circuit power consumption: the power consumption is generated by the simultaneous conduction of a PMOS tube and an NMOS tube; (3) static power consumption: leakage current consumes power when the transistor is not active at all.
The switching power consumption of a CMOS circuit, described by a formula, can be written as:
wherein, CLIs the total load capacitance of the circuit; vddIs the working voltage; ptransFor the probability of the output of the working circuit to be switched, fclockIs the operating clock frequency;
the short-circuit power consumption is the power consumption formed by the instantaneous current when the PMOS and the NMOS are simultaneously turned on during input inversion. The formula description can be written as:
Pshort＝TSC*Vdd*Ipeak*fclock
wherein, TSCFor the duration of the short-circuit current, IpeakIs a short circuit current.
Generally, both the switching power consumption and the short-circuit power consumption are also collectively referred to as dynamic power consumption. From the above 2 formulas, it can be found that the switch power consumption and the short-circuit power consumption have a direct relation with the working voltage. Especially, the switch power consumption and the working voltage are in a square relation, and the effect of reducing the voltage on reducing the power consumption is obvious.
For example, if the operating voltage is 1V and the corresponding switch power consumption is 10W, when the voltage drops by 10%, i.e. the operating voltage is 0.9V, the corresponding switch power consumption is 8.1W and drops by 19%.
Based on this principle, the main techniques for reducing power consumption include:
multi-voltage domain technology: the most basic form is to divide the chip into different voltage domains, wherein the high-performance part is in the high-voltage domain, and the low-performance part is distributed in the low-voltage domain. For example, in an SOC chip, the MCU should operate at the highest possible clock, and its voltage should be the highest voltage; the USB module in the peripheral has a fixed rate defined by a protocol, and only needs to be allocated to a working voltage which can meet the requirement; some modules which do not work normally can even turn off the voltage, so that the power consumption tends to be 0. In such a chip, the voltage domain is divided into various voltage domains. However, most chips are in the worst process condition, so that the working voltage adopted by the method is higher than the actually required voltage, and waste of power consumption is caused.
Dynamic voltage adjustment technology: the magnitude of the working voltage is dynamically adjusted in real time by adopting the magnitude of the load instead of the fixed working frequency. When the working load is small, the working voltage can be reduced; when the work load is large, the work voltage can be increased. However, similar to the drawbacks of the multiple voltage domain technique. Whether software or hardware adjustment methods are adopted, the starting point is the worst process condition, the adjustment precision and effectiveness (time length) are not so accurate, and the waste of power consumption is also brought.
Disclosure of Invention
In view of this, the present invention provides a method for reducing chip power consumption by using a distributed monitoring circuit, which can obtain detailed and accurate circuit operating states in each voltage region and adjust the voltage of each voltage region in real time.
The technical scheme for realizing the invention is as follows:
a method for reducing chip power consumption by adopting a distributed monitoring circuit comprises the following steps:
dividing a chip into a plurality of voltage areas according to a functional module, wherein each voltage area is provided with a plurality of monitoring circuits;
step two, setting a voltage threshold value for each monitoring circuit according to respective functions, if the monitored voltage is greater than or equal to the voltage threshold value of the monitoring circuit, outputting 1, and if not, outputting 0;
step three, adjusting the voltage in any voltage area:
i. when the output of all monitoring circuits in the voltage area is 1, reducing the working voltage;
when only 1 monitoring circuit output in the voltage region is 0, maintaining the existing voltage;
and iii, when more than 1 monitoring circuit in the voltage region outputs 0, increasing the working voltage until all monitoring circuits in the voltage region output 1.
Furthermore, the functional module comprises a data moving module, a matrix operation module and a memory read-write module.
Has the advantages that:
the invention adopts distributed monitoring circuits densely distributed at each position of the chip to master the circuit state of each voltage area and adjust the voltage of each voltage area in real time. The method can not only ensure the stable work of the functional circuit, but also more effectively reduce the working voltage of the chip, and more effectively reduce the power consumption of the chip than the prior method.
Drawings
FIG. 1 is a schematic diagram of the implementation of the method of the present invention.
Detailed Description
The invention is described in detail below by way of example with reference to the accompanying drawings.
The invention provides a method for reducing chip power consumption by adopting a distributed monitoring circuit. The monitoring circuit can embody detailed and accurate circuit working state in a certain voltage area. The voltage of each voltage region is adjusted in real time according to the output of the monitoring circuit. The implementation process of the invention specifically comprises the following steps:
the method comprises the following steps of dividing a chip into a plurality of voltage areas according to a functional module, densely arranging a plurality of monitoring circuits at each physical position of each voltage area, and basically having no influence on the area of the chip because the monitoring circuits occupy extremely small area. The functional modules comprise a data moving module, a matrix calculation module, a memory read-write module and the like.
Step two, setting a voltage threshold value for each monitoring circuit according to respective functions, if the monitored voltage is greater than or equal to the voltage threshold value of the monitoring circuit, outputting 1, and if not, outputting 0; the critical path of the monitoring circuit (the longest connecting line when the transistors in the chip are interconnected is the critical path) is slightly shorter than the critical path of each functional circuit of the current chip, and the critical path can detect the lower limit of the working voltage in one step in advance than the critical path of each functional circuit of the current chip. When the output of the monitoring circuit is '1', the working voltage can meet the time sequence requirement of the monitoring circuit, and the functional circuit can work normally. Once the output of the monitoring circuit is '0', it indicates that the current working voltage may not meet the timing requirement of the monitoring circuit, and if the voltage is further reduced at this time, an error may occur in the functional circuit. According to the output signal of each monitoring circuit, the circuit state of the CMOS tube at different physical positions of the chip can be mastered in real time.
Step three, adjusting the voltage in any voltage area:
i. when the output of all monitoring circuits in the voltage area is 1, the working voltage of the circuit in the area is higher, and the working voltage can be reduced.
When only 1 monitoring circuit in the voltage region outputs 0, the voltage in the region cannot be further reduced, and the existing voltage is maintained;
and iii, when more than 1 monitoring circuit in the voltage region outputs 0, increasing the working voltage until all monitoring circuits in the voltage region output 1.
As shown in fig. 1, which is an embodiment of the present invention, the outermost square box in the figure represents a circuit portion of a complete chip, and the small square boxes in the figure represent the division of a chip into voltage regions, which is 12 voltage regions in this example. The small circles within each voltage region in the figure represent 1 monitoring circuit.
In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.