阅读说明：本技术 虚拟电阻栅极驱动器 (Virtual resistance gate driver ) 是由 王激尧 徐炜 李思龙 于 2019-06-11 设计创作，主要内容包括：本公开提供了“虚拟电阻栅极驱动器”。一种车辆,包括由逆变器操作的电机。所述电机包括栅极驱动器,所述栅极驱动器被配置成利用脉冲宽度调制(PWM)信号来激励所述逆变器的开关。所述栅极驱动器被配置成将所述PWM信号延迟相关量,所述相关量是所述电机引线的电流幅值的函数。所述延迟响应于所述电流的极性为正。(The present disclosure provides a "virtual resistance gate driver". A vehicle includes an electric machine operated by an inverter. The electric machine includes a gate driver configured to energize switches of the inverter with Pulse Width Modulation (PWM) signals. The gate driver is configured to delay the PWM signal by a correlation amount that is a function of a current amplitude of the motor lead. The delay is responsive to the polarity of the current being positive.)

1. A vehicle, comprising:

a motor operated by an inverter; and

a gate driver configured to energize switches of the inverter with a Pulse Width Modulation (PWM) signal and to delay the PWM signal by an amount that is a function of the current amplitude in response to a polarity of a current of the motor lead driven by the switches being positive.

2. The vehicle of claim 1, wherein the function is a constant plus a product of the constant and the magnitude in response to the PWM signal being on.

3. The vehicle of claim 2, wherein the constant is greater than an activation time of the switch.

4. The vehicle of claim 1, wherein the function is a constant minus a product of the constant and the magnitude in response to the PWM signal being off.

5. The vehicle of claim 1, wherein the gate driver is further configured to delay the PWM signal by an amount that is independent of the magnitude in response to the polarity being negative.

6. The vehicle of claim 5, wherein the quantity independent of the magnitude is a constant.

7. The vehicle of claim 6, wherein the constant is greater than an activation time of the switch.

8. The vehicle of claim 1, further comprising a delay block chip configured to cause the delay.

9. The vehicle of claim 1, further comprising a resistor-capacitor circuit configured to cause the delay.

10. A vehicle, comprising:

a motor operated by an inverter; and

a gate driver configured to energize a switch of the inverter with a Pulse Width Modulation (PWM) signal and to delay the PWM signal by an amount independent of an amplitude of a current of the motor lead driven by the switch in response to a polarity of the current being negative.

11. The vehicle of claim 10, wherein the amount is greater than an activation time of the switch.

12. The vehicle of claim 10, wherein the gate driver is further configured to delay the PWM signal by an amount that is a function of the magnitude of the current in response to the polarity being positive.

13. The vehicle of claim 12, wherein the function is a constant plus a product of the constant and the magnitude in response to the PWM signal being on.

14. The vehicle of claim 13, wherein the constant is greater than an activation time of the switch.

15. The vehicle of claim 12, wherein the function is a constant minus a product of the constant and the magnitude in response to the PWM signal being off.

Technical Field

The present disclosure relates to a gate driver generated virtual resistance.

Background

The damping method is used to reduce harmonic distortion at the resonant frequency of the inverter. Passive and active damping methods may be used. While passive methods provide sufficient damping, resistive losses can reduce efficiency. Software-based dummy resistors have been implemented to reduce hardware losses. Such software-based dummy resistors defined and generated by the controller may overburden the controller and degrade performance.

Disclosure of Invention

A vehicle includes an electric machine operated by an inverter. The electric machine includes a gate driver configured to energize switches of the inverter with Pulse Width Modulation (PWM) signals. The gate driver is configured to delay the PWM signal by a correlation amount that is a function of a current amplitude of the motor lead. The delay is responsive to the polarity of the current being positive.

A vehicle includes an electric machine operated by an inverter. The electric machine includes a gate driver configured to energize switches of the inverter with Pulse Width Modulation (PWM) signals. The gate driver is configured to delay the PWM signal by an independent amount that is independent of a current magnitude of the motor lead. The delay is negative in response to the polarity of the current.

A vehicle includes an electric machine operated by an inverter. The electric machine includes a gate driver configured to energize switches of the inverter with Pulse Width Modulation (PWM) signals. The gate driver is configured to delay the PWM signal by a correlation amount that is a function of the current magnitude through the corresponding switch. The delay is responsive to the polarity of the current being positive and the polarity of the current through the corresponding switch being negative.

Drawings

FIG. 1 is a schematic illustration of a vehicle having a motor and an inverter;

FIG. 2A is a schematic diagram of corresponding switches associated with phases of the motor and associated gate drivers with motor lead feedback;

FIG. 2B is a schematic diagram of corresponding switches associated with phases of a motor and associated gate drivers with internal switching feedback;

FIG. 3A is an algorithm for delaying the PWM signal via the gate driver with motor lead feedback;

FIG. 3B is an algorithm for delaying the PWM signal via the gate driver with internal switch feedback;

fig. 4 is a graph depicting current-based PWM signal delay.

FIG. 5A is a schematic diagram of a gate driver circuit with motor lead feedback; and is

Fig. 5B is a schematic diagram of a gate driver circuit with internal switching feedback.

Detailed Description

Embodiments of the present disclosure are described herein. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various and alternative forms. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As one of ordinary skill in the art will appreciate, various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides a representative embodiment for typical applications. However, various combinations and modifications of the features consistent with the teachings of the present disclosure may be desired for particular applications or implementations.

A solution may be implemented to provide a virtual damping resistor for an inverter system at a gate driver. The gate driver energizes the gates of the inverter switches. The switches of the inverter may be Insulated Gate Bipolar Transistors (IGBTs). The gate driver may actuate the switch based on a PWM signal from the microcontroller. The gate driver may modulate the PWM signal to impart characteristics to the virtual damping resistor. The dummy resistor may need to modulate the width of the PWM pulse. To modulate the pulses of the PWM signal, the input PWM signal may be delayed. The delay of the PWM signal allows the PWM pulse to be modulated to an appropriate width that would otherwise be unavailable because the desired modulation period has occurred. For example, if the dummy resistor requires a wider pulse width than would otherwise be provided to the gate driver, the gate driver cannot post-expand the pulse. Accordingly, the input PWM signal is delayed by a predetermined constant. The modulation of the PWM signal that would otherwise be late is delayed less so that the PWM signal is modulated to generate the virtual resistor. In practice, a hardware implemented virtual resistor may be implemented by a gate driver via delay modulation of PWM.

Referring to FIG. 1, a vehicle 100 is shown. Vehicle 100 includes an electric machine 102. Although shown as a Y-shaped configuration, a triangular configuration may also be used. The motor 102 is operated by an inverter 104. The inverter 104 converts Direct Current (DC) from the battery 106 to Alternating Current (AC) for the electric machine 102, and vice versa. The battery supplies power to the rails 108, 110 of the inverter. The capacitor 112 eliminates voltage fluctuations. The switches 120A, 120B, 122A, 122B, 124A, 124B are used to convert DC to AC and energize leads 126A, 126B, 126C of the motor 102. The current on leads 126A, 126B, 126C may be monitored via current sensors 128A, 128B, 128C. The switches 120A, 120B, 122A, 122B, 124A, 124B may also include internal current sensing capabilities (not shown) to monitor the current through the switches 120A, 120B, 122A, 122B, 124A, 124B.

Referring to fig. 2A, a set of corresponding switches 120A, 120B is shown, where a lead 126A feedback 208 is available. The corresponding switches 120A, 120B cooperatively energize the lead 126A of the motor 102. Each of the switches 120A, 120B is operated by a gate driver 202A, 202B, respectively. The gate drivers 202A, 202B receive input PWM signals 204A, 204B and output PWM signals 206A, 206B, respectively. The input PWM signals 204A, 204B may be received from a microcontroller (not shown) configured to form PWM signals. The output PWM signals 206A, 206B are delayed as described below. The gate drivers 202A, 202B receive current feedback 208. Although the gate drivers 202A, 202B are similarly configured, the current feedback polarity of the negative switch 120B is inverted by the negative logic 210 to ensure that the output PWM signal 206B corresponds to the output PWM signal 206A, thereby ensuring a cooperative AC signal on lead 126A.

Referring to fig. 2B, a set of corresponding switches 120A, 120B is shown, where the lead 126A feedback is not available. The corresponding switches 120A, 120B cooperatively energize the lead 126A of the motor 102. Each of the switches 120A, 120B is operated by a gate driver 252A, 252B, respectively. The gate drivers 252A, 252B receive input PWM signals 254A, 254B and output PWM signals 256A, 256B, respectively. The input PWM signals 254A, 254B may be received from a microcontroller (not shown) configured to form PWM signals. The output PWM signals 256A, 256B are delayed as described below. The gate drivers 252A, 252B receive current feedback from the respective switches 120A, 120B and the corresponding switches 120A, 120B. For example, the gate driver 252A receives a current feedback 258 associated with the switch 120A, which provides an output PWM signal 256A. Gate driver 252A also receives current feedback 260 from the corresponding switch 120B. As shown below, the current feedback 258, 260 is used to delay the PWM signal at the gate drivers 252A, 252B. The switches 120A and 120B may provide current feedback 258, 260 through shunts or other devices to provide a current indication. The currents 258, 260 may correspond to voltages across terminals of the switches 120A, 120B. Because the gate drivers 252A, 252B receive current feedback 258, 260 from the switches 120A, 120B, inverter current feedback is not required.

Referring to fig. 3A, an algorithm 300 is shown. The algorithm is implemented in the gate drivers 202A, 202B via hardware or software. The algorithm 300 begins in step 302. In step 304, the gate drivers 202A, 202B detect the polarity of the current feedback 208. If the current feedback is negative in step 304, the input PWM signal is delayed by a constant in step 306. The constant may be greater than an actuation period or a minimum switching period of the switch. The switching period may be 1.0 mus. The constant may be 1.5 mus. If the polarity is positive in step 304, the gate drivers 202A, 202B determine the active state of the PWM signal in step 308. If the PWM signal is on, the input signal is delayed by the constant discussed above plus the product of the constant and the current input in step 310. In step 312, if the PWM signal is off in step 308, the PWM input signal is delayed by a constant minus the product of the constant and the current input. It should be appreciated that the constants may be scaled or that two constants may be used in order to achieve the appropriate delay. This means that the constant and current input can be adjusted by the gain to ensure that a virtual resistor PWM signal is obtained. The first constant may be configured to be 1.5 μ s and the second constant may be configured to be 1.5 μ s per 100 amps. The virtual resistor value may be determined by equation 1,

in which V is_dcFor the bus voltage (400V), Δ TA is 1.5 μ s per 100 amps, and T_SIs 100 mus so that the delay varies from cycle to cycle depending on the current flowing through the switch, giving a virtual resistor and harmonic damping.

Referring to fig. 3B, an algorithm 350 is shown. The algorithm is implemented in the gate drivers 252A, 252B via hardware or software. The algorithm 350 begins in step 352. In step 354, the gate drivers 252A, 252B detect the polarity of the associated current feedback 258. If the current feedback is negative in step 354, the input PWM signal is delayed by a constant in step 356. The constant may be greater than an actuation period or a minimum switching period of the switch. The constant may be 1.5 mus. If the polarity is positive in step 354, the gate drivers 252A, 252B determine the active state of the PWM signal in step 358. In step 360, if the PWM signal is off in step 358, the PWM input signal is delayed by a constant minus the product of the constant and the current input. If the PWM signal is on in step 358, the gate drivers 252A, 252B delay the PWM signal based on the corresponding gate driver currents. This means that if the corresponding gate driver current is negative, then the input PWM signal is delayed by a constant plus the product of the constant and the corresponding gate driver current in step 366. Thus, gate driver 252A will first look at its own current feedback 258, and if the PWM signal is on, gate driver 252A will next look at the current feedback 260 of the corresponding gate driver 252B to determine whether to delay by some constant or a constant plus a product. It should be appreciated that the constants may be scaled or two constants may be used in order to achieve the appropriate delay, as described above. This means that the constant and current input can be adjusted by the gain to ensure that a virtual resistor PWM signal is obtained. The first constant may be configured to be 1.5 μ s and the second constant may be configured to be 1.5 μ s per 100 amps.

Referring to fig. 4, a graph 400 is shown having an x-axis 404 in units of time and a y-axis 402 indicating the state of the PWM signal. The output PWM signals 204A, 204B are shown with corresponding output PWM signals 206A, 206B from the gate drivers 202A, 202B. It should be appreciated that gate drivers 252A, 252B operate similarly. The delay 406 is assigned to the output PWM signals 206A, 206B of different lengths 408. The delay 406 of the PWM signals 204A, 204B allows the PWM pulses to be modulated to a width 410 that would otherwise be unavailable because the desired modulation period has occurred. For example, if the dummy resistor requires a pulse width 410 that is wider than otherwise provided to the gate driver, the gate driver cannot post-expand the pulse. Thus, the PWM input signals 204A, 204B are delayed by a predetermined constant 406 plus or minus the variance 408.

Referring to fig. 5A, a schematic diagram of the delay gate driver 202A is shown. The other gate drivers 202B, 252A, 252B may be similarly configured. The gate driver 202A receives an input PWM signal 204A. The gate driver 202A outputs a PWM signal 206A. The output PWM signal 206A drives the switch 120A. The gate driver 202A includes a driver circuit 502 and a delay circuit 506. The input to the delay circuit 506 includes a gain adjustment circuit 504 to ensure that the proper delay is formed by the gate driver 202A. The gain adjustment circuit 504 is fed by the current feedback 208. Delay circuit 506 may be an integrated circuit as known in the art.

Referring to fig. 5B, a schematic diagram of the delay gate driver 202A is shown. The other gate drivers 202B, 252A, 252B may be similarly configured. The gate driver 202A receives an input PWM signal 204A. The gate driver 202A outputs a PWM signal 206A. The output PWM signal 206A drives the switch 120A. The gate driver 202A includes a driver circuit 552. The delay portion of gate driver 202A is provided via xor logic 556 and RC circuit pass filters 558, 560. The logic used in xor logic 556 may be any other logic implementation (e.g., "and" logic, "nand" logic, "nor" logic) or a combination thereof. Logic may be based on current feedback 208 to ensure proper delay of the PWM signal 204A. For example, if current feedback 258 and corresponding current feedback 260 are used, the logic portion may correspond to current feedback 258 and corresponding current feedback 260 (not shown). In addition, the appropriate gains 504, 554 may be positive or negative depending on the configuration of the circuitry used to delay the PWM signal 204A. The current feedback 208 may be adjusted via a gain operational amplifier 554.

The words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the disclosure. As previously mentioned, features of the various embodiments may be combined to form further embodiments of the invention that may not be explicitly described or illustrated. While various embodiments may have been described as providing advantages or being preferred over other embodiments or prior art implementations in terms of one or more desired characteristics, those of ordinary skill in the art will recognize that one or more features or characteristics may be compromised to achieve desired overall system attributes, which depend on the specific application and implementation. These attributes may include, but are not limited to, cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, availability, weight, manufacturability, ease of assembly, and the like. Accordingly, embodiments described as less desirable with respect to one or more characteristics than other embodiments or prior art implementations are outside the scope of the present disclosure and may be desirable for particular applications.

According to the present invention, there is provided a vehicle having: a motor operated by an inverter; and a gate driver configured to energize switches of the inverter with a Pulse Width Modulation (PWM) signal and to delay the PWM signal by an amount that is a function of the current amplitude in response to a current polarity of the motor lead driven by the switches being positive.

According to one embodiment, in response to the PWM signal being on, the function is a constant plus a product of the constant and the amplitude.

According to one embodiment, the constant is greater than an actuation time of the switch.

According to one embodiment, the function is a constant minus a product of the constant and the amplitude in response to the PWM signal being off.

According to one embodiment, the gate driver is further configured to delay the PWM signal by an amount independent of the amplitude in response to the polarity being negative.

According to one embodiment, the magnitude independent quantity is a constant.

According to one embodiment, the constant is greater than an actuation time of the switch.

According to one embodiment, the above invention also features a delay block chip configured to cause the delay.

According to one embodiment, the above invention also features a resistor-capacitor circuit configured to cause the delay.

According to the present invention, there is provided a vehicle having: a motor operated by an inverter; and a gate driver configured to energize switches of the inverter with a Pulse Width Modulation (PWM) signal and to delay the PWM signal by an amount that is independent of an amplitude of a current of the motor lead driven by the switches in response to the polarity of the current being negative.

According to one embodiment, said amount is greater than an actuation time of said switch.

According to one embodiment, the gate driver is further configured to delay the PWM signal by an amount that is a function of the current amplitude in response to the polarity being positive.

According to one embodiment, in response to the PWM signal being on, the function is a constant plus a product of the constant and the amplitude.

According to one embodiment, the constant is greater than an actuation time of the switch.

According to one embodiment, the function is a constant minus a product of the constant and the amplitude in response to the PWM signal being off.

According to one embodiment, the constant is greater than an actuation time of the switch.

According to the present invention, there is provided a vehicle having: a motor operated by an inverter; and a gate driver configured to energize switches of the inverter with Pulse Width Modulation (PWM) signals and to delay the PWM signals by a correlation amount that is a function of the magnitude of the current through the corresponding switch in response to a polarity of the current through the switch being positive and a polarity of the current through the corresponding switch being negative.

According to one embodiment, in response to the PWM signal being on, the function is a constant plus a product of the constant and the magnitude of the current through the corresponding switch.

According to one embodiment, the constant is greater than an actuation time of the switch.

According to one embodiment, in response to the PWM signal being off, the function is a constant minus a product of the constant and the magnitude of the current through the corresponding switch.