阅读说明：本技术 一种发动机转速监控电路 (Engine rotating speed monitoring circuit ) 是由 李有池 李金宝 姜峰 刘海亮 于 2019-10-30 设计创作，主要内容包括：本发明涉及一种发动机转速监控电路,包括比较器、计数器、振荡电路及两路双D触发器；输入的正弦信号经比较器输出为脉冲信号,作为计数器的时钟信号；振荡电路产生的时间基准信号作为计数器的清零信号和两路双D触发器中的前一单元的清零信号和后一单元的时钟信号；计数器的输出经两种组合逻辑译码电路,分别得到分频系数为1/N和1/M的信号,并分别对应输入至两路双D触发器中的前一单元；当计数器所计脉冲数达到低频点N/2或高频点M/2个数时,触发双D触发器中后一单元的输出从低电平跳变到高电平,否则输出一直为低电平。该电路能直接判定发动机转速是否在设定的正常运转区间；监控电路结构简单、体积小、易实现、成本低。(The invention relates to an engine rotating speed monitoring circuit, which comprises a comparator, a counter, an oscillating circuit and two paths of double-D triggers, wherein the two paths of double-D triggers are connected with the comparator; the input sine signal is output as a pulse signal through a comparator and is used as a clock signal of a counter; the time reference signal generated by the oscillation circuit is used as a zero clearing signal of the counter, a zero clearing signal of a previous unit and a clock signal of a next unit in the two paths of double-D triggers; the output of the counter respectively obtains signals with frequency division coefficients of 1/N and 1/M through two combinational logic decoding circuits, and respectively and correspondingly inputs the signals to a previous unit in the two double-D triggers; when the number of pulses counted by the counter reaches the number of low frequency points N/2 or high frequency points M/2, the output of the latter unit in the double-D trigger is triggered to jump from low level to high level, otherwise, the output is always low level. The circuit can directly judge whether the rotating speed of the engine is in a set normal operation interval; the monitoring circuit has the advantages of simple structure, small volume, easy realization and low cost.)

1. An engine rotating speed monitoring circuit is characterized by comprising a comparator, a counter, an oscillating circuit and two paths of double-D triggers;

the input engine rotating speed sine signal is output as a pulse signal with the same frequency as the sine signal through a comparator and is used as a clock signal of a counter;

the time reference signal generated by the oscillation circuit is used as a zero clearing signal of the counter, a zero clearing signal of a previous unit and a clock signal of a next unit in the two paths of double-D triggers;

the output of the counter respectively obtains signals with frequency division coefficients of 1/N and 1/M through two combinational logic decoding circuits, and respectively and correspondingly inputs the signals to a previous unit in the two paths of double-D triggers, and the output of the previous unit is used as the input of a next unit;

when the number of pulses counted by the counter reaches the number of low frequency points N/2 or high frequency points M/2, the output of the latter unit in the double-D trigger is triggered to jump from low level to high level, otherwise, the output is always low level.

2. The engine speed monitoring circuit of claim 1, further comprising a buffer output circuit through which the output of the latter unit of the dual D flip-flop is output.

3. An engine speed monitoring circuit as claimed in claim 2 wherein the buffer output circuit is a triode.

4. The engine speed monitoring circuit of claim 1, wherein the time reference signal is delayed and then used as a zero clearing signal for a previous unit in the counter and the two-way double-D flip-flops.

5. The engine speed monitoring circuit of claim 1, wherein the oscillating circuit comprises a crystal oscillator and a frequency divider, and a signal generated by the crystal oscillator is divided by the frequency divider to output the time reference signal.

6. An engine speed monitoring circuit as claimed in claim 1 or 5, wherein the time reference signal is a 1Hz time reference signal.

7. A circuit for monitoring the speed of an engine as claimed in claim 6, wherein the 32768Hz signal generated by the crystal oscillator in the oscillator circuit is 1/2 through two division factors⁴And 1/2¹¹The two frequency dividers output 1Hz time reference signals after frequency division.

8. An engine speed monitoring circuit as claimed in claim 1 wherein the first combinatorial logic decoding circuit comprises two 3-input and gates; first 3 input AND gate outputs signal 2 of counter²、2⁷、2⁸AND, the second 3-input AND gate outputs the signal from the first 3-input AND gate and the signal 2 from the counter¹¹、2¹²And, the output signal frequency is 6532 Hz.

9. The engine speed monitoring circuit of claim 1, wherein the second combinational logic decoding circuit comprises a third 3-input and gate; third 3 input AND gate outputs signal 2 from counter⁵、2⁸、2⁹And, the output signal frequency is 800 Hz.

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to an engine rotating speed monitoring circuit.

Background

The rotational speed is one of the important parameters of the engine. The measurement and control of the engine speed are usually performed by converting the engine speed into a sine wave signal of a corresponding frequency by a tachogenerator sensor, and then converting the sine wave signal into a pulse signal of a corresponding frequency. The core of the control is a negative feedback closed-loop control system which compares the pulse signal frequency with a set frequency (representing the set rotating speed of the engine) and sends a corresponding control instruction to the engine according to the comparison result.

There are various methods for implementing such a negative feedback closed-loop control system, for example, a frequency-voltage conversion circuit (FVC) is used to convert a pulse signal into a dc voltage, and then the dc voltage is compared with a set reference voltage, and an engine is controlled according to the comparison result to implement a constant speed operation. However, even if the rotation speed monitoring circuit designed by this method uses a high-precision frequency-voltage converter, a precision voltage reference, and a high-precision voltage divider circuit, the rotation speed monitoring circuit does not necessarily satisfy the requirement of high-precision rotation speed control. The rotating speed of the engine is measured and controlled through the central processing unit, the control is flexible, the precision is guaranteed, but the anti-interference capability is poor, and software is involved. The design is complicated if the system requires evaluation of the software.

Disclosure of Invention

In order to solve the problems, the invention designs a high-precision engine rotating speed monitoring circuit which can accurately calculate the rotating speed of an engine and can directly judge whether the rotating speed of the engine is in a set normal operation interval.

The technical solution for realizing the purpose of the invention is as follows:

an engine rotating speed monitoring circuit comprises a comparator, a counter, an oscillating circuit and two paths of double-D triggers;

the input engine rotating speed sine signal is output as a pulse signal with the same frequency as the sine signal through a comparator and is used as a clock signal of a counter;

the time reference signal generated by the oscillation circuit is used as a zero clearing signal of the counter, a zero clearing signal of a previous unit and a clock signal of a next unit in the two paths of double-D triggers;

the output of the counter respectively obtains signals with frequency division coefficients of 1/N and 1/M through two combinational logic decoding circuits, and respectively and correspondingly inputs the signals to a previous unit in the two paths of double-D triggers, and the output of the previous unit is used as the input of a next unit;

when the number of pulses counted by the counter reaches the number of low frequency points N/2 or high frequency points M/2, the output of the latter unit in the double-D trigger is triggered to jump from low level to high level, otherwise, the output is always low level.

Furthermore, the double-D flip-flop further comprises a buffer output circuit, and the output of the latter unit in the double-D flip-flop is output through the buffer output circuit.

Further, the buffer output circuit is a triode.

Furthermore, the time reference signal is delayed and then used as a zero clearing signal of a previous unit in the counter and the two double-D triggers.

Further, the oscillation circuit comprises a crystal oscillator and a frequency divider, and a signal generated by the crystal oscillator is divided by the frequency divider to output a time reference signal.

Further, the time reference signal is a 1Hz time reference signal.

Furthermore, a 32768Hz signal generated by a crystal oscillator in the oscillating circuit is 1/2 through two frequency division coefficients⁴And 1/2¹¹The two frequency dividers output 1Hz time reference signals after frequency division.

Further, the first combinational logic decoding circuit comprises two 3-input AND gates; first 3 input AND gate outputs signal 2 of counter²、2⁷、2⁸AND, the second 3-input AND gate outputs the signal from the first 3-input AND gate and the signal 2 from the counter¹¹、2¹²And, the output signal frequency is 6532 Hz.

Further, the second combinational logic decoding circuit comprises a third 3-input AND gate; third 3 input AND gate outputs signal 2 from counter⁵、2⁸、2⁹And, the output signal frequency is 800 Hz.

The invention has the advantages that:

1. the rotating speed of the monitoring point can be measured with high precision, and the system error is less than 0.2 per mill.

2. The monitoring circuit has the advantages of simple structure, small volume, easy realization and low cost.

Drawings

FIG. 1 is a functional block diagram of an engine speed monitoring circuit of the present invention.

FIG. 2 is a circuit diagram of filtering and comparing of an engine speed monitoring circuit according to the present invention.

FIG. 3 is a circuit diagram of an oscillator, time reference circuit of an engine speed monitoring circuit of the present invention.

FIG. 4 is a circuit diagram of the 1/N and 1/M counters of an engine speed monitoring circuit of the present invention.

Fig. 5 is a circuit diagram of a two-way dual D flip-flop of an engine speed monitoring circuit of the present invention.

Fig. 6 is a circuit diagram of a triode drive of an engine speed monitoring circuit of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The invention discloses an engine speed monitoring circuit which comprises a comparator, a counter, an oscillating circuit, two paths of double-D triggers, a buffer output circuit and the like, and is shown in figure 1. The basic function of the circuit is to output a corresponding high or low level depending on the frequency value of the input signal (representing the engine speed). The input engine speed sine signal is compared by a comparator and then changed into a pulse sequence with corresponding frequency, and the pulse sequence is used as a clock signal of a counter. The time reference signal generated by the high-precision oscillation circuit is applied to the clear terminal CLR of the counter D1, so that the counter always operates in the count-clear-count-clear cycle. According to the actual requirement of monitoring the rotating speed of the engine, the output of the counter forms two decoding circuits by using combinational logic, signals with frequency division coefficients of 1/N and 1/M are obtained (M, N are positive integers, and N is less than or equal to M), and the signals are respectively used as clock signals of a previous unit in the two double-D triggers. Therefore, the output of the decoding circuit can jump from low level to high level only when the pulse number counted by the counter reaches N/2 (low frequency point) or M/2 (high frequency point), otherwise, the output is always low. On the other hand, since the time reference is a signal set to 1Hz, and the counting time provided to the counter is 500ms, if N or M pulses are counted within this time, the minimum frequency of the engine speed input signal should be N (low frequency point) or M (high frequency point). Namely, the high and low frequency points of the normal operation interval of the engine speed are M (Hz) and N (Hz), respectively.

For example, according to the actual requirement of the circuit, the output of the counter is combined with logic to form two decoding circuits, and the counters with frequency division coefficients of 1/800 and 1/6532 are obtained. Which are used as clock signals for one unit of two double-D flip-flops respectively. Therefore, the output of the decoding circuit jumps from low level to high level only when the number of pulses counted by the counter reaches 400 (low frequency point) or 3276 (high frequency point), otherwise, the output is always low. On the other hand, since the time reference is a signal set to 1Hz, and the counting time provided to the counter is 500ms, if it is desired to count 400 or 3276 pulses within this time, the frequency of the engine speed input signal should be at least 800Hz (low frequency point) or 6532 Hz (high frequency point). Namely, the high and low frequency points of the normal operation interval of the engine speed are 6532 Hz and 800Hz, respectively.

The two paths of double-D triggers adopt the following connection method: the input signal of the former unit is always high level, and the output of the former unit is used as the input of the latter unit; the time reference signal is directly used as a clock signal of the next unit and is used as a zero clearing signal of the counter and the previous unit after a certain time delay. The structure ensures that the output of the unit behind the trigger in one path is always high when the frequency of the input signal is greater than N (low frequency point) and the frequency of the input signal in the other path is greater than M (high frequency point), and the output is changed into low when the frequency of the input signal is less than the two values. And the output signals of the latter unit of the two paths of double-D triggers are used as two output ends for monitoring the rotating speed after being driven by the triode to invert the phase.

The time reference signal of the circuit is not only the zero clearing end of the counter and the previous unit of the two double D triggers, but also the clock of the next unit of the double D triggers, and in order to avoid errors caused by logic competition, the time reference signal is delayed by the two inverters and then is sent to the zero clearing end of the counter and the previous unit of the two double D triggers, so that the logic competition is effectively avoided.

As shown in fig. 2, the comparator N1A, the resistors R1, R2, R3, and the capacitor C1 filter, compare, and output an input sinusoidal signal, thereby forming a pulse signal having the same frequency as the sinusoidal signal.

As shown in fig. 3, the crystal oscillator Cy, the not gates D7E, D7F, the resistors R9, R10, the capacitors C4, C5, and the frequency dividers D2 and D3 constitute a time reference generating circuit. The 32768Hz signal generated by the crystal oscillator Cy is divided by a frequency divider D2 (frequency division coefficient 1/2)⁴) And a frequency divider D3 (frequency division coefficient 1/2)¹¹) And outputting a 1Hz time reference signal after frequency division.

As shown in FIG. 4, the counter D1 generates 1/N and 1/M frequency signals through the combinational logic of three 3-input AND gates D4A, D4B, and D4C. The output of the comparator is fed to the clock terminal CLK of the counter D1, and the time reference signal is fed to the clear terminal CLR of the counter D1. So that the counter D1 always operates in a count-clear-count-clear loop. 3-input AND gate D4A outputs signal 2 from counter D1²、2⁷、2⁸AND, the 3-input AND gate D4B compares the signal output from the 3-input AND gate D4A with the signal 2 output from the counter D1¹¹、2¹²And, output signal frequency 6532 Hz; 3-input AND gate D4C outputs signal 2 from counter D1⁵、2⁸、2⁹And, the output signal frequency is 800 Hz.

As shown in fig. 5, the input signal terminals D of the two-way dual D flip-flops D5A, D6A, D5B, and D6B of the previous units D5A and D6A are always at high level, and the output terminal Q thereof is connected to the input terminals D of the next units D5B and D6B; the time reference signal is directly used as the clock CLK of the following cells D5B and D6B, and is delayed by the inverters D7A and D7B for a certain time to be used as the clear signal CLR of the counter D1 and the clear signal R of the preceding cells D5A and D6A. With the structure, the output of the following units D6B and D5B of the double D flip-flop is always high when the frequency of the input signal is greater than N (low frequency point) or M (high frequency point), and the output is low when the frequency is less than the value.

As shown in fig. 6, signals output by the output terminals Q of the two-way double-D flip-flop units D5B and D6B are respectively driven by the triodes V4 and V5 to output signals OUT2 and OUT1 after phase inversion, and the output capability of the circuit is improved by driving the triodes.