阅读说明：本技术 高电压输出放大器 (High voltage output amplifier ) 是由 小仓静雄 于 2019-03-14 设计创作，主要内容包括：提供一种高电压输出放大器,正侧输出级电路的高电压放大器具备Nch MOS FET和Nch MOS FET,负侧输出级电路的高电压放大器具备Nch MOS FET和Nch MOS FET,连接Nch MOS FET的源极和Nch MOS FET的漏极,连接Nch MOS FET的源极和Nch MOS FET的漏极,分别对Nch MOS FET的源极、Nch MOS FET的源极进行电流控制,通过负侧光电耦合器对Nch MOS FET的源极进行电流控制,经过电容器连接了Nch MOS FET的栅极和Nch MOS FET的栅极。(A high-voltage amplifier of a positive-side output stage circuit includes an Nch MOS FET and an Nch MOS FET, a high-voltage amplifier of a negative-side output stage circuit includes an Nch MOS FET and an Nch MOS FET, a source of the Nch MOS FET and a drain of the Nch MOS FET are connected, a source of the Nch MOS FET and a source of the Nch MOS FET are current-controlled, respectively, a source of the Nch MOS FET and a source of the Nch MOS FET are current-controlled by a negative-side photocoupler, and a gate of the Nch MOS FET are connected via a capacitor.)

1. A high-voltage output amplifier is provided with: an input stage circuit provided with a low-voltage amplifier; an output stage circuit having a high voltage amplifier; and a photo coupler interposed between the input stage circuit and the output stage circuit, the input signal being amplified by the low voltage amplifier, the amplified signal being introduced into the high voltage amplifier through the photo coupler and being amplified, and the amplified signal being output from an output terminal, the high voltage output amplifier being characterized in that,

the high-voltage amplifier is provided with at least one Nch MOS FET,

a high voltage is introduced from a high voltage source to the drain of the Nch MOS FET, and a bias voltage of a predetermined voltage value is applied to the gate, thereby controlling the source current by the photocoupler.

2. The high voltage output amplifier of claim 1,

the output stage circuit is provided with a positive side output stage circuit and a negative side output stage circuit, the photoelectric coupler is also provided with a positive side photoelectric coupler and a negative side photoelectric coupler,

a high-voltage amplifier of the positive-side output stage circuit introduces a positive high voltage from the high-voltage source to a drain of the Nch MOS FET, applies a positive bias voltage of a predetermined voltage value to a gate, and controls a source current by the positive-side photocoupler,

the high-voltage amplifier of the negative-side output stage circuit introduces a negative high voltage from the high-voltage source to the source of the Nch MOS FET, and applies a negative bias voltage of a predetermined voltage value to the gate, thereby controlling the source current by the negative-side photocoupler.

3. The high voltage output amplifier of claim 2,

the high-voltage amplifier of the positive-side output stage circuit and the high-voltage amplifier of the negative-side output stage circuit have the Nch MOS FET as a first Nch MOS FET, respectively, a second Nch MOS FET provided, and a drain of the second Nch MOS FET connected to a source of the first Nch MOS FET,

applying a bias voltage of a positive predetermined voltage value to the gate of the second Nch MOS FET on the positive side, applying a bias voltage of a negative predetermined voltage value to the gate of the second Nch MOS FET on the negative side,

the source of the second Nch MOS FET on the positive side is current-controlled by the positive-side photo coupler, and the source of the second Nch MOS FET on the negative side is current-controlled by the negative-side photo coupler.

4. The high voltage output amplifier of claim 3,

means are provided for lowering the impedance of the gate of the first Nch MOS FET of the positive side output stage circuit and the gate of the first Nch MOS FET of the negative side output stage circuit so that these Nch MOS FETs operate virtually by gate grounding.

5. The high voltage output amplifier of claim 4,

as means for virtually operating the Nch MOS FET with the gate grounded, a series circuit of a capacitor of a predetermined capacitance value and a resistor of a predetermined resistance value is connected between the gate of the first Nch MOS FET of the positive side output stage circuit and the gate of the first Nch MOS FET of the negative side output stage circuit.

6. The high voltage output amplifier of any one of claims 1 to 5,

the plurality of photo-couplers are provided in accordance with the magnitude of the output current value, output currents on light receiving sides of the plurality of photo-couplers are merged, and the source of the second Nch MOS FET is current-controlled by the merged output current.

7. A high-voltage output amplifier is provided with: an input stage circuit provided with a low-voltage amplifier; an output stage circuit having a high voltage amplifier; and a photo coupler interposed between the input stage circuit and the output stage circuit, the input signal being amplified by the low voltage amplifier, the amplified signal being introduced into the high voltage amplifier through the photo coupler and being amplified, and the amplified signal being output from an output terminal,

the output stage circuit includes a positive side output stage circuit and a negative side output stage circuit, and the photocoupler also includes a positive side photocoupler and a negative side photocoupler,

the high-voltage amplifier of each of the output stage circuits includes N stages of Nch MOS FETs, a source of one of the Nch MOS FETs and a drain of the second stage of the Nch MOS FET are connected such that a source of the first stage of the Nch MOS FET and a drain of the second stage of the Nch MOS FET are connected,

the source of the Nch MOS FET of the N-stage of the high-voltage amplifier of the positive-side output stage circuit is connected to the drain of the Nch MOS FET of the first stage of the high-voltage amplifier of the negative-side output stage circuit through a resistor,

a voltage of a predetermined positive high voltage value is introduced from a positive high voltage power supply to the drain of the Nch MOS FET of the first stage of the high voltage amplifier of the positive side output stage circuit, and a gate voltage of a predetermined positive voltage value is applied to the gate of the Nch MOS FET of each stage,

a predetermined negative high-voltage value voltage is introduced from a negative high-voltage power supply to the source of the Nth stage of the high-voltage amplifier of the negative-side output stage circuit, and a predetermined negative voltage value gate voltage is applied to the gate of the Nth stage of the Nth MOS FET,

the source of the Nch MOS FET of the nth stage of the positive side output stage circuit is current-controlled by the positive side photo coupler, and the source of the Nch MOS FET of the nth stage of the negative side output stage circuit is current-controlled by the negative side photo coupler.

8. The high voltage output amplifier of claim 7,

in the order of the gate of the Nch MOS FET of the first stage of the high-voltage amplifier of the positive-side output stage circuit and the gate of the Nch MOS FET of the N-1 st stage of the high-voltage amplifier of the negative-side output stage circuit, the gate of the Nch MOS FET of the second stage of the high-voltage amplifier of the positive-side output stage circuit and the gate of the Nch MOS FET of the N-2 nd stage of the high-voltage amplifier of the negative-side output stage circuit, … … the gate of the Nch MOSFET of the N-1 st stage of the high-voltage amplifier of the positive-side output stage circuit and the gate of the Nch MOS FET of the first stage of the high-voltage amplifier of the negative-side output stage circuit, the gates of the Nch MOS FETs of the high-voltage amplifier of the positive-side output stage circuit and the gates of the Nch MOS FETs of the high-voltage amplifier of the negative-side output stage circuit are connected to each other through a capacitor having a predetermined capacitance value.

9. The high voltage output amplifier of claim 8,

a resistor is connected in series to a capacitor that connects the gate of the Nch MOS FET of the high-voltage amplifier of the positive-side output stage circuit and the gate of the Nch MOS FET of the high-voltage amplifier of the negative-side output stage circuit.

10. A high-voltage output amplifier is provided with: an input stage circuit provided with a low-voltage amplifier; an output stage circuit having a high voltage amplifier; and a photo coupler interposed between the input stage circuit and the output stage circuit, amplifying an input signal by the low voltage amplifier, introducing the amplified signal to the high voltage amplifier through the photo coupler, amplifying the signal, and outputting the amplified signal from an output terminal, wherein the high voltage output amplifier is characterized in that,

the output stage circuit includes one or more positive side output stage circuits arranged on a positive side and one or more negative side output stage circuits arranged on a negative side,

the high-voltage amplifier of the positive-side output stage circuit and the negative-side output stage circuit includes at least a first Nch MOS FET and a second Nch MOS FET, a source of the first Nch MOS FET is connected to a drain of the second Nch MOS FET,

the source of the second Nch MOS FET of the high-voltage amplifier of the positive-side output stage circuit is connected to the drain of the first Nch MOS FET of the high-voltage amplifier of the negative-side output stage circuit through a resistor,

a voltage of a positive predetermined voltage value is introduced from a high-voltage power supply to a drain of a first Nch MOS FET of a high-voltage amplifier of the positive side output stage circuit, and bias voltages of the positive predetermined voltage value are applied to a gate of the first Nch MOS FET and a gate of a second Nch MOS FET, respectively,

a voltage of a negative predetermined voltage value is introduced from a high-voltage power supply to a source of a second Nch MOS FET of a high-voltage amplifier of the negative-side output stage circuit, and bias voltages of negative predetermined voltage values are applied to a gate of the first Nch MOS FET and a gate of the second Nch MOS FET, respectively,

the source of the second Nch MOS FET of the high-voltage amplifier of the positive side output stage circuit is current-controlled by the positive side photo coupler, and the source of the second Nch MOSFET of the negative side output stage circuit is current-controlled by the negative side photo coupler.

11. The high voltage output amplifier of claim 10,

the gate of the first Nch MOS FET of the high-voltage amplifier of the positive-side output stage circuit and the gate of the first Nch MOS FET of the high-voltage amplifier of the negative-side output stage circuit are connected at least via a capacitor of a predetermined capacitance value.

12. The high voltage output amplifier of claim 11,

a resistor of a prescribed resistance value is connected in series to the capacitor connected between the gate of the first Nch MOS FET of the positive side output stage circuit and the gate of the first Nch MOS FET of the negative side output stage circuit.

Technical Field

The present invention relates to a high-voltage output amplifier using a negative channel metal oxide semiconductor field effect transistor (hereinafter referred to as "Nch MOS FET") as an output stage, and relates to a high-voltage output amplifier of a high-voltage circuit in which an output stage is constituted by the Nch MOS FET because a high-voltage product cannot be produced by a positive channel metal oxide semiconductor field effect transistor.

Background

Fig. 1 is a diagram showing an example of a circuit configuration of a high-voltage output amplifier of the bypass type positive voltage output in the related art. The output stage of the high-voltage output amplifier includes a pair of Nch MOS fet q101 and Nch MOS fet q102 having source and drain connected in the upper side of fig. 1, and a pair of Nch MOS fet q201 and Nch MOS fet q202 having source and drain connected in the lower side of fig. 1. A resistor R103, a resistor R105 for analog, and a resistor R205 are connected in series between the source of the Nch MOS fet q102 on the upper side and the drain of the Nch MOS fet q201 on the lower side.

Further, the drain of the Nch MOS fet q101 on the upper side is connected to the high-voltage positive power supply + HVps via a resistor R104 for simulation, the resistor R101 is connected between the drain and the gate of the Nch MOS fet q101, and the resistor R102 is connected between the gate of the Nch MOS fet q101 and the gate of the Nch MOS fet q 102. A parallel circuit of the zener diode D102 and the capacitor C101 is connected in parallel to the gate of the Nch MOS fet q102 and the end of the inverted Nch MOS fet q102 of the resistor R103.

Further, a resistor R201 is connected between the drain and gate of the Nch MOS fet q201 on the lower side, and a resistor R202 is connected in parallel to an end portion on the anti-Nch MOS fet q202 side of the resistor R203 connected to the gate of the Nch MOS fet q201 and the source of the Nch MOS fet q 202. A low-voltage negative power supply-V is connected to a connection point between the resistor R202 and the resistor R203 via an analog resistor R204. An output line lout is connected to a connection point between the resistor R105 for analog and the resistor R205 for analog, and serves as an output unit of the high-voltage output amplifier.

The input section of the high-voltage output amplifier includes an operational amplifier U1, an output signal of which is fed back to the input terminal via a series circuit of a resistor R9 and a capacitor C1, and is led to the gate of the NchMOS fet q202 on the lower side of the output stage via a resistor R5. Further, the output signal from the output unit of the high-voltage output amplifier is fed back to the input terminal of the operational amplifier U1 via a circuit in which a parallel circuit of the resistor R2 and the capacitor C2, a parallel circuit of the resistor R3 and the capacitor C3, and a parallel circuit of the resistor R4 and the capacitor C4 are connected in series.

[ patent document 1 ] JP 2016-532339A

In the bypass-type positive voltage output high-voltage output amplifier having the configuration shown in fig. 1, the Nch MOS fet q101 and Nch MOS fet q102 on the upper side of the output stage constitute a constant current source circuit (source constant current source circuit) whose current becomes the maximum output current that can be supplied to the load L including the resistor R501 and the capacitor C501. In the high-voltage output amplifier, the Nch MOS fet q101 and Nch MOS fet q102 on the upper side do not perform source current control, and therefore the efficiency is poor. Although the Nch MOS fet q101 and Nch MOS fet q102 on the upper side can also be controlled by the operational amplifier U1, an expensive DC/DC power supply with high withstand voltage (6100V or more in fig. 1) is required to gate-control the Nch MOS fet q 102.

The operational amplifier U1 controls the gate of the Nch MOS fet q202 so that the output voltage Vout is obtained by absorbing the current obtained by subtracting the output current from the source constant current source circuit in which the source of the Nch MOS fet q201 on the lower side and the drain of the Nch MOS fet q202 are connected, in proportion to the input voltage Vin (in fig. 1, for example, the resistance value of R1 is set to 5k Ω, the resistance values of R2, R3, and R4 are set to 1000k Ω, and the amplification factor G of the operational amplifier U1 is {1+ (R2+ R3+ R4)/R1} (601). Thus, in the high-voltage output amplifier described above, the high-voltage positive power supply + HVps (+6100V) always supplies the maximum power regardless of the output current or the output voltage.

Therefore, the maximum power is consumed by Nch MOS fet q101 and Nch MOS fet q102 and Nch MOS fet q201 and Nch MOS fet q202 at no load. For example, when the current supplied from the source constant current source circuit including Nch MOS fet q101 and Nch MOS fet q102 is 30mA, the source constant current source circuit consumes 30mA × 6100V 183W of electric power as heat. Therefore, in many cases, a circuit for operating the source constant current source circuit only when output is desired is provided, thereby suppressing power consumption when not operating.

In the high-voltage output amplifier shown in fig. 1, as the frequency of the input Vin increases, imbalance occurs in the voltage distribution between Nch MOS FET q101 and Nch MOS FET q102 and the voltage distribution between Nch MOS FET q201 and Nch MOS FET q202, and therefore, it is necessary to have a sufficient margin in the withstand voltage of these Nch MOS FETs, which causes a problem that the Nch MOS FETs become expensive.

Further, the impedance of the gates of Nch MOS fet q101 and Nch MOS fet q201 is high, and the operation of Nch MOS fet q101 and Nch MOS fet q201 is delayed, which also causes a problem that the band of the high-voltage output amplifier is narrowed.

Disclosure of Invention

The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a broadband high-voltage output amplifier that solves the above-described problems, has excellent efficiency, does not require an expensive high-voltage DC/DC power supply for gate control of Nch MOS FETs, can suppress power consumption, does not cause imbalance in voltage distribution between Nch MOS FETs q101 and Nch MOS FET q102 and voltage distribution between Nch MOS FETs q201 and Nch MOS FET q202, and can use the Nch MOS FETs with low voltage resistance.

In order to solve the above problem, the present invention is a high-voltage output amplifier including: an input stage circuit provided with a low-voltage amplifier; an output stage circuit having a high voltage amplifier; and a photocoupler interposed between the input stage circuit and the output stage circuit, for amplifying an input signal by a low voltage amplifier, introducing the amplified signal to a high voltage amplifier through the photocoupler, amplifying the amplified signal, and outputting the amplified signal from an output terminal, wherein the high voltage amplifier includes at least one Nch MOS FET, and a high voltage is introduced from a high voltage source to a drain of the Nch MOS FET, and a bias voltage of a predetermined voltage value is applied to a gate, and a source current is controlled by the photocoupler.

Further, in the high voltage output amplifier, the output stage circuit includes a positive side output stage circuit and a negative side output stage circuit, and the photocoupler also includes a positive side photocoupler and a negative side photocoupler, the high voltage amplifier of the positive side output stage circuit introduces a positive high voltage from the high voltage source to the drain of the Nch MOS FET and applies a positive bias voltage of a predetermined voltage value to the gate to current-control the source by the positive side photocoupler, and the high voltage amplifier of the negative side output stage circuit introduces a negative high voltage from the high voltage source to the source of the Nch MOS FET and applies a negative bias voltage of a predetermined voltage value to the gate to current-control the source by the negative side photocoupler.

In the present invention, the high-voltage amplifier of the positive-side output stage circuit and the high-voltage amplifier of the negative-side output stage circuit are each configured such that the Nch MOS FET is a first Nch MOS FET, a second Nch MOS FET is provided, a drain of the second Nch MOS FET is connected to a source of the first Nch MOS FET, a bias voltage of a positive predetermined voltage value is applied to a gate of the positive-side second Nch MOS FET, a bias voltage of a negative predetermined voltage value is applied to a gate of the negative-side second Nch MOS FET, a source of the positive-side second Nch FET is current-controlled by a positive-side photocoupler, and a source of the negative-side second Nch MOSFET is current-controlled by a negative-side photocoupler.

Further, the present invention is characterized in that the high-voltage output amplifier is provided with means for lowering the impedance of the gate of the first Nch MOS FET of the positive-side output stage circuit and the gate of the first Nch MOS FET of the negative-side output stage circuit so that these Nch MOS FETs operate virtually by gate grounding.

In the high-voltage output amplifier, a series circuit of a capacitor having a predetermined capacitance value and a resistor having a predetermined resistance value is connected between the gate of the first Nch MOS FET of the positive-side output stage circuit and the gate of the first Nch MOS FET of the negative-side output stage circuit as means for virtually operating the Nch MOS FETs with their gates grounded.

In the high-voltage output amplifier, a plurality of photocouplers are provided according to the magnitude of the output current value, the output currents on the light receiving sides of the plurality of photocouplers are merged, and the source of the second Nch MOS FET is current-controlled by the merged output current.

Further, the present invention is a high-voltage output amplifier including: an input stage circuit provided with a low-voltage amplifier; an output stage circuit having a high voltage amplifier; and a photocoupler interposed between the input stage circuit and the output stage circuit, for amplifying an input signal by the low voltage amplifier, introducing the amplified signal into the high voltage amplifier through the photocoupler, amplifying the amplified signal, and outputting the amplified signal from the output terminal, wherein the output stage circuit includes a positive side output stage circuit and a negative side output stage circuit, and the photocoupler also includes a positive side photocoupler and a negative side photocoupler, the high voltage amplifier of each output stage circuit includes N stages of Nch MOS FETs, the source of the Nch MOSFET of a certain stage and the drain of the Nch MOS FET of the secondary stage are connected such that the source of the Nch MOS FET of the first stage is connected to the drain of the Nch MOS FET of the second stage, the source of the Nch MOS FET of the high voltage amplifier of the positive side output stage circuit is connected to the Nch MOS FET of the first stage of the high voltage amplifier of the negative side output stage circuit through a resistor And a drain for supplying a predetermined positive high-voltage value voltage from the positive high-voltage power supply to a drain of the Nch MOS FET of the first stage of the high-voltage amplifier of the positive-side output stage circuit, supplying a predetermined positive voltage value gate voltage to a gate of the Nch MOS FET of each stage, supplying a predetermined negative high-voltage value voltage from the negative high-voltage power supply to a source of the Nth stage of the high-voltage amplifier of the negative-side output stage circuit, supplying a predetermined negative voltage value gate voltage to a gate of the Nch MOS FET of each stage, current-controlling the source of the Nth stage of the positive-side output stage circuit by the positive-side photocoupler, and current-controlling the source of the Nth stage of the negative-side output stage circuit by the negative-side photocoupler.

Further, in the high-voltage output amplifier of the present invention, according to the order of the gate of the Nch MOS FET of the first stage of the high-voltage amplifier of the positive-side output stage circuit and the gate of the Nch MOS FET of the N-1 th stage of the high-voltage amplifier of the negative-side output stage circuit, the gate of the Nch MOS FET of the second stage of the high-voltage amplifier of the positive-side output stage circuit and the gate of the Nch MOS FET of the N-2 th stage of the high-voltage amplifier of the negative-side output stage circuit, the gate of the Nch MOS FET of the N-1 th stage of the high-voltage amplifier of the positive-side output stage circuit and the gate of the Nch MOS FET of the first stage of the high-voltage amplifier of the negative-side output stage circuit, the gates of the Nch MOS FETs of the high-voltage amplifier of the positive-side output stage circuit and the gates of the Nch MOS FETs of the high-voltage amplifier of the negative-side output stage circuit are connected through a capacitor having a predetermined capacitance value.

Further, in the high-voltage output amplifier, a resistor is connected in series to a capacitor connecting a gate of the Nch MOS FET of the high-voltage amplifier of the positive-side output stage circuit and a gate of the Nch MOS FET of the high-voltage amplifier of the negative-side output stage circuit.

Further, the present invention is a high-voltage output amplifier including: an input stage circuit provided with a low-voltage amplifier; an output stage circuit having a high voltage amplifier; and a photocoupler interposed between the input stage circuit and the output stage circuit, for amplifying an input signal by a low voltage amplifier, introducing the amplified signal through the photocoupler into a high voltage amplifier and amplifying the amplified signal, and outputting the amplified signal from an output terminal, wherein the output stage circuit includes one or more positive side output stage circuits disposed on a positive side and one or more negative side output stage circuits disposed on a negative side, the high voltage amplifiers of the positive side output stage circuits and the negative side output stage circuits include at least a first Nch MOSFET and a second Nch MOS FET, a source of the first Nch MOS FET is connected to a drain of the second Nch MOS FET, a source of the second Nch MOS FET of the high voltage amplifier of the positive side output stage circuit is connected to a drain of the first Nch MOS FET of the high voltage amplifier of the negative side output stage circuit through a resistor, a voltage of a positive predetermined voltage value is introduced from a high-voltage power supply to a drain of a first Nch MOS FET of a high-voltage amplifier of a positive-side output stage circuit, a bias voltage of a positive predetermined voltage value is applied to a gate of the first Nch MOS FET and a gate of a second Nch MOS FET, a voltage of a negative predetermined voltage value is introduced from the high-voltage power supply to a source of a second Nch MOS FET of the high-voltage amplifier of a negative-side output stage circuit, a bias voltage of a negative predetermined voltage value is applied to the gate of the first Nch MOS FET and the gate of the second Nch MOS FET, a source of the second Nch MOS FET of the high-voltage amplifier of the positive-side output stage circuit is current-controlled by a positive-side photocoupler, and a source of the second Nch MOS FET of the negative-side output stage circuit is current-controlled by a negative-side photocoupler.

In the high-voltage output amplifier, a gate of the first Nch MOS FET of the high-voltage amplifier of the positive-side output stage circuit and a gate of the first NchMOS FET of the high-voltage amplifier of the negative-side output stage circuit are connected at least via a capacitor having a predetermined capacitance value.

Further, in the high-voltage output amplifier, a resistor having a predetermined resistance value is connected in series to a capacitor connected between the gate of the first Nch MOS FET of the positive-side output stage circuit and the gate of the first Nch MOS FET of the negative-side output stage circuit.

According to the present invention, since the source of the Nch MOS FET is current-controlled by the photocoupler, unlike the method of controlling the gate of the high-voltage output amplifier of the related art, an expensive high-voltage DC/DC converter is not required in this portion, and the circuit configuration of the high-voltage output amplifier is simplified and the low-cost effect can be achieved.

Further, according to the present invention, since the output stage circuit includes the positive side output stage circuit and the negative side output stage circuit, and the photocoupler also includes the positive side photocoupler and the negative side photocoupler, the high voltage amplifier of the positive side output stage circuit current-controls the source of the Nch MOS FET through the positive side photocoupler, and the high voltage amplifier of the negative side output stage circuit current-controls the source of the Nch MOSFET through the negative side photocoupler, it is possible to provide a high voltage output amplifier capable of outputting positive voltage, negative voltage, and positive and negative voltage, which has a simple circuit configuration and can greatly suppress power consumption.

Further, according to the present invention, since the high-voltage amplifier of the positive-side output stage circuit and the high-voltage amplifier of the negative-side output stage circuit connect the drain of the second Nch MOS FET to the source of the first Nch MOS FET and the source of the second Nch MOS FET is current-controlled by the positive-side photocoupler or the negative-side photocoupler, respectively, it is possible to provide a high-voltage output amplifier in which the photocoupler performs current control of the source of the low-impedance Nch MOS FET and the combination with the photocoupler is optimized and which has a wide frequency band.

Further, according to the present invention, since the gate of the first Nch MOS FET of the positive side output stage circuit and the gate of the first Nch MOSFET of the negative side output stage circuit are connected via the capacitor of a predetermined capacitance value, the first Nch MOS FET of the positive and negative sides is virtually grounded by the gate, and the performance thereof is greatly improved as described later.

Further, according to the present invention, it is possible to provide a high-voltage output amplifier that can easily cope with an increase in output current by providing a plurality of photo-couplers depending on the magnitude of the output current value, merging the output currents on the light receiving sides of the plurality of photo-couplers, and current-controlling the source of the second Nch MOS FET by the merged output current.

Drawings

Fig. 1 is a diagram showing a circuit configuration of a bypass-type positive voltage output high-voltage output amplifier according to the related art.

Fig. 2 is a diagram showing an example of the circuit configuration of the high-voltage output amplifier according to the present invention.

Fig. 3 is a diagram showing a sine wave response waveform of the high-voltage output amplifier according to the present invention.

Fig. 4 is a diagram showing a sine wave response waveform of the high-voltage output amplifier according to the present invention.

Fig. 5 is a diagram showing a sine wave response waveform of the high-voltage output amplifier according to the present invention.

Fig. 6 is a diagram showing a sine wave response waveform of the high-voltage output amplifier according to the present invention.

Fig. 7 is a diagram showing a sine wave response waveform of the high-voltage output amplifier according to the present invention.

Fig. 8 is a diagram showing a sine wave response waveform of the high-voltage output amplifier according to the present invention.

Fig. 9 is a diagram showing a sine wave response waveform of the high-voltage output amplifier according to the present invention.

Fig. 10 is a diagram showing a sine wave response waveform of the high-voltage output amplifier according to the present invention.

Fig. 11 is a diagram showing a sine wave response waveform of the high-voltage output amplifier according to the present invention.

Fig. 12 is a diagram showing a sine wave response waveform of the high-voltage output amplifier according to the present invention.

Fig. 13 is a diagram showing an example of the circuit configuration of the high-voltage output amplifier according to the present invention.

Fig. 14 is a diagram showing an example of the circuit configuration of the high-voltage output amplifier according to the present invention.

Fig. 15 is a diagram showing an example of the circuit configuration of the high-voltage output amplifier according to the present invention.

Fig. 16 is a diagram showing an example of the circuit configuration of the high-voltage output amplifier according to the present invention.

Fig. 17 is a diagram showing an example of the circuit configuration of the high-voltage output amplifier according to the present invention.

Fig. 18 is a diagram showing an example of the circuit configuration of the high-voltage output amplifier according to the present invention.

Description of the symbols

C1, C2, C3, C4, C101, C151, C152, C201, C301, C351, C401, C501: capacitor with a capacitor element

D1, D2, D3, D4: diode with a high-voltage source

D101, D102, D103, D201, D202, D203, D301, D302, D303, D401, D402, D403: zener diode

+ HVps: high voltage positive power supply

-HVps: high voltage negative power supply

Q101, Q102, Q103, Q201, Q202, Q203, Q301, Q302, Q401, Q402: nch MOS FET (negative channel metal oxide semiconductor field effect transistor)

R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R101, R102, R103, R104, R105, R106, R107, R108, R151, R152, R201, R202, R203, R204, R205, R206, R207, R208, R301, R302, R303, R304, R305, R307, R308, R351, R352, R401, R402, R403, R404, R405, R407, R408, R501: resistor with a resistor element

L: load(s)

lout: output line

U1: operational amplifier

U101, U102, U103, U201, U202, U203, U301, U401: photoelectric coupler

+ V: low voltage positive power supply

-V: low voltage negative power supply

Detailed Description

Hereinafter, embodiments of the present invention will be described. Fig. 2 is a diagram showing a circuit configuration of a high-voltage output amplifier according to the present invention. The high-voltage output amplifier is capable of realizing a high-voltage positive output and a high-voltage negative output, and includes a pair of Nch MOS FET Q101 and Nch MOS FET Q102 having a source and a drain connected to each other on the positive side (upper side in FIG. 2) of an output stage, and a pair of Nch MOS FET Q201 and Nch MOS FET Q202 having a source and a drain connected to each other on the negative side (lower side in FIG. 2) of the output stage, and the output stage is constituted by only semiconductor elements of the Nch MOS FET. The source (non-gate) of each of Nch MOS fet q102 and Nch MOS fet q202 of the output stage is current-controlled by the photo-coupler U10I and the photo-coupler U201. In addition, + HVps represents a positive high voltage positive supply (e.g., +3100V), -HVps represents a negative high voltage negative supply (e.g., -3100V), -V represents a positive low voltage positive supply (e.g., +15V), -V represents a negative low voltage negative supply (e.g., -15V).

The drain of Nch MOS fet q101 on the positive side of the output stage is connected to the high-voltage positive power supply + HVps via a resistor R105 (for example, 1 Ω) for simulation, and the source thereof is connected to the drain of Nch MOS fet q 102. A zener diode D101 (cathode is a gate, and anode is a source) is connected between the source and the gate of the Nch MOS fet q 101. The source of the Nch MOS fet q102 is connected to one end of a resistor R104 connected to both output ends of the photocoupler U101 through a resistor R103 (e.g., 100 Ω), and the other end of the resistor R104 (e.g., 7.5k Ω) is connected to the output line lout. The output line lout is connected to a resistor R501 as a resistance of the load L and a capacitor C501 as a capacitance after passing through a resistor R152 (for example, 1 Ω) for simulation.

The drain of Nch MOS fet q201 on the negative side of the output stage is connected to the output line lout, and the source thereof is connected to the drain of Nch MOS fet q 202. The Nch MOS fet q202 has a source connected to one end of a resistor R203 (e.g., 100 Ω), and the other end of the resistor R203 is connected to one end of a resistor R204 (e.g., 7.5k Ω) connected to both output ends of the photocoupler U201. The other end of the resistor R204 is connected to a high-voltage negative power supply-HVps via an analog resistor R205 (e.g., 1 Ω).

One end of a resistor R101 (e.g., 3000k Ω) is connected to the drain of the Nch MOS fet q101, and the other end is connected to the other end of a resistor 106 (e.g., 1 Ω) for simulation having one end connected to the gate of the Nch MOS fet q101 and one end of a resistor R102 (e.g., 3000k Ω). The other end of the resistor R102, the gate of the Nch MOS fet q102, and one end of the capacitor C101 (e.g., 10 μ F) are connected to the cathode end of the zener diode D102. The other end of the capacitor C101, the anode end of the zener diode D102, the drain of the Nch MOS fet q201, and one end of the resistor R201 (e.g., 3000k Ω) are connected to the output line lout.

The other end of the resistor R201, the other end of a resistor R206 (for example, 1 Ω) for simulation having one end connected to the gate of the Nch MOS fet q201, and one end of a resistor R202 (for example, 3000k Ω) are connected to each other. The other end of the resistor R202, the gate of the Nch MOS fet q202, the cathode end of the zener diode D202, and one end of the capacitor C201 (e.g., 10 μ F) are connected to each other. The anode terminal of the zener diode D202 and the other terminal of the capacitor C201 are connected to the high voltage negative power supply-HVps via the analog resistor R205 (e.g., 1 Ω). A zener diode D201 (cathode is gate, anode is source) is connected between the source and gate of the Nch MOS fet q 201.

The other end of the capacitor C201 and the anode of the zener diode D202 are connected to the high voltage negative power supply HVps via the resistor R205 as described above. The gate of Nch MOS fet q101 and the gate of Nch MOS fet q201 are connected to each other through a series circuit of a capacitor C151 (for example, 1000pF) and a resistor R151 (for example, 100 Ω).

The input stage of the high-voltage output amplifier includes an operational amplifier U1, a photo coupler U101, and a photo coupler U201. The output terminal of the operational amplifier U1 is connected to the input terminal of the photocoupler U101 via a resistor R5 (e.g., 470 Ω), and is connected to the input terminal of the photocoupler U201 via a resistor R6 (e.g., 470 Ω). Two output terminals (collector and emitter of phototransistor) of the photocoupler U101 are connected to two terminals of a resistor R104 (e.g., 7.5k Ω) of the output stage, and two output terminals (collector and emitter of phototransistor) of the photocoupler U201 are connected to two terminals of a resistor R204 (e.g., 7.5k Ω) of the output stage. The output of the high-voltage output amplifier is fed back to the input section (-) of the operational amplifier U1 via a series circuit in which a parallel circuit of the resistor R4 and the capacitor C4, a parallel circuit of the resistor R3 and the capacitor C3, and a parallel circuit of the resistor R2 and the capacitor C2 are connected in series.

The Nch MOS FETs Q101, Q102, Q201, and Q202 are high-voltage Nch MOS FETs, and if the high-voltage positive/negative power supply ± HVps is ± 3100V, for example, the high-voltage Nch MOS FETs have a withstand voltage of at least 3100V or more, and need about 4000V in terms of redundancy. The zener diode D102 supplies its zener voltage (for example, 10V) from the output voltage to the gate of the Nch MOS fet q102 at all times. The capacitor C101 (for example, 10 μ F) functions to cancel and stabilize the 10V ripple, and functions to hold the gate of the Nch MOS fet q102 at a low impedance.

The resistor R101 has the same resistance value (e.g., 3000k Ω) as the resistor R102, divides a difference voltage (e.g., +3100V) between a voltage of the high-voltage positive power supply + HVps and an output voltage (e.g., +10V) of the output line lout, and supplies a gate voltage to the gate of the Nch MOS fet q 101. Voltage distribution between the drain and source of Nch MOS fet q101 and between the drain and source of NchMOS fet q102 is approximately equal. When the output is-3000V, the voltage between the drain and the source of Nch mosfet q101 and Nch MOS fet q102 becomes maximum, and the voltage is about 3050V.

The zener diode D202 having a zener voltage of about 10V supplies a voltage always higher by the zener voltage (10V) than the voltage of the high-voltage negative power supply-HVps (for example, -3100V) to the gate of the Nch MOS fet q 202. The capacitor C201 is for eliminating and stabilizing the ripple of the zener voltage 10V, and thus functions to keep the gate of the Nch MOS fet q202 low in impedance. The resistor R201 and the resistor R202 have the same resistance value (for example, 3000k Ω), and the voltage of the high-voltage negative power supply-HVps (strictly speaking, the voltage-3090V obtained by adding +10V to the voltage-3100V of the high-voltage negative power supply-HVps) and the output differential voltage are divided by the resistor R201 and the resistor R202, and a potential is supplied to the gate of the Nch MOS fet q 201. The voltage distribution between the drain and source of Nch mosfet q201 and between the drain and source of Nch MOS fet q202 is approximately equal. When +3000V is output, the voltage between the drain and the source of Nch MOS fet q201 and Nch MOS fet q202 becomes maximum, and is about 3050V.

In the case where the output current of the photocoupler U101 is 0, the resistor R103 and the resistor R104 are applied with a voltage value 6V obtained by subtracting the voltage Vgs between the source and the gate of the Nch MOS fet q102 (here, 4V) from the zener voltage 10V of the zener diode D102, so that, for example, if the resistance value of the resistor R103 is 100 Ω and the resistance value of the resistor R104 is 7.5k Ω, the current flowing through the resistor R103 is 6V/7.6k Ω ≈ 0.8 mA. This current value is the minimum drain current of Nch mosfet q101 and Nch MOS fet q102 at no load.

When the output current of the photocoupler U201 is 0, the resistor R203 and the resistor R204 flow a current of 6V/7.6k Ω ≈ 0.8mA in the series circuit of the resistor R203 and the resistor R204 because a voltage value 6V obtained by subtracting a voltage Vgs between the source and the gate of the Nch mosfet q202 (here, 4V) from a zener voltage 10V of the zener diode D202 is applied to both ends of the series circuit, and the current value becomes the minimum drain current of the Nch MOS fet q201 and the Nch MOS fet q 202.

The DC gain of the operational amplifier U1 is { (R2+ R3+ R4)/R1} +1, and for example, if R1 is 10k Ω, R2 is 1000k Ω, R3 is 1000k Ω, and R4 is 1000k Ω, the DC gain is 301 times. The reason why the feedback voltage is divided by the three resistors R2, R3, and R4 is that the feedback voltage of the high voltage is gradually decreased by the three resistors. The frequency band of the amplifier is determined by capacitors C2, C3, and C4 connected in parallel to resistors R2, R3, and R4, and if C2 is 10pF, C3 is 10pF, and C4 is 10pF, the frequency band is 1/(2 pi · 1000k Ω · 10pF) ≈ 16 kHz.

The output of the operational amplifier U1 is input to the photo coupler U101 via the resistor R5, and is input to the photo coupler U201 via the resistor R6. The collector output of the photo-transistor on the light receiving side of the photo-coupler U101 drives (current control) the source of the Nch MOS fet q102, and the collector output of the photo-transistor on the light receiving side of the photo-coupler U201 drives (current control) the source of the Nch MOS fet q 202. Here, the photocoupler U101 functions to separate a high voltage circuit operating at a high voltage positive voltage (+3100V or more) of the high voltage positive power supply + HVps and a low voltage circuit operating at a low positive voltage (+15V) of the low voltage positive power supply + V, and the photocoupler U201 functions to separate a high voltage circuit operating at a high voltage negative voltage (-3100V or less) of the high voltage negative power supply-HVps and a low voltage circuit operating at a low negative voltage (-15V) of the low voltage negative power supply-V.

The withstand voltage of the high-voltage output amplifier requires a high-voltage positive power supply + HVps (here, +3100V) or more or a high-voltage negative power supply-HVps (here, -3100V) or less between the input and the output. Here, the collector output of the photo-transistor on the light receiving side of the photo-coupler U101 drives the low-impedance source of the Nch MOS fet q102, and the collector output of the photo-transistor on the light receiving side of the photo-coupler U201 drives the low-impedance source of the Nch MOS fet q 202. This allows the photocoupler U101 or U201 to directly reflect the performance described in the dataform without degrading the performance.

When a voltage Vin of +5V is input to the + input terminal of the operational amplifier U1, for example, the output is + 1505V. If the resistance value of the resistor R501 of the load L is set to 100k Ω, for example, the current flowing in the resistor R501 is +15.05 mA. The output of the operational amplifier U1 drives the light emitting diode on the light emitting side of the photocoupler U101, and NchMOS fet q101 and NchMOS fet q102 operate so that the current of +15.05mA is supplied from the high voltage positive power supply + HVps to the resistor R501 of the load L. When a voltage of, for example, -5V is input to the + input terminal of the operational amplifier U1, the output becomes-1505V, and the current flowing through the resistor R501 of the load L becomes-15.05 mA. The operational amplifier U1 drives the light emitting diode on the light emitting side of the photocoupler U201, and the Nch MOS fet q201 and Nch MOS fet q202 operate so that the-15.05 mA is absorbed into the resistor R501 of the load L from the high voltage negative power supply-HVps.

The diodes D1 and D2 connected to the inputs of the photocouplers U101 and U201 protect the light emitting diodes on the light emitting sides of the photocouplers U101 and U201 from the input voltage in the opposite direction, respectively, and do not emit light by the voltage applied in the opposite direction. Also, diodes D3, D4 connected to the (-) input terminal of the operational amplifier U1 are used to protect the (-) input terminal from overvoltage input. Further, zener diodes D101 and D201 connected between the source and the gate of the Nch MOS fet q101 and Nch MOS fet q201 are used to protect the gate when an overvoltage is input to the Nch mosfet q101 and Nch MOS fet q201, respectively. The resistors R7 and R8 are elements that reduce distortion at zero crossing.

The capacitor C151 connected between the gate of the Nch MOS fet q101 and the gate of the Nch MOS fet q201 is an important capacitor for extracting the characteristics of the present high-voltage output amplifier. When the output voltage decreases, the Nch mosfet q101 operates so that the current flowing through the drain decreases, and the voltage between the gate and the source decreases. That is, the electric charge accumulated in the gate of the Nch MOS fet q101 is discharged. On the other hand, Nch MOS fet q201 operates to increase the current flowing through the drain, and increase the voltage between the gate and the source. That is, absorption is performed so that electric charge is accumulated at the gate of the Nch mosfet q 201. When the output voltage increases, the above-described operation is reversed.

In the high-voltage output amplifier, for example, when the voltage of the high-voltage positive power supply + HVps is 3100V, the voltage of the high-voltage negative power supply-HVps is-3100V, and the output voltage is +1000V,

gate voltage V of Nch MOS FETQ101_Q101-GComprises the following steps:

(3100V-1000V-10V)/2+1000V+10V＝2055V

gate voltage V of Nch MOS FETQ201_Q201-GComprises the following steps:

1000V-(3100V+1000V-10V)/2＝-1045V。

therefore, the voltage V across the capacitor C151_C151Comprises the following steps:

2055V-(-1045)＝3100V。

when the output voltage was-1000V,

gate voltage V of Nch MOS FETQ101_Q101-GComprises the following steps:

3100V-{3100V-(-1000V)-10V}/2＝1055V

gate voltage V of Nch MOS FETQ201_Q201-GComprises the following steps:

-1000V-(3100V-1000V-10V)/2＝-2045V。

therefore, the voltage V across the capacitor C151_C151Comprises the following steps:

1055V-(-2045V)＝3100V。

from the above results, it is understood that the voltage across the capacitor C151 is always constant regardless of the output voltage. Since the capacitor C151 does not affect the voltage distribution when the circuit of the high-voltage output amplifier ideally operates, there is no problem at all in inserting the capacitor C151 between the gate of the Nch MOS fet q101 and the gate of the Nch MOS fet q 201. In contrast, the capacitor C151 plays an important role in suppressing voltage variation between both ends so that the circuit of the present high-voltage output amplifier approaches an ideal operating state. Here, the capacitance value of the capacitor C151 is targeted to be more than several times the input capacitance of the gates of the Nch MOS fet q101 and Nch mosfet q 201.

To explain further, when the circuit shown in fig. 2 operates ideally, the gate voltage V of the Nch MOS fet q101 is equal to an arbitrary output voltage_Q101-GComprises the following steps:

V_Q101-G＝(+HVps-V_OUT-V_D102)/2+V_OUT+V_D102

＝(+HVps+V_OUT+V_D102)/2

gate voltage V of Nch MOS FETQ201_Q201-GComprises the following steps:

V_Q201-G＝V_OUT-{V_OUT-(-HVps)-V_D202}/2

＝{(-HVps)+V_OUT+V_D202}/2

therefore, the voltage + V across C151_C151Comprises the following steps:

V_C151＝V_Q101-G-V_Q201-G

＝(+HVps+V_OUT+V_D102)/2-{(-HVps)+V_OUT+V_D202}/2

＝+HVps/2-(-HVps)/2＝3100V。

from this result, it can be seen that the voltage across the capacitor C151 is always constant regardless of the output voltage.

From the above facts, Nch MOS fet q101 is opposite to the moving phase of the charge of Nch MOS fet q 201. That is, the gate of Nch MOS fet q101 and the gate of Nch MOS fet q201 satisfy supply-demand relationship of electric charge with each other. A capacitor C151 connected between the gate of the Nch MOS fet q101 and the gate of the Nch MOS fet q201 achieves this object. That is, the capacitor C151 lowers the impedance of the gate of the Nch MOS FET q101 and the gate of the Nch MOS FET q201, and operates these NchMOS FETs virtually by grounding the gates. Further, as described above, the capacitor C151 connected between the gate of the Nch MOS fet q101 and the gate of the Nch MOS fet q201 satisfies the supply-demand relationship of electric charges with respect to the gate of the Nch MOS fet q101 and the gate of the Nch mosfet q 201. In this way, if the gate of Nch MOS fet q101 and the gate of Nch MOS fet q201 satisfy supply-demand relationship of electric charge with each other, other units may be used. That is, it is sufficient if the impedance of the gate of Nch MOS FET q101 and the gate of Nch MOS FET q201 is reduced and these Nch MOS FETs are operated by the gate ground in a dummy manner.

As described above, the Nch MOS fet q101 and Nch MOS fet q201 operate with the gate grounded, so the Nch MOS fet q101 and Nch MOS fet q102 and Nch MOS fet q201 and Nch MOS fet q202 operate in accordance with each other, and the circuit operation is well balanced. In addition, the resistor R151 connected in series with the capacitor C151 is a resistor for preventing generation of unnecessary vibration of the gates of the Nch MOS fet q101 and Nch MOS fet q 201.

The resistors R105, R205, and R152 for simulation have no particular meaning in circuit characteristics, and are arranged to check the current flowing therein. The diodes D1 and D2 protect the light-emitting diodes (LEDs) of the photocouplers U101 and U201 from the input voltage in the opposite direction, and also prevent the light-emitting diodes from emitting light when the voltage in the opposite direction is applied.

Fig. 3 to 10 are diagrams showing the sine wave response waveforms of the high-voltage output amplifier according to the present invention (the high-voltage output amplifier having the circuit configuration shown in fig. 2), and the input frequencies are 1Hz, 10Hz, 100Hz, and 1000 Hz. Here, the capacitor C151 is 0.01pF, and is substantially the same as the capacitor C151. In the figure, V_C151Shows the voltage waveform, V, across the capacitor C151_OUTRepresenting the output voltage waveform, V_Q101-GShows the gate voltage waveform, V, of Nch MOS FETQ101_Q201-GA gate voltage waveform of the Nch MOS fet q201 is shown.

Fig. 3 shows a response waveform of a sine wave with an input frequency of 1Hz when the capacitance value of the capacitor C151 of the high-voltage output amplifier shown in fig. 2 is 0.01 pF. Here, it can be seen that: voltage V between two terminals of capacitor C151_C151Substantially constant, even without the capacitor C151 between the gate of the Nch MOS fet q201 and the gate of the Nch MOS fet q101, the ideal operation of the high-voltage output amplifier can be maintained substantially under the sine wave input with the frequency of 1 Hz.

Fig. 4 shows a response waveform of a sine wave input with a frequency of 1Hz and a capacitor C151 of 1000 pF. Here, the voltage V between both ends of the capacitor C151_C151Approximately constant, gate voltage waveform V at Nch MOS FETQ101_Q101-GGate voltage waveform V of Nch MOS FETQ201_Q201-GRespectively, no abnormality was seen. This makes it possible to prevent the high-voltage output amplifier from operating.

Fig. 5 shows a response waveform of a sine wave input with a frequency of 10Hz and a capacitor C151 of 0.01 pF. Here, the voltage V between the two terminals of the capacitor C151 can be seen_C151A little bitThe gate voltage waveform V varies but in the Nch MOS FETQ101_Q101-GGate voltage waveform V of Nch MOS FETQ201_Q201-GNo anomaly was seen in each. This shows that the ideal operation of the high-voltage output amplifier can be substantially maintained.

Fig. 6 shows a response waveform of a sine wave input with a frequency of 10Hz and a capacitor C151 of 1000 pF. Here, the voltage V between the two terminals of the capacitor C151 can be seen_C151There was a slight variation, but the gate voltage waveform V in the Nch MOS FETQ101_Q101-GGate voltage waveform V of Nch MOS FETQ201_Q201-GNo anomaly was seen in each. This shows that the ideal operation of the high-voltage output amplifier can be substantially maintained.

Fig. 7 shows a response waveform of a sine wave input with a frequency of 100Hz and a capacitor C151 of 0.01 pF. Here, the voltage V between the two terminals of the capacitor C151 can be seen_C151Although there was a slight variation, it was found that the gate voltage V of the Nch MOS FETQ101_Q101GAnd gate voltage V of Nch MOS FETQ201_Q201GFrom the output voltage V of the phase_OUTHas some deviation from the beginning.

Fig. 8 shows a response waveform of a sine wave input with a frequency of 100Hz and a capacitor C151 of 1000 pF. Here, the voltage V between the two terminals of the capacitor C151 can be seen_C151Slightly larger. This indicates that there is a movement of charge between the gate of Nch MOS fet q101 and the gate of Nch MOS fet q201 after passing through capacitor C151. If the capacitance value of the capacitor C151 is increased, the variation becomes small. Here, even if the frequency of 100Hz input, Nch MOS FETQ101 grid voltage V_Q101GGate voltage V with Nch MOS fet q201_Q201GAnd also the output voltage V_OUTAre substantially identical.

Fig. 9 shows a response waveform of a sine wave input with a frequency of 1000Hz and a capacitor C151 of 0.01 pF. Here, the voltage V between the two terminals of the capacitor C151 can be seen_C151There is a large variation. This is because, since the capacitance value of the capacitor C151 is 0.01pF (substantially the same as the capacitor C151 not mounted), electric charge is input to the gate between the gate of the Nch MOS fet q101 and the gate of the Nch mosfet q201The movement (charge/discharge) of the capacitor cannot be smoothly performed. Further, it is known that the gate voltage V of the Nch MOS FETQ101 is inputted at a frequency of 1000Hz_Q101GAnd gate voltage V of Nch MOS FETQ201_Q201GFrom the output voltage V_OUTHas a large deviation from the phase.

Fig. 10 shows a response waveform of a sine wave input with a frequency of 1000Hz and a capacitor C151 of 1000 pF. Here, the voltage V between the two terminals of the capacitor C151 can be seen_C151Although there is a slight variation, the variation width is significantly reduced as compared with the case where the capacitor C151 is 0.01 pF. Further, at a frequency of 1000Hz, the gate voltage V of the Nch MOS FETQ101 is also known_Q101GGate voltage V with Nch MOS fet q201_Q201GPhase and output voltage V_OUTAre substantially identical.

Next, the gate current I to the Nch MOS FETQ101_Q101GAnd gate current I of Nch MOS FETQ201_Q201GThe description is given. FIGS. 11 and 12 show the gate current I of the Nch MOS FETQ101 of the high-voltage output amplifier having the circuit configuration shown in FIG. 2_Q101GWaveform of (3) and gate current I of Nch MOS FETQ201_Q201GA graph of the waveform of (a), which shows the output voltage V at a sine wave input frequency of 1000Hz_OUTThe case of + -3000V. In addition, the gate current I_Q101G、I_Q201GIs a right scale, and outputs a voltage V_OUTIs the left scale.

Fig. 11 shows a case where the capacitor C151 is 0.1 pF. Here, the gate current I for Nch MOS fet q101_Q101GThe gate current I is high impedance as high as 1500k Ω because the value of (n) when the resistor R101 and R102 sides are viewed from the gate of the Nch MOS fet q101 of fig. 2_Q101GThe distortion of the current waveform of (2) is large. Further, since the value of the gate current IQ201G of the Nch MOS fet q201 viewed from the gate of the Nch MOS fet q201 toward the resistors R201 and R202 is high impedance, which is as high as 1500k Ω, the gate current I is taken_Q201GThe distortion of the current waveform of (2) is large. Also, the output voltage V_OUTThe waveform of (2) also shows no amplitude of ± 3000V of distortion.

Fig. 12 shows a capacitor C1511000 pF. Here, the gate current I for Nch mosfet q101_Q101GAnd gate current I of Nch MOS FETQ201_Q201GThe direction of the current flowing into the gate electrode is positive. Gate current I of Nch MOS FETQ101_Q101GSpecific output voltage V_OUTLeading the phase by 90 degrees, but this is normal, the gate current I of Nch MOS FETQ201_Q201GSpecific output voltage V_OUTLagging the phase by 90 degrees, but this is normal. In addition, the gate current I of the Nch MOS FETQ101_Q101GAnd gate current I of Nch MOS FETQ201_Q201GHave the same amplitude and a phase difference of 180 degrees (inversion relationship).

Gate current I at Nch MOS FETQ101_Q101GFor positive half-cycles (charging charge to the input capacitance of the gate), the gate current I of Nch MOS FETQ201_Q201GIn the negative half-cycle (the charge is discharged from the input capacitance of the gate). Gate current I at Nch MOS FETQ101_Q101GIn the negative half cycle, the flow of current (movement of charge) is reversed. This means that the electric charge moves between the gate of Nch MOS fet q101 and the gate of Nch MOS fet q201 after passing through the capacitor C151.

Gate current I at Nch MOS FETQ101_Q101GAnd gate current I of Nch MOS FETQ201_Q201GWhen crossing and becoming 0, the output voltage V_OUTThe value (absolute value) of (c) reaches the maximum. That is, at the time point when the movement of the electric charges between the gates of the Nch MOS fet q101 and Nch MOS fet q201 is completed, the output voltage V is output_OUTBecomes maximum in absolute value. When the operation is performed so that the current of the Nch MOS fet q101 increases, charge is charged (the current is positive) to the input capacitance of the gate of the Nch MOS fet q 101. At this time, Nch MOS fet q201 operates to reduce the current, and therefore operates to discharge the charge to the input capacitance of Nch MOS fet q201 (the current is negative). The capacitor C151 connected between the gate of the Nch MOS fet q101 and the gate of the Nch MOS fet q201 functions as a channel for accommodating electric charges, and the symbiotic relationship between the Nch MOS fet q101 and the Nch MOS fet q201 is established.

FIG. 13 shows a modification of the high-voltage output amplifier according to the present inventionA diagram of an example of a circuit configuration of an output high-voltage amplifier. In this figure, the same reference numerals as those in fig. 2 denote the same components. The same applies to fig. 14 to 18 described later. The circuit configuration of the positive output high voltage amplifier shown in fig. 13 is different from that of fig. 2 in that the voltage of the high voltage positive power supply + HVps of fig. 2 is changed to +6100V, and the high voltage negative power supply-HVps is changed to a low voltage negative power supply-V (-15V). In the high-voltage amplifier of fig. 2, the positive voltage, the negative voltage, and the output voltage V of the positive and negative voltages_OUTIs possible, in contrast to which in the high voltage output amplifier of fig. 13, only the positive output voltage V is present_OUT. The other circuit configurations, operations, and the like are substantially the same as those of the circuit of fig. 2, and therefore, the description thereof is omitted.

Fig. 14 is a diagram showing an example of the circuit configuration of a negative output high-voltage amplifier according to a modification of the high-voltage output amplifier according to the present invention. The circuit configuration of the negative output high voltage amplifier shown in fig. 14 is different from that of fig. 2 in that the high voltage positive power supply + HVps of fig. 2 is changed to a low voltage positive power supply + V (+15V), the high voltage negative power supply-HVps is changed to-6100V, and the output voltage V is set to_OUTOnly negative. The other circuit configurations, operations, and the like are substantially the same as those of the circuit of fig. 2, and therefore, the description thereof is omitted.

Fig. 15 shows a modification of the high-voltage output amplifier according to the present invention. The circuit configuration of the high-voltage output amplifier shown in fig. 15 is different from that of fig. 2 in that Nch MOS FETs on the positive side and the negative side are three-stage configured. That is, Nch MOS fet q101, Nch MOS fet q102, and Nch MOS fet q103 are arranged on the positive side, and Nch mosfet q201, Nch MOS fet q202, and Nch MOS fet q203 are arranged on the negative side. Further, the source of the positive Nch MOS fet q101 and the drain of the Nch MOS fet q102 are connected, the source of the Nch MOS fet q102 and the drain of the Nch MOS fet q103 are connected, the source of the negative Nch MOS fet q201 and the drain of the Nch MOS fet q202 are connected, and the source of the Nch MOS fet q202 and the drain of the Nch MOS fet q203 are connected.

Further, a resistor R103 is connected between the gate of the Nch MOS fet q102 and the gate of the Nch MOS fet q103 on the positive side, the source of the Nch MOS fet q103 is connected to one end of a resistor R105 through a resistor R104, the other end of the resistor R105 is connected to the output line lout, and the resistor R105 is connected to both output ends of the photocoupler U101. Further, the cathode terminal of the zener diode D103, one terminal of the capacitor C101, and the gate of the Nch MOS fet q103 are connected, and the other terminal of the resistor R105, the anode terminal of the zener diode D103, and the other terminal of the capacitor C101 are connected to the output line lout.

Further, a resistor R203 is connected between the gate of the Nch MOS fet q202 and the gate of the Nch MOS fet q203 on the negative side, the source of the Nch MOS fet q203 is connected to one end of a resistor R205 via a resistor R204, and the resistor R205 is connected to both output ends of the photocoupler U201. Further, the cathode of the zener diode D203 and one end of the capacitor C201 are connected to the gate of the Nch MOS fet q203, and the other end of the resistor R205, the anode of the zener diode D203, and the other end of the capacitor C201 are connected to the high-voltage negative power supply-HVps via a resistor R206 for simulation (for example, 1 Ω).

A series circuit of a capacitor C151 and a resistor R151 is connected between the gate of the Nch MOS fet Q102 on the positive side and the gate of the Nch MOS fet Q201 (not Q202) on the negative side, and a series circuit of a capacitor C152 and a resistor R152 is connected between the gate of the Nch MOS fet Q101 on the positive side and the gate of the Nch MOS fet Q202 (not Q201) on the negative side. Thus, the capacitor C151 connected between the gate of the Nch MOS fet Q102 and the gate of the Nch MOS fet Q201 and the capacitor C152 connected between the gate of the Nch MOS fet Q101 and the gate of the Nch MOS fet Q202 function as a channel for accommodating electric charges, and the symbiotic relationship between the Nch MOS fet Q102 and Q201 and between the Nch MOS fet Q101 and Q202 is established. Further, the voltage of the high voltage positive power supply + HVps of fig. 2 is changed to +5300V, and the voltage of the high voltage negative power supply-HVps is changed to-5300V. With the above configuration, a high-voltage output amplifier with a higher voltage can be realized. Further, by setting the number of stages of the Nch MOS FET to four or more stages, a high-voltage output amplifier can be further realized.

For example, when the Nch MOS FETs are set to five stages, and the Nch MOS FETs Q101, Q102, Q103, Q104, and Q105 are arranged on the positive side, and the Nch MOS FETs Q201, Q202, Q203, Q204, and Q205 are arranged on the negative side, the Nch MOS FETs Q204, Q203, Q202, and Q201 are arranged on the negative side with respect to the gates of the Nch MOS FETs Q101, Q102, Q103, and Q104 in correspondence with fig. 15, and a series circuit of a capacitor C and a resistor R is connected between the gates, thereby realizing a super high voltage output amplifier.

Fig. 16 shows a modification of the high-voltage output amplifier according to the present invention. The circuit configuration of the high-voltage amplifier shown in fig. 16 is different from that shown in fig. 2 in that Nch MOS FETs on the positive side and the negative side are configured in one stage, that is, one Nch MOS FET q102 is provided on the positive side and one Nch MOS FET q202 is provided on the negative side. And, the voltage of the high voltage positive power supply + HVps of fig. 2 is changed to +1600V, and the voltage of the high voltage negative power supply-HVps is changed to-1600V.

The drain of Nch MOS fet q102 is connected to the high-voltage positive power supply + HVps via a resistor R104 for simulation, and a resistor R101 is connected between the drain and the gate of Nch MOS fet q 102. The source of the Nch MOS fet q102 is connected to one end of a resistor R103 (e.g., 7.5k Ω) via a resistor R102 (e.g., 100 Ω), and the resistor R103 is connected to both ends of the output of the photocoupler U101. The cathode of the zener diode D101 is connected to one end of the capacitor C101, and the anode of the zener diode D101, the other end of the capacitor C101, and the other end of the resistor R103 are connected to the output line lout.

The source of the Nch MOS fet q202 is connected to one end of a resistor R203 (e.g., 7.5k Ω) via a resistor R202 (e.g., 100 Ω), and the resistor R203 is connected to the output terminal of the photocoupler U201. The gate of the Nch MOS fet q202 is connected to the output line lout via the resistor R201, and the cathode of the zener diode D201 and one end of the capacitor C201 are connected to the gate of the Nch MOS fet q 202. The anode terminal of the zener diode D201, the other terminal of the capacitor C201, and the other terminal of the resistor R203 are connected to the negative high voltage power supply-HVps through a resistor R204 for simulation.

Fig. 17 shows a modification of the high-voltage output amplifier according to the present invention. The circuit configuration of the high-voltage output amplifier shown in fig. 17 differs from that shown in fig. 2 in that three positive photo couplers U101, U102, and U103 are used as positive photo couplers, and three negative photo couplers U201, U202, and U203 are used as negative photo couplers, in order to increase the output currents on the positive and negative sides. The output of the operational amplifier U1 is serially input to the light emitting diodes on the light emitting side of the photo couplers U103 and U102 on the positive side through a resistor R5 (e.g., 470 Ω), and is input to the light emitting diodes on the light emitting side of the photo coupler U101 through a resistor R10 (e.g., 100 Ω). Further, the output of the operational amplifier U1 is serially input to the light emitting diodes on the light emitting side of the negative side photocouplers U203, U202 through a resistor R6 (e.g., 470 Ω), and is input to the light emitting diode on the light emitting side of the photocoupler U201 through a resistor R11.

Collector currents of the photo transistors on the light receiving sides of the positive photo couplers U101, U102, and U103 are merged and introduced into the resistor R104, and collector currents of the photo transistors on the negative side are merged and introduced into the resistor R204. This can increase the output current on the positive side and the negative side. It is to be understood that the number of photocouplers is not limited to this.

Fig. 18 shows a modification of the high-voltage output amplifier according to the present invention. The circuit configuration of the high-voltage output amplifier shown in fig. 18 is different from that shown in fig. 2 in that two amplification circuits of Nch MOS FETs each including an output stage of the photocoupler shown in fig. 2 are provided on the positive side and the negative side, respectively, in order to increase the output currents on the positive side and the negative side. That is, the amplification circuit MP1 including the photocoupler U101, Nch MOS fet q101, and Nch MOS fet q102, the amplification circuit MP2 including the photocoupler U301, Nch MOS fet q301, and Nch MOS fet q302, and the amplification circuit MN1 including the photocoupler U201, Nch MOS fet q201, and Nch MOS fet q202, and the amplification circuit MN2 including the photocoupler U401, Nch MOS fet q401, and Nch MOS fet q402 are arranged in parallel on the positive side.

The output of the operational amplifier U1 of the input stage is input to the light emitting diodes of the positive photo couplers U101 and U301 through the resistor R107 (e.g., 470 Ω) and the resistor R307 (e.g., 470 Ω), and is input to the light emitting diodes of the negative photo couplers U201 and U401 through the resistor R207 (e.g., 470 Ω) and the resistor R407 (e.g., 470 Ω). Collector currents of the photo-transistors on the light receiving sides of the photo-couplers U101 and U301 are introduced into the resistor R104 and the resistor R304, respectively, and current control is performed on the sources of the Nch mosfet q102 of the amplification circuit MP1 and the Nch MOS fet q302 of the amplification circuit MP2 through the resistor R103 and the resistor R303, respectively. Similarly, collector currents of the photo-transistors on the light receiving sides of the photo-couplers U201 and U401 pass through the resistor R204 and the resistor R404, respectively, and current control is performed on the sources of the Nch MOS fet q202 of the amplification circuit MN1 and the Nch MOS fet q402 of the amplification circuit MN 2.

The outputs of the positive side amplifier circuit MP1 and the negative side amplifier circuit MN1 are supplied to the load L from the output line lout via the analog resistor R152. The outputs of the positive amplifier circuit MP2 and the negative amplifier circuit MN2 are supplied to the load L from the output line lout via the analog resistor R352. In this way, by providing the high-voltage output amplifier having a configuration in which two high-voltage output amplifiers are disposed on the positive side and the negative side, respectively, which is substantially the same as the circuit configuration shown in fig. 2, the output current can be increased, and the loss can be dispersed, so that the heat dissipation process can be facilitated.

This can increase the output current on the positive side and the negative side. The circuit including the Nch MOS FETs of the positive and negative output stages is not limited to two circuits, and may be of two or more stages. This can further disperse the loss, and facilitate heat dissipation.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the technical ideas described in the claims, the description, and the drawings.