阅读说明：本技术 具有驱动电路的降压-升压转换器供电电源 (Buck-boost converter power supply with drive circuit ) 是由 高保成 于 2016-08-01 设计创作，主要内容包括：供电电源(50)包括第一供电输入节点(38)和第二供电输入节点(40)、供电输出节点(42)、第一和第二开关电路(24、28)、滤波器电路(32)以及驱动电路(54)。第一和第二供电输入节点分别配置接收第一和第二输入电压,供电输出节点配置提供输出电压。第一开关电路(24)具有耦合第一供电输入节点的第一导电节点、第二导电节点和配置接收第一控制信号(S1)的控制节点。滤波器电路具有耦合第二导电节点的第一节点(60)且具有第二节点。第二开关电路(28)具有耦合滤波器电路第二节点的第一导电节点、耦合第二供电输入节点的第二导电节点和控制节点。驱动电路具有耦合第一开关电路的控制节点和滤波器电路的第一节点中的一个的输入节点(58),且具有耦合第二开关电路控制节点的输出节点(62)。(A power supply (50) includes first and second power supply input nodes (38, 40), a power supply output node (42), first and second switching circuits (24, 28), a filter circuit (32), and a drive circuit (54). The first and second supply input nodes are configured to receive first and second input voltages, respectively, and the supply output node is configured to provide an output voltage. The first switching circuit (24) has a first conductive node coupled to the first power supply input node, a second conductive node, and a control node configured to receive a first control signal (S1). The filter circuit has a first node (60) coupled to the second conductive node and has a second node. A second switching circuit (28) has a first conductive node coupled to the second node of the filter circuit, a second conductive node coupled to the second supply input node, and a control node. The drive circuit has an input node (58) coupled to one of the control node of the first switch circuit and the first node of the filter circuit, and has an output node (62) coupled to the control node of the second switch circuit.)

1. A power supply, comprising:

a first supply input node and a second supply input node configured to receive a first input voltage and a second input voltage, respectively;

a supply output node configured to provide an output voltage;

a first switching circuit having a first conductive node coupled to the first supply input node, a second conductive node, and a control node configured to receive a first control signal;

a filter circuit having a first node coupled to the second conductive node and having a second node;

a second switching circuit having a first conductive node coupled to the second node of the filter circuit, having a second conductive node coupled to the second supply input node, and having a control node; and

a drive circuit having an input node coupled to one of the control node of the first switch circuit and the first node of the filter circuit, and having an output node coupled to the control node of the second switch circuit.

2. The power supply of claim 1, wherein:

the first switching circuit includes a first transistor; and is

The second switching circuit includes a second transistor.

3. The power supply of claim 1 wherein said filter circuit comprises an inductor.

4. The power supply of claim 1 wherein said second input voltage is ground.

5. The power supply of claim 1, further comprising:

a third switch circuit having a first conductive node coupled to the first node of the filter circuit, a second conductive node coupled to the second power supply input node, and a control node configured to receive a second control signal; and is

Wherein the drive circuit has the output node coupled to one of the control node of the first switch circuit, the first node of the filter circuit, and the control node of the third switch circuit.

6. The power supply of claim 1 further comprising a diode having an anode coupled to the second node of the filter circuit and having a cathode coupled to the power supply output node.

7. The power supply of claim 1, further comprising a capacitor coupled between the power supply output node and the second power supply input node.

8. The power supply of claim 1 further comprising a controller having a first controller output node coupled to the control node of the first switching circuit and configured to generate the first control signal on the first controller output node.

9. The power supply of claim 1, further comprising:

a controller having a first controller output node coupled to the control node of the first switch, having a feedback node and configured to generate the first control signal on the first controller output node; and

a feedback circuit having an input node coupled to the supply output node and having an output node coupled to the feedback node of the controller.

10. The power supply of claim 1, wherein the drive circuit is configured to cause the second switch circuit to be on when the first switch circuit is on and off when the first switch circuit is off during a boost mode, and to cause the second switch circuit to be on during a buck mode.

11. The power supply of claim 1, further comprising:

a third switch circuit having a first conductive node coupled to the first node of the filter circuit, a second conductive node coupled to the second power supply input node, and a control node configured to receive a second control signal; and is

Wherein the drive circuit comprises

The input node coupled to the first node of the filter circuit,

an NMOS transistor having a drain node coupled to the input node, having a source node coupled to the output node, and having a control node,

a voltage limiter circuit having a first node coupled to the control node of the NMOS transistor and having a second node coupled to the second power supply input node,

a fourth switching circuit coupled across the voltage limiter and having a control node,

an impedance circuit having a first node coupled to the first supply input node and having an output node coupled to the control node of the NMOS transistor, an

A comparator circuit having a first input node coupled to the first supply input node, a second input node coupled to the supply output node, and an output node coupled to the control node of the fourth switching circuit.

12. The power supply of claim 11 further comprising a controller having a first controller output node coupled to the control node of the first switch circuit, having a second controller output node coupled to the control node of the third switch and configured to generate the first and second control signals on the first and second controller output nodes, respectively.

13. The power supply of claim 1, further comprising:

a third switch circuit having a first conductive node coupled to the first node of the filter circuit, a second conductive node coupled to the second power supply input node, and a control node configured to receive a second control signal; and is

Wherein the drive circuit comprises

The input node coupled to the first node of the filter circuit,

an NMOS transistor having a drain node coupled to the input node, having a source node coupled to the output node, and having a substrate node coupled to the source node,

a zener diode having a cathode coupled to the control node of the NMOS transistor and having an anode coupled to the second power supply input node,

a fourth switching circuit coupled across the zener diode and having a control node,

an impedance circuit having a first node coupled to the first supply input node and having an output node coupled to the control node of the NMOS transistor, an

A comparator circuit having a first input node coupled to the first supply input node, a second input node coupled to the supply output node, and an output node coupled to the control node of the fourth switch circuit, the comparator circuit configured to cause the first switch circuit to couple the control node of the NMOS transistor to the second supply input node in response to the first input voltage being greater than the output voltage.

14. The power supply of claim 13 further comprising a controller having a first controller output node coupled to the control node of the first switch circuit, having a second controller output node coupled to the control node of the third switch and configured to generate the first and second control signals on the first and second controller output nodes, respectively.

15. The power supply of claim 1, further comprising:

a third switch circuit having a first conductive node coupled to the first node of the filter circuit, a second conductive node coupled to the second power supply input node, and a control node configured to receive a second control signal; and is

Wherein the drive circuit comprises

The input node coupled to the control node of the first switching circuit,

an inverter having an input node coupled to the input node of the driver circuit and having an output node coupled to the output node of the driver circuit,

a fourth switching circuit coupled between the output node of the drive circuit and the control node of the second switching circuit,

an impedance circuit having a first node coupled to the control node of the second switching circuit and a second node coupled to the second supply input node, an

A comparator circuit having a first input node coupled to the first supply input node, a second input node coupled to the supply output node, and an output node coupled to the control node of the fourth switching circuit, the comparator circuit configured to cause the fourth switching circuit to couple the output node of the drive circuit to the control node of the second switching circuit in response to the first input voltage being less than the output voltage.

16. A system, comprising:

a power supply source comprising

A first supply input node and a second supply input node configured to receive a first input voltage and a second input voltage, respectively;

a supply output node configured to provide an output voltage;

a first switching circuit having a first conductive node coupled to the first supply input node, a second conductive node, and a control node configured to receive a first control signal;

a filter circuit having a first node coupled to the second conductive node and having a second node;

a second switching circuit having a first conductive node coupled to the second node of the filter circuit, having a second conductive node coupled to the second supply input node, and having a control node; and

a drive circuit having an input node coupled to one of the control node of the first switch circuit and the first node of the filter circuit, and having an output node coupled to the control node of the second switch circuit; and

a load coupled to the supply output node.

17. The system of claim 16, wherein the power supply comprises a buck-boost converter.

18. The power supply of claim 16, further comprising:

a third switch circuit having a first conductive node coupled to the first node of the filter circuit, a second conductive node coupled to the second power supply input node, and a control node configured to receive a second control signal;

a controller configured to generate the first control signal and the second control signal; and is

Wherein the drive circuit has the input node coupled to one of the first node of the filter circuit and the control node of the third switch circuit.

19. The system of claim 16, wherein the load comprises a processor circuit.

20. A method, comprising:

driving a first node and a second node of a power supply source having a high-side switching circuit and a first low-side switching circuit, respectively, during a current increase portion of a boost mode; and

drive the first low side switching circuit in response to a signal at the first node of the power supply.

21. The method of claim 20, further comprising driving the first node of the power supply source with a second low side switching circuit during a current reduction portion of the boost mode.

22. The method of claim 21, further comprising:

generating a first control signal and a second control signal by using a power supply controller;

driving the high side switching circuit in response to the first control signal; and

driving the second low side switching circuit in response to the second control signal.

23. The method of claim 20, further comprising deactivating the first low-side switching circuit during a buck mode.

24. A method, comprising:

driving a first node and a second node of a power supply source having a high-side switching circuit and a first low-side switching circuit, respectively, during a current increase portion of a boost mode; and

the high side switching circuit and the first low side switching circuit are driven in response to the same control signal from a power supply controller integrated circuit.

25. The method of claim 24, further comprising driving the first node of the supply power supply with a second low-side switching circuit during a current reduction portion of the boost mode.

26. The method of claim 25, further comprising:

generating a first control signal and a second control signal by using a power supply controller;

driving the high side switch circuit and the first low side switch circuit in response to the first control signal; and

driving the second low side switching circuit in response to the second control signal.

27. The method of claim 24, further comprising deactivating the first low-side switching circuit during a buck mode.

28. A method, comprising:

driving a first node and a second node of a power supply source having a high-side switching circuit and a first low-side switching circuit, respectively, during a current increase portion of a boost mode;

driving the first node of the power supply source with a second low side switching circuit during a current reduction portion of the boost mode;

driving the high side switch in response to a first control signal; and

driving the first low side switching circuit and the second low side switching circuit in response to a second control signal from a power supply controller integrated circuit.

29. The method of claim 28, further comprising generating the first control signal and the second control signal with a power supply controller.

30. The method of claim 28, further comprising deactivating the first low-side switching circuit during a buck mode.

Disclosure of Invention

In an embodiment, a power supply includes first and second power supply input nodes, a power supply output node, first and second switching circuits, a filter circuit, and a drive circuit. The first and second supply input nodes are configured to receive first and second input voltages, respectively, and the supply output node is configured to provide an output voltage. The first switch circuit has a first conductive node coupled to the first supply input node, a second conductive node, and a control node configured to receive a first control signal, and the filter circuit has a first node coupled to the second conductive node and has a second node. The second switching circuit has a first conductive node coupled to the second node of the filter circuit, a second conductive node coupled to the second supply input node, and a control node. And the drive circuit has an input node coupled to one of the control node of the first switch circuit and the first node of the filter circuit, and has an output node coupled to the control node of the second switch circuit.

In embodiments, such power supplies may operate in a buck mode even if there is a power supply controller with only two switching circuit control output nodes per power supply. Such power supplies may therefore include simpler and less expensive power supply controllers than many previous buck-boost power supplies. Such power supplies therefore allow power supply designers to choose from a greater variety of power supply controllers because there are more controllers on the market with two switching control output nodes per phase than there are controllers with more than two (e.g., four) switching circuit control output nodes per phase.

Drawings

Fig. 1 is a diagram of a buck-boost converter power supply and a load powered by the power supply.

Fig. 2 is a timing diagram of control signals of the switching circuit of fig. 1.

Fig. 3 is a diagram of a buck-boost converter power supply according to an embodiment.

Fig. 4 is a timing diagram of control signals of the switching circuit of fig. 3 according to an embodiment.

FIG. 5 is a diagram of a buck-boost converter power supply according to another embodiment.

Fig. 6 is a diagram of a buck-boost converter power supply according to yet another embodiment.

Fig. 7 is a diagram of a system incorporating at least one of the power supplies of fig. 3, 5, and 6, according to an embodiment.

Detailed Description

Fig. 1 is a diagram of a power supply, here a buck-boost converter power supply 10, and a load 12 powered by the power supply. As described below, a problem with the power supply 10 is the use of a power supply controller Integrated Circuit (IC)14 having four switching circuit control output nodes 16, 18, 20 and 22. Thus, the controller IC 14 is generally less expensive and less demanding than a controller having less than four (e.g., two) switching circuits controlling the output nodes.

In addition to controller IC 14, buck-boost converter power supply 10 includes a switching circuit (here, transistors 24, 26, 28, and 30), a filter circuit (here, phase inductor 32), an output filter capacitor 34, a feedback circuit 36 configured to receive a first input supply voltage V_{Input device}A first supply input node 38 (e.g., from a battery or from another supply source), a second supply input node 40 configured to receive a second input supply voltage (here ground), and configured to provide a regulated output voltage V_{Output of}To the supply output node 42. The power supply 10 may include other components that have been omitted from fig. 1 for the sake of brevity.

The supply power controller IC 14 includes an error amplifier 44 and a switch control circuit 46, and is configured to generate a reference signal (here not shown) using, for example, a conventional bandgap voltage reference circuit (not shown in FIG. 1)Is a reference voltage V_{Reference to}). Error amplifier 44 is configured to compare the feedback signal (here, feedback voltage FB from feedback circuit 36) with V_{Reference to}And generates an ERROR signal (here, an ERROR voltage) ERROR in response to the comparison. The switch control circuit 46 is configured to generate switch signals S1-S4 in response to the signal ERROR, and these switch signals control the conductive state, conductive (e.g., "on") and non-conductive (e.g., "off") of the transistors 24-30, respectively. For example, if FB is less than V_{Reference to}Then, in response to the resulting signal ERROR, the switch control circuit 46 is configured to generate the switch signals S1-S4 such that the average current I through the inductor 32_LIncrease, and thus make V_{Output of}Increasing toward regulated values (e.g., 1.1 volts (V), 1.3V, 3.3V, 5V, and 12V), the power supply 10 is configured to target V_{Output of}An adjustment value is generated. In contrast, if FB is greater than V_{Reference to}Then, in response to the resulting signal ERROR, the switch control circuit 46 is configured to generate the switch signals S1-S4 such that the average current I through the inductor 32_LReduce, and thus make V_{Output of}Decreasing towards its adjusted value. The circuit topology of the error amplifier 44 and the switch control circuit 46 may be conventional; therefore, for simplicity, these topologies are omitted from fig. 1 and are not described in detail. For example, error amplifier 44 may include a frequency compensation circuit. And although not shown in fig. 1, controller IC 14 may include a comparator configured to compare V_{Input device}And V_{Output of}Such that the controller IC can determine whether it is in buck mode (e.g., when V is_{Input device}>V_{Output of}When) or in boost mode (e.g., when V_{Input device}<V_{Output of}Time) to operate the power supply 10.

Transistors 24 through 30 are respective NMO switch transistors, although one or more of these NMOs transistors (e.g., one or both of transistors 24 and 30) may be replaced with respective PMOS transistors. Transistors 24 and 30 may be referred to as a first high-side transistor and a second high-side transistor, respectively; likewise, transistors 26 and 28 may be referred to as a first low side transistor and a second low side transistor, respectively.

And feedback circuit 36 will be V_{Output of}Converted into a feedback signal (here feedback voltage FB). For example, feedback circuit 36 may include generating FB ═ k · V_{Output of}Of a conventional resistor voltage driver, wherein k<1 and is set by the value of the resistor forming the voltage driver.

During operation of buck-boost converter power supply 10, power supply controller IC 14 first determines whether V is_{Input device}>V_{Output of}。

If controller IC 14 determines V_{Input device}>V_{Output of}Then the controller IC causes the power supply 10 to operate in the buck mode.

When operating in the buck mode, the switch control circuit 46 generates the switch control signal S3 having a low level so that the transistor 28 is always off, and generates the switch control signal S4 having a high level so that the transistor 30 is always on.

And the switch control circuit 46 generates signals S1 and S2 to switch the transistors 24 and 26 at a duty cycle that will be V_{Output of}Is adjusted to from V_{Reference to}And the value set by feedback circuit 36.

However, if the controller IC 14 determines V_{Input device}<V_{Output of}Then the controller IC causes the power supply 10 to operate in the boost mode.

Fig. 2 is a graph of switch control signals S1-S4 when the buck-boost converter power supply 10 of fig. 1 is operating in a boost mode.

With reference to fig. 1 to 2, the operation of the buck-boost converter power supply 10 in the boost mode is described.

During a first part T of the boost mode period_{Charging of electricity}Meanwhile, the switch control circuit 46 generates signals S1 and S3 having a logic high level so that the transistors 24 and 28 are turned on, and generates signals S2 and S4 having a logic low level so that the transistors 26 and 30 are turned off. Although FIG. 2 shows S1 and S3 as having the same logic high level, the actual voltage levels of S1 and S3 may differ because the source of transistor 24 is coupled to the phase node (input node of inductor 32) whose voltage (e.g., near V) is_{Input device}) Above the grounded source of transistor 28. Similarly, although FIG. 2 shows S2 and S4 as having the same logic low level, the actual voltage levels of S2 and S4 may differ because the source of transistor 30 is coupled to the output node of inductor 32, the voltage of which is (e.g., near V)_{Output of}) Above the grounded source of transistor 26.

Thus, at T_{Charging of electricity}Linearly increasing, i.e. during charging of the inductor, current I_LFrom V_{Input device}Through transistor 24, inductor 32 and transistor 28 to ground.

During a second part T of the boost mode period_{Discharge of electricity}Meanwhile, the switch control circuit 46 generates signals S1 and S3 having a logic low level so that the transistors 24 and 28 are turned off, and generates signals S2 and S4 having a logic high level so that the transistors 26 and 30 are turned on. Although fig. 2 shows S1 and S3 as having the same logic low level, the actual voltage levels of S1 and S3 may differ because the source of transistor 24 is coupled to a phase node that has a voltage (e.g., one transistor rds voltage drop near below ground) that is lower than the grounded source of transistor 28. Similarly, although FIG. 2 shows S2 and S4 as having the same logic high level, the actual voltage levels of S2 and S4 may differ because the source of transistor 30 is coupled to the output node of inductor 32, the voltage of which is (e.g., near V)_{Output of}) Above the grounded source of transistor 26.

Thus, at T_{Discharge of electricity}Linearly decreasing, i.e. current I during discharge of the inductor_LFrom ground through transistor 26, inductor 32 and transistor 30 to V_{Output of}。

Thus, controller 14 is configured to control the duty cycle of transistors 24 and 28 during boost modeTo adjust V_{Output of}。

Referring again to FIG. 1, if V_{Input device}～V_{Output of}But at V_{Output of}Within a threshold voltage of, the controller IC 14 may be configured to control the supply voltageElectric power source 10 to regulate V_{Output of}Alternating between a buck mode and a boost mode. The designer of power supply 10 may select the threshold voltage based on criteria such as, but not limited to, V_{Output of}And the expected steady state current flowing to load 12.

Referring again to fig. 1 and 2, alternative embodiments of the buck-boost converter power supply 10 are contemplated. For example, although the rising edges of S1 and S3 and the falling edges of S2 and S4, and the falling edges of S1 and S3 and the rising edges of S2 and S4 are described as occurring simultaneously, the switch control logic 46 may be configured to compensate two or more of these edges with respect to each other or with respect to other ones of the edges. Such compensation may impart operational characteristics to power supply 10 such as Zero Voltage Switching (ZVS), Zero Current Switching (ZCS), or blocking crowbar current flowing through transistors 24 and 26 and through transistors 28 and 30, respectively.

Still referring to fig. 1 and 2, as mentioned above, a problem with the buck-boost converter power supply 10 is that the controller IC 14 includes four switching circuit control output nodes 16, 18, 20 and 22 on which the controller IC generates the drive signals S1-S4, respectively. For example, because controller IC 14 includes four switching circuit control output nodes per power supply, controller IC may include more circuitry, consume more power, and be more expensive than a power supply controller IC having fewer than four switching circuit control output nodes per power supply. Furthermore, controller ICs 14 having fewer than four (e.g., two) switching circuit control output nodes per supply power supply tend to be more commercially available and, therefore, more readily available than controller ICs having four or more switching circuit control output nodes per supply power supply.

The solution to this problem is to replace each of transistors 26 and 30 with a separate diode and controller IC 14 with a controller IC having only two switching circuit drive nodes per supply power supply.

But this solution has problems. For example, replacing transistors 26 and 30 with separate diodes may reduce the conversion efficiency of power supply 10 because the voltage across the conducting diodes is typically significantly higher than the voltage across the conducting/on switching transistors. Furthermore, if the replacement controller IC 14 is configured to operate the power supply only in the buck mode, the controller IC will not be able to generate the signal S3, and therefore will not be able to drive the transistor 28 properly.

Fig. 3 is a diagram of a buck-boost converter power supply 50 in accordance with an embodiment, where components common to power supply 10 (fig. 1) and power supply 50 are identified with like reference numerals. The power supply 50 is similar to the power supply 10 of fig. 1, except that the power supply 50 includes four switching circuit control output controller ICs 14 and transistors 30, the power supply 50 also includes two switching circuit control output controller ICs 52, a drive circuit 54 configured to drive the transistors 28, and a diode 56. Thus, power supply 50 may include a cheaper and richer controller IC than power supply 10, while still retaining the ability to operate in boost mode, even though controller IC 52 is a buck mode controller.

Drive circuit 54 includes an input node 58 coupled to a phase node 60, and includes an output node 62 coupled to a control node (here, a gate) of transistor 28; that is, the driver circuit is configured to generate signal S3 for transistor 28. Alternatively, the driver circuit 54 may include one or both of the other input nodes 64 and 66, coupled to receive signals S1 and S2, respectively, from the controller IC 52, instead of or in addition to the input node 58.

During operation of buck-boost converter power supply 50, power supply controller IC 52 first determines whether V is_{Input device}>V_{Output of}。

If controller IC 52 determines V_{Input device}>V_{Output of}Then the controller IC causes the power supply 50 to operate in the buck mode.

When operating in the step-down mode, the drive circuit 54 generates the switching control signal S3 having a low level so that the transistor 28 is always turned off.

Also, controller IC 52 switches transistors 24 and 26 at a duty cycle (via signals S1 and S2, respectively) that will be V_{Output of}Is adjusted to from V_{Reference to}(not shown in fig. 3, but internally generated by controller IC 52) and the value set by feedback circuit 36.

However, if the controller IC 52 determines V_{Input device}<V_{Output of}Then the controller IC causes the power supply 50 to operate in the boost mode.

Fig. 4 is a plot of switch control signals S1-S3 when the buck-boost converter power supply 50 of fig. 3 is operating in a boost mode.

Referring to fig. 3 to 4, the operation of the buck-boost converter power supply 50 in the boost mode is described.

During a first part T of the boost mode period_{Charging of electricity}Meanwhile, the controller IC 52 and the drive circuit 54 generate signals S1 and S3 having a logic high level so that the transistors 24 and 28 are turned on, respectively, and the controller IC generates a signal S2 having a logic low level so that the transistor 26 is turned off. Although FIG. 4 shows S1, S2, and S3 as having the same logic high and logic low levels, the actual voltage levels of S1, S2, and S3 may differ because the source of transistor 24 is coupled to phase node 60, the voltage of which (e.g., near V)_{Input device}) Above the grounded sources of transistors 26 and 28.

Thus, at T_{Charging of electricity}Linearly increasing, i.e. during charging of the inductor, current I_LFrom V_{Input device}Through transistor 24, inductor 32 and transistor 28 to ground.

During a second part T of the boost mode period_{Discharge of electricity}Meanwhile, the controller IC 52 and the drive circuit 54 generate signals S1 and S3 having a logic low level so that the transistors 24 and 28 are turned off, respectively, and the controller IC generates a signal S2 having a logic high level so that the transistor 26 is turned on.

Thus, at T_{Discharge of electricity}Linearly decreasing, i.e. current I during discharge of the inductor_LFrom ground through transistor 26, inductor 32 and diode 56 to V_{Output of}。

Controller IC 52 is therefore configured to control the duty cycle of transistors 24 and 28 during the boost mode (i.e.,) To adjust V_{Output of}。

Referring again to FIG. 3, if V_{Input device}～V_{Output of}But at V_{Output of}Within the threshold voltage of V, then the controller IC 52 may control the power supply 50 to alternate between the buck mode and the boost mode to adjust V_{Output of}. The designer of the power supply 50 may select the threshold voltage based on criteria such as, but not limited to, V_{Output of}And the expected steady state load current flowing to the load powered by the power supply 50.

Referring again to fig. 3 and 4, alternative embodiments of the buck-boost converter power supply 50 are contemplated. For example, the alternative embodiments of the power supply 10 described above in connection with fig. 1 and 2 may be applied to the power supply 50. Further, the power supply 50 may include the transistor 30 in place of the diode 56 and the driving circuit 54 may be configured to generate the signal S4 for driving the transistor 30, or the power supply may include another driving circuit configured to generate the driving signal S4.

Fig. 5 is a diagram of a buck-boost converter power supply 50 including a detailed view of a driver circuit 54 in an embodiment including a single input node 58 coupled to a phase node 60. In addition, components common to fig. 3 and 5 are identified with like reference numerals.

In addition to the input node 58 and the output node 62, the driver circuit 54 includes a switching circuit (here, an NMOS transistor 70), a voltage limiting circuit (here, a zener diode 72), a switch 74, an impedance circuit (here, a resistor 76), and a comparator circuit 78.

The NMOS transistor 70 has a drain coupled to the drive circuit input node 58, a source coupled to the drive circuit output node 62, and a first supply node 38 (V) coupled via a resistor 76_{Input device}) Is controlled (here, the gate). The NMOS transistor 70 also has a substrate node coupled to its source such that the NMOS transistor includes a body diode 80 having an anode coupled to the source and a cathode coupled to the drain.

Zener diode 72 includes a cathode coupled to the gate of transistor 70 and an anode coupled to second power supply input node 40 (which is ground in the depicted embodiment).

A switching circuit 74, which may be an NMOS or PMOS transistor, is coupled across the zener diode 72.

Also, comparator circuit 78 includes a first power supply input node 38 coupled to receive V_{Input device}Coupled to the supply output node 42 to receive V_{Output of}And an output node coupled to a control node of switching circuit 74.

During the buck mode of operation, the power supply 50 operates as described above in connection with fig. 3 and 4.

Further, the drive circuit 54 operates as follows. Because during the buck mode V_{Input device}>V_{Output of}The comparator circuit 78 generates an output signal that turns off the switch circuit 76, pulling the gate of the NMOS transistor 70 to ground and turning off the NMOS transistor. Because NMOS transistor 70 is off, any charge on parasitic capacitance 82 between the gate of transistor 28 and ground discharges through body diode 805 to the phase node 60 when the phase node is low (i.e., when transistor 24 is off). And this charge flows from phase node 60 to ground through transistor 26 when transistor 26 is on, or from phase node 60 through inductor 32, diode 56 to power supply output node 42 when transistor 26 is off. Because there is no charge path to transistor 28, drive circuit 54 maintains the gate of transistor 28 at a low voltage level, and thus maintains transistor 28 in an off state during the buck mode.

During the boost mode of operation, the power supply 50 operates as described above in connection with fig. 3 and 4.

Further, the drive circuit 54 operates as follows. Because during boost mode V_{Input device}<V_{Output of}The comparator circuit 78 generates an output signal that turns on the switch circuit 76, thereby allowing the resistor 76 to pull up the gate of the NMOS transistor 70 to the voltage (V) across the zener diode 72_{Voltage stabilization}) To turn on NMOS transistor 70, zener diode 72 limits the gate voltage of NMOS transistor 28To make to V_{Voltage stabilization}To V_th70(V_th70Is the threshold voltage of NMOS transistor 70) such that V_{Input device}Does not damage the gate oxide of NMOS transistor 28, which is also present on phase node 60. Because NMOS transistor 70 is turned on, the voltage at the gate of transistor 28 is equal to or approximately equal to the voltage of phase node 60, causing signal S3 to follow signal S1 in accordance with the timing diagram of FIG. 4, and causing the state of transistor 28 to follow the state of transistor 24. When transistor 24 is turned on, the voltage at phase node 60, and therefore the voltage at the gate of transistor 28, is equal to or approximately equal to V_{Input device}So that transistor 28 is also turned on. And when transistor 24 is turned off, the voltage at phase node 60, and thus the voltage at the gate of transistor 28, is equal to or substantially equal to zero (or a diode drop below zero if transistor 26 is turned off so that its body diode conducts in diode emulation mode) so that transistor 28 is also turned off; parasitic capacitance 82 discharges via transistor 26 being turned on (or via inductor 32 if transistor 26 is turned off). The above cycle repeats so that in the boost mode, the state of transistor 28 is the same as the state of transistor 24.

Still referring to fig. 5, an alternative embodiment of the power supply 50 is contemplated. For example, the alternative embodiments described above in connection with fig. 3 and 4 may be applied to the embodiment of the power supply 50 described in connection with fig. 5. In addition, the power supply 50 may use the comparator circuit 78 to determine whether V_{Input device}>V_{Output of}And thus the power supply should operate in either the buck mode or the boost mode without using the comparator on the controller IC 52. Further, the comparator circuit 78 may be configured to include and implement hysteresis to avoid chattering.

Fig. 6 is a diagram of a buck-boost converter power supply 50 including a detailed view of a driver circuit 54 in accordance with another embodiment, in which the driver circuit includes a single input node 58 coupled to a control node (here, gate 90) of transistor 26. In addition, components common to fig. 3, 5 and 6 are identified with like reference numerals.

In addition to input node 58, output node 62, and comparator circuit 78, drive circuit 54 includes an inverter 92, a switching circuit 94, and a capacitive circuit (here, a resistor 96).

Inverter 92 includes PMOS transistor 98 and NMDS transistor 100. The PMOS transistor 98 includes a transistor coupled to the first supply input node 38 (V)_{Input device}) A source, a drain, a control node coupled to the input node 58, and a substrate node coupled to the source. And NMOS transistor 100 includes a source coupled to second power supply input node 40 (ground in the depicted embodiment), a drain coupled to the drain of PMOS transistor 98, a control node coupled to input node 58, and a substrate node coupled to the source.

The switch circuit 94, which may be an NMOS or PMOS transistor, is coupled between the drain of the transistor 98 and the output node 62 of the driver circuit 54.

A resistor 96 is coupled between the output node 62 and the second supply input node 40 (ground in the depicted embodiment).

Also, comparator circuit 78 includes a first power supply input node 38 coupled to receive V_{Input device}Coupled to the supply output node 42 to receive V_{Output of}And an output node coupled to a control node of switching circuit 94.

During the buck mode of operation, the power supply 50 operates as described above in connection with fig. 3 and 4.

Further, the drive circuit 54 operates as follows. Because during the buck mode V_{Input device}>V_{Output of}Comparator circuit 78 generates an output signal that turns on switching circuit 96, thereby disconnecting the gate of transistor 28 from inverter 92 and allowing resistor 96 to turn off transistor 28, and maintaining transistor 28 in the off state by pulling the gate of transistor 28 to ground.

During the boost mode of operation, the power supply 50 operates as described above in connection with fig. 3 and 4.

Further, the drive circuit 54 operates as follows. Because during boost mode V_{Input device}<V_{Output of}So that the comparator circuit 78 generates an output signal that closes the switching circuit 76 from which it is derivedAnd coupling the output of inverter 92 to the gate of transistor 28 causes the inverter to produceBecause of the fact thatS3 follows or substantially follows signal S1 in accordance with the timing diagram of fig. 4, such that the state of transistor 28 follows the state of transistor 24. The above cycle repeats so that in the boost mode, the state of transistor 28 follows the state of transistor 24.

Still referring to fig. 6, an alternative embodiment of the power supply 50 is contemplated. For example, the alternative embodiments described above in connection with fig. 3-5 may be applicable to the embodiment of the power supply 50 described in connection with fig. 6. Furthermore, it is contemplated that the source of switching transistor 98 may be connected to less than V_{Input device}May be generated by controller IC 52 or another voltage generator.

Fig. 7 is a block diagram of an embodiment of a computer system 110 incorporating one or more of the buck-boost converter power supplies 50 of fig. 3, 5, and 6 as a power supply 112, according to an embodiment. Although system 110 is described as a computer system, it may be any system suitable for implementation of power supply 112. Examples of such systems include, but are not limited to, battery chargers (e.g., USB compatible) that plug into a car outlet to charge a battery, such as a battery in a smart phone, car chargers, portable battery powered devices, televisions (e.g., for providing BUS power), video cameras with 24V AC power input and 32V DC power input, and low power (e.g., ≦ 36 Watts (W)).

The system 102 includes a computing circuit 114 that includes, in addition to the power supply 112, a processor circuit 116 (e.g., a microprocessor or microcontroller) powered by the power supply (i.e., the processor circuit is a load of the power supply), at least one input device 118, at least one output device 120, and at least one data storage device 122.

In addition to being configured to process data, the processor circuit 116 may also be configured to program, or otherwise control, the power supply 112. For example, the processor circuit 116 may be configured to perform one or more of the functions of a power supply controller IC (not shown in fig. 7) of the power supply 112.

An input device (e.g., keyboard, mouse) 118 is configured to allow data to be provided, programmed, and commands for the computing circuitry 114.

Output devices (e.g., displays, printers, speakers) 120 are configured to allow the computing circuitry 114 to provide data in a form that is perceptible by a human operator.

Furthermore, a data storage device (e.g., flash drive, hard drive, RAM, optical drive) 122 allows for storage of, for example, programs and data.

Still referring to fig. 7, although described as powering the processor circuit 116, the power supply 112 may be configured to provide power to one or more other components of the system 110 that are not, or are in addition to, the processor circuit. Further, one or more components of the power supply 112 (e.g., a power supply controller) may be placed on the integrated circuit chip as other components of the system 110 (e.g., the processor circuit 116); or components of power supply 112 and other components of system-on-chip 110 may be placed on different integrated circuit chips.

From the foregoing it will be appreciated that, although specific embodiments have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the disclosure. Further, where an alternative is disclosed for a particular embodiment, this alternative may also be applied to other embodiments, even if not specifically stated. Also, the components described above may be placed on a single or multiple IC chips to form one or more ICs, which may be coupled to one or more other ICs. Additionally, any of the described components or operations may be implemented/performed in hardware, software, firmware, or a combination of any two or more of hardware, software, and firmware. Moreover, one or more components of the apparatus or system may be omitted from the description for the sake of clarity or for another reason. Also, one or more components of the apparatus or system that have been included in the description may be omitted from the apparatus or system.