Logic-to-entity table updating method and storage controller
阅读说明:本技术 逻辑转实体表更新方法及存储控制器 (Logic-to-entity table updating method and storage controller ) 是由 廖世田 萧又华 于 2018-06-01 设计创作,主要内容包括:本发明提供一种逻辑转实体表更新方法及存储控制器。存储控制器包括处理器及快闪存储器存取电路。快闪存储器存取电路耦接到快闪存储器。逻辑转实体表更新方法包括:通过处理器传送写入指令到快闪存储器存取电路;通过快闪存储器存取电路执行写入指令来存取快闪存储器;以及在快闪存储器存取电路执行写入指令之后,通过快闪存储器存取电路更新随机存取存储器中的逻辑转实体表。(The invention provides a logic conversion entity table updating method and a storage controller. The memory controller includes a processor and a flash memory access circuit. The flash memory access circuit is coupled to the flash memory. The logic conversion entity table updating method comprises the following steps: transferring, by the processor, a write command to the flash memory access circuit; accessing the flash memory by the flash memory access circuit executing the write command; and updating the logic transition entity table in the random access memory through the flash memory access circuit after the flash memory access circuit executes the write command.)
1. A logic-to-entity table update method, adapted for a memory controller and a flash memory, the memory controller including a processor and a flash memory access circuit, the flash memory access circuit coupled to the flash memory, the logic-to-entity table update method comprising:
transferring, by the processor, a write instruction to the flash memory access circuit;
accessing the flash memory by the flash memory access circuitry executing the write instruction; and
after the flash memory access circuitry executes the write instruction, a table of logical transitionary entities in random access memory is updated by the flash memory access circuitry.
2. The logical transition entity table updating method of claim 1, wherein the processor finds the entity unit mapped by the logical unit through the logical transition entity table.
3. The logic transition entity table update method of claim 1, wherein the write command comprises a physical address, a data source, and an update address of the random access memory.
4. The logic transition entity table update method of claim 3, wherein the step of executing the write instruction by the flash memory access circuit comprises: writing data corresponding to the data source to the physical address of the flash memory by the flash memory access circuitry.
5. The logic transition table updating method according to claim 3, wherein the step of updating the logic transition table in the random access memory by the flash memory access circuit comprises: writing, by the flash memory access circuitry, the physical address to the update address of the random access memory.
6. The logic transition entity table update method of claim 1, wherein the random access memory is a Static Random Access Memory (SRAM) in the memory controller or a dynamic Random Access Memory (RAM) coupled to the memory controller.
7. A storage controller, comprising:
a processor; and
a flash memory access circuit coupled to the processor through a bus, wherein the flash memory access circuit is coupled to a flash memory, wherein
The processor transferring a write instruction to the flash memory access circuit;
the flash memory access circuit executes the write instruction to access the flash memory; and
after the flash memory access circuitry executes the write instruction, the flash memory access circuitry updates a table of logical transitionary entities in random access memory.
8. The storage controller of claim 7, wherein the processor looks up the entity unit mapped by the logical unit through the logical transition entity table.
9. The memory controller of claim 7, wherein the write command comprises a physical address, a data source, and an update address of the random access memory.
10. The memory controller of claim 9, wherein the flash memory access circuit writes data corresponding to the data source to the physical address of the flash memory.
11. The memory controller of claim 9, wherein the flash memory access circuit writes the physical address to the update address of the random access memory after the flash memory access circuit executes the write instruction.
12. The memory controller of claim 7, wherein the random access memory is a static random access memory in the memory controller or a dynamic random access memory coupled to the memory controller.
Technical Field
The present invention relates to a method for updating a logic to entity table and a memory controller, and more particularly, to a method for updating a logic to entity table and a memory controller capable of increasing instruction execution speed.
Background
Solid State Drive (SSD) is a storage device that is quite popular today. Generally, the solid state disk receives a command from a host system through a memory controller and accesses a flash memory (i.e., a rewritable nonvolatile memory module) according to the received command.
In the example of FIG. 1, the
The
Disclosure of Invention
In view of the above, the present invention provides a method for updating a logical-to-entity table and a storage controller, which efficiently updates the logical-to-entity table to increase the input/output operations per second of a system.
The invention provides a logic-to-entity table updating method which is suitable for a storage controller and a flash memory (flash). The memory controller includes a processor and a flash memory access circuit. The flash memory access circuit is coupled to the flash memory. The logic conversion entity table updating method comprises the following steps: transferring, by the processor, a write command to the flash memory access circuit; accessing the flash memory by the flash memory access circuit executing the write command; and updating the logic transition entity table in the random access memory through the flash memory access circuit after the flash memory access circuit executes the write command.
In an embodiment of the invention, the processor searches the entity unit mapped by the logic unit through the logic transition entity table.
In an embodiment of the invention, the write command includes a physical address, a data source, and an update address of the random access memory.
In an embodiment of the invention, the step of executing the write command by the flash memory access circuit includes: data corresponding to the data source is written to a physical address of the flash memory by the flash memory access circuit.
In an embodiment of the invention, the step of updating the logic transition table in the random access memory by the flash memory access circuit includes: the physical address is written to the update address of the random access memory by the flash memory access circuit.
In an embodiment of the invention, the Random Access Memory is a Static Random Access Memory (SRAM) in the Memory controller or a dynamic Random Access Memory coupled to the Memory controller.
The invention provides a memory controller, which comprises a processor and a flash memory access circuit. The flash memory access circuit is coupled to the processor by a bus. The flash memory access circuit is coupled to the flash memory. The processor transfers the write command to the flash memory access circuit. The flash memory access circuit executes a write command to access the flash memory. After the flash memory access circuit executes the write command, the flash memory access circuit updates the logical transition table in the random access memory.
In an embodiment of the invention, the processor searches the entity unit mapped by the logic unit through the logic transition entity table.
In an embodiment of the invention, the write command includes a physical address, a data source, and an update address of the random access memory.
In an embodiment of the invention, the flash memory access circuit writes data corresponding to the data source to a physical address of the flash memory.
In one embodiment of the present invention, after the flash memory access circuit executes the write command, the flash memory access circuit writes the physical address to the update address of the random access memory.
In an embodiment of the invention, the random access memory is a static random access memory in the memory controller or a dynamic random access memory coupled to the memory controller.
Based on the above, the method for updating a logic transition entity table and the memory controller according to the present invention update the logic transition entity table in the random access memory through the flash memory access circuit after the flash memory access circuit executes the write command. Therefore, the flash memory access circuit does not need to transmit an interrupt signal to the processor after the write instruction is executed, and then the processor executes the firmware to update the logic transition table in the random access memory. The instruction execution speed can thus be increased, thereby improving the input-output operations per second of the system.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a block diagram of a conventional memory device.
FIG. 2 is a block diagram of a memory device according to an embodiment of the invention.
FIG. 3 is a flowchart of a logic transition entity table updating method according to an embodiment of the present invention.
Fig. 4A and 4B are schematic diagrams of updating a logical transition entity table according to an embodiment of the invention.
Description of reference numerals:
10. 20: storage device
100. 200: storage controller
101. 102, 103, 201, 202, 203: signal line
110. 210: processor with a memory having a plurality of memory cells
120. 220, and (2) a step of: flash memory access circuit
130. 230: dynamic random access memory access circuit
140. 240: static random access memory
150. 250: interrupt control circuit
160. 260: bus line
170. 270: flash memory
180. 280: dynamic random access memory
221: logic to entity table updating circuit
S301, S303, S305: step of logic conversion entity table updating method
400: logic to entity table
Detailed Description
FIG. 2 is a block diagram of a memory device according to an embodiment of the invention.
Referring to fig. 2, the memory device 20 may include a
The storage device 20 is, for example, a usb disk, a memory card, a Solid State Drive (SSD), or other similar devices. The
The flash
For example, the
In addition, the data to be written into the rewritable nonvolatile memory module is converted into a format acceptable to the rewritable nonvolatile memory module by the flash
In the embodiment, the flash
The rewritable nonvolatile memory module of the
In the present embodiment, the memory cells of the rewritable nonvolatile memory module form a plurality of physical programming units, and the physical programming units form a plurality of physical blocks (also called as physical erasing units). Specifically, memory cells on the same word line (or same word line layer) constitute one or more physical program cells. If each memory cell is used to store more than 2 bits, the physical program cells on the same word line (or the same word line layer) can be classified into at least a lower physical program cell and an upper physical program cell.
In one embodiment, if each memory cell is used to store 2 bits, the physical program cells on the same word line (or the same word line layer) can be classified into a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program unit, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program unit. Generally, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell. In another embodiment, if each memory cell is used to store 3 bits, the physical program cells on the same word line (or the same word line layer) can be classified into a lower physical program cell, an upper physical program cell, and an additional (extra) physical program cell. For example, the least Significant Bit of a cell belongs to the lower physical program cell, the middle Significant Bit (CSB) of a cell belongs to the upper physical program cell, and the most Significant Bit of a cell belongs to the additional physical program cell.
In the present embodiment, data is used as a memory cell for writing data (program programming) in units of physical blocks. The physical blocks may also be referred to as physical erase cells or physical cells. The physical erase cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. Each physical block has a plurality of physical programming units. The physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., error correction codes).
However, the present invention is not limited thereto. For example, in another embodiment, the data transmission method described in this embodiment can also be applied to a rewritable nonvolatile memory module in which the physical programming unit is used as a unit for writing data.
The
In addition, the
In this embodiment, the flash
FIG. 3 is a flowchart of a logic transition entity table updating method according to an embodiment of the present invention.
Referring to fig. 3, in step S301, a write command is transmitted to the flash
Specifically, the write instruction may include an operation code (op code), a physical address, a data source, and an update address of the random access memory. The random access memory may be static random access memory 240 or dynamic
In step S303, the
In step S305, after the flash
Fig. 4A and 4B are schematic diagrams of updating a logical transition entity table according to an embodiment of the invention.
In FIG. 4A, the logical transition entity table 400 is recorded in an address field of the RAM, for example, an address field starting from 0x 4000. Each field of the logical-to-entity table 400 may be four bytes (bytes) to record the physical address corresponding to the logical unit. In the present embodiment, the logical units of the storage apparatus 20 are represented by Logical Block Addresses (LBAs), for example, the storage apparatus 20 includes logical units LBA (0), LBA (1), …, and LBA (n). Thus, address 0x4000 may correspond to LBA (0) and address 0x4000 records the physical address to which LBA (0) maps, address 0x4004 may correspond to LBA (1) and address 0x4004 records the physical address to which LBA (1) maps, and so on.
In FIG. 4B, assuming that the write command indicates that the data from LBA (7) is written to physical address A of the
In summary, the logic-to-entity table updating method and the memory controller according to the present invention update the logic-to-entity table in the random access memory through the logic-to-entity table updating circuit in the flash memory access circuit after the flash memory access circuit executes the write command. Therefore, the flash memory access circuit does not need to transmit an interrupt signal to the processor after the write instruction is executed, and then the processor executes the firmware to update the logic transition table in the random access memory. The instruction execution speed can thus be increased, thereby improving the input-output operations per second of the system.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
- 上一篇:一种医用注射器针头装配设备
- 下一篇:实体存储对照表产生装置及方法