Integrated circuit chip, integrated circuit and electronic device
阅读说明:本技术 集成电路芯片、集成电路及电子装置 (Integrated circuit chip, integrated circuit and electronic device ) 是由 吴良顺 于 2019-09-02 设计创作,主要内容包括:本发明公开一种集成电路芯片、集成电路及电子装置,所述集成电路芯片包括:目标逻辑单元、混淆逻辑单元、密钥单元和选择单元,其中:所述目标逻辑单元,用于接收输入信号,基于所述输入信号获得目标输出信号,向选择单元发送所述目标输出信号;所述混淆逻辑单元,用于接收所述输入信号,基于所述输入信号获得混淆输出信号,向选择单元发送所述混淆输出信号;所述密钥单元,用于向选择单元发送密钥信号;所述选择单元,用于接收所述目标输出信号、混淆输出信号和密钥信号,基于所述密钥信号,从所述目标输出信号、所述混淆输出信号中选择输出信号,输出选择的输出信号。(The invention discloses an integrated circuit chip, an integrated circuit and an electronic device, wherein the integrated circuit chip comprises: a target logic unit, an obfuscation logic unit, a key unit and a selection unit, wherein: the target logic unit is used for receiving an input signal, obtaining a target output signal based on the input signal and sending the target output signal to the selection unit; the confusion logic unit is used for receiving the input signal, obtaining a confusion output signal based on the input signal, and sending the confusion output signal to the selection unit; the key unit is used for sending a key signal to the selection unit; the selection unit is used for receiving the target output signal, the obfuscated output signal and the key signal, selecting an output signal from the target output signal and the obfuscated output signal based on the key signal, and outputting the selected output signal.)
1. An integrated circuit chip, the integrated circuit chip comprising: a target logic unit, an obfuscation logic unit, a key unit and a selection unit, wherein:
the target logic unit is used for receiving an input signal, obtaining a target output signal based on the input signal and sending the target output signal to the selection unit;
the confusion logic unit is used for receiving the input signal, obtaining a confusion output signal based on the input signal, and sending the confusion output signal to the selection unit;
the key unit is used for sending a key signal to the selection unit;
the selection unit is configured to receive the target output signal, the obfuscated output signal, and the key signal, select an output signal from the target output signal and the obfuscated output signal based on the key signal, and output the selected output signal.
2. The integrated circuit chip of claim 1, wherein the integrated circuit chip comprises at least one obfuscated logic cell, wherein the at least one obfuscated logic cell is of the same type, or is not the same type.
3. The integrated circuit chip of claim 1, wherein the number of obfuscated logic cells included in the integrated circuit chip is 2 when the key signal includes N key bitsN-1, wherein N is a positive integer.
4. The IC chip of claim 1 wherein the selection unit is 2 when the key signal contains N key bitsNAnd selecting a multiplexer, wherein N is a positive integer.
5. The integrated circuit chip of claim 1, wherein when the key signal contains 2 key bits, the number of obfuscated logic cells contained in the integrated circuit chip is 3; correspondingly, the selection unit is a 4-selection multiplexer.
6. The integrated circuit chip of any of claims 1-5,
the target logic unit is specifically configured to: performing logic operation on the input signal to obtain a target output signal;
the obfuscation logic unit is specifically configured to: and carrying out logic operation on the input signal to obtain an aliasing output signal.
7. An integrated circuit comprising at least one integrated circuit chip as claimed in any one of claims 1 to 6.
8. An electronic device, characterized in that the electronic device comprises the integrated circuit of claim 7.
Technical Field
The present invention relates to the field of integrated circuit chip protection technologies, and in particular, to an integrated circuit chip, an integrated circuit, and an electronic device.
Background
In the current manufacturing process of integrated circuits, Intellectual Property (IP) cores and integrated circuit chips have security risks, for example, an integrated circuit chip designer has no permission of the IP core designer to use the designed IP core; or the IC chip manufacturer repeatedly uses the authorized IP core to manufacture excessive IC chips, and then illegal sale is carried out; or the manufacturer of the integrated circuit chip sells the authorized IP core to a third party factory, and the like. No matter which behavior is described above, property and reputation loss will be brought to designers of the IP core and suppliers of the IP core, which is not favorable for the development of the IP core technology, and further has adverse effect on the development of the integrated circuit.
Disclosure of Invention
In order to solve the existing technical problems, embodiments of the present invention provide an integrated circuit chip, an integrated circuit and an electronic device.
In order to achieve the above purpose, the technical solution of the embodiment of the present invention is realized as follows:
in a first aspect, an embodiment of the present invention provides an integrated circuit chip, where the integrated circuit chip includes: a target logic unit, an obfuscation logic unit, a key unit and a selection unit, wherein:
the target logic unit is used for receiving an input signal, obtaining a target output signal based on the input signal and sending the target output signal to the selection unit;
the confusion logic unit is used for receiving the input signal, obtaining a confusion output signal based on the input signal, and sending the confusion output signal to the selection unit;
the key unit is used for sending a key signal to the selection unit;
the selection unit is used for receiving the target output signal, the obfuscated output signal and the key signal, selecting an output signal from the target output signal and the obfuscated output signal based on the key signal, and outputting the selected output signal.
In the above solution, the integrated circuit chip includes at least one obfuscated logic unit, where the at least one obfuscated logic unit is completely the same, or not completely the same in type.
In the above scheme, when the key signal includes N key bits, the number of the obfuscated logic units included in the integrated circuit chip is 2N-1, wherein N is a positive integer.
In the above scheme, when the key signal contains N key bits, the selection unit is 2NAnd selecting a multiplexer, wherein N is a positive integer.
In the above scheme, when the key signal comprises 2 key bits, the number of the obfuscated logic units included in the integrated circuit chip is 3; correspondingly, the selection unit is a 4-selection multiplexer.
In the foregoing solution, the target logic unit is specifically configured to: performing logic operation on the input signal to obtain a target output signal;
the obfuscation logic unit is specifically configured to: and carrying out logic operation on the input signal to obtain an aliasing output signal.
In a second aspect, an embodiment of the present invention further provides an integrated circuit, which includes at least one integrated circuit chip as described above.
In a third aspect, an embodiment of the present invention further provides an electronic apparatus, where the electronic apparatus includes the integrated circuit.
The embodiment of the invention provides an integrated circuit chip, an integrated circuit and an electronic device, wherein the integrated circuit chip comprises: a target logic unit, an obfuscation logic unit, a key unit and a selection unit, wherein: the target logic unit is used for receiving an input signal, obtaining a target output signal based on the input signal and sending the target output signal to the selection unit; the confusion logic unit is used for receiving the input signal, obtaining a confusion output signal based on the input signal, and sending the confusion output signal to the selection unit; the key unit is used for sending a key signal to the selection unit; the selection unit is used for receiving the target output signal, the obfuscated output signal and the key signal, selecting an output signal from the target output signal and the obfuscated output signal based on the key signal, and outputting the selected output signal. By adopting the integrated circuit chip provided by the embodiment of the invention, the correct logic function can be output only when a user provides the correct key; otherwise, the wrong logic function is output, and for this reason, the design of the integrated circuit chip and the design of the integrated circuit containing the integrated circuit chip can be protected from being hacked, thereby ensuring that the benefit of the designer is not damaged.
Drawings
FIG. 1 is a diagram illustrating an integrated circuit with a protection structure according to the related art;
FIG. 2 is a schematic diagram of an integrated circuit chip according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an integrated circuit structure including an integrated circuit chip according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a dual-input integrated circuit chip according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a 4-out-of-one multiplexer according to an embodiment of the present invention;
fig. 6 is a schematic diagram of an integrated circuit including a dual-input integrated circuit chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following describes specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
To facilitate understanding of the embodiments of the present invention, a brief description of the related art will be given.
An Integrated Circuit (IC) is a type of microelectronic device or component. The IC has the advantages of small volume, light weight, few lead wires and welding points, long service life, high reliability, good performance and the like. According to the difference of IC function and structure, IC can be divided into three categories of analog IC, digital IC and digital/analog mixed IC.
In the design of an IC chip, an IP core refers to a pre-designed Circuit function module used in an Application Specific Integrated Circuit (ASIC) or a Field-programmable Gate Array (FPGA). The IP core plays an important role in the modern integrated circuit industry chain, so that the time for designing the integrated circuit can be saved, and the cost for producing the integrated circuit can be reduced.
The modern integrated circuit industry chain begins with IP core designers, which primarily design certain functional blocks within an integrated circuit chip, rather than the integration of an entire IC chip, which designs an IP core and outsources it to other integrated circuit chip designers in the form of soft, hard, and hard cores. The integrated circuit chip designer designs the function of the whole integrated circuit chip, and then integrates different IP cores and other integrated circuit function models to form the final integrated circuit chip design. The final integrated circuit chip design may also be outsourced to third party companies for logic synthesis and place and route. The third party company may then return the resulting integrated circuit chip to the integrated circuit designer or send it directly to a foundry for fabrication.
In the manufacturing process of the integrated circuit chip, the final integrated circuit chip is formed through cooperation of multiple parties, and on the basis, potential safety hazards exist, and property and reputation loss can be caused to both designers of the IP core and suppliers of the IP core.
Based on the above description, in order to solve the hardware security problem of the IP core and the integrated circuit chip, in the related art, the circuit in the integrated circuit chip is obfuscated or encrypted by randomly inserting an exclusive or gate (XOR) and/or an exclusive nor gate (XNOR) into the integrated circuit chip, and the integrated circuit chip can output a correct logic function only when a user provides a correct key; otherwise, when the user can not provide the correct key, the inserted exclusive or gate (XOR) and/or exclusive nor gate (XNOR) will change the original logic function, so that the integrated circuit chip outputs the wrong logic function, thereby ensuring the hardware security of the IP core and the integrated circuit chip.
Specifically, fig. 1 is a schematic diagram of an integrated circuit with a protection structure in the related art. As shown in fig. 1, the integrated circuit with protection structure comprises: input signals I1-I6; K1K2 is a two-bit key; an exclusive or gate (XOR) and an exclusive nor gate (XNOR) are logic gates newly inserted into the integrated circuit for protecting the integrated circuit; the rest logic gates are original in the integrated circuit; o1 and O2 are two-way output signals.
Assuming that the designer of the integrated circuit with protection architecture has K1 ═ 0 and K2 ═ 1 as the correct keys, then the correct keys are provided to the user, i.e.: only when K1 is equal to 0 and K2 is equal to 1, the integrated circuit with the protection structure can output a correct output signal, that is: the correct logic function; otherwise, the integrated circuit with the protection structure will output a wrong output signal, that is: the wrong logic function.
However, if only a simple inserted exclusive or gate (XOR) and/or exclusive nor gate (XNOR) is used in the design of the integrated circuit, when the integrated circuit is attacked by the integrated circuit reverse engineering based on the image extraction technology, the gate-level netlist of the integrated circuit will be exposed, and an attacker can deduce the key through the inserted exclusive or gate (XOR) and/or exclusive nor gate (XNOR), thereby causing the leakage of the key.
To solve the above problem, fig. 2 is a schematic structural diagram of an integrated circuit chip according to an embodiment of the present invention. As shown in fig. 2, the
a target logic unit 201, configured to receive an input signal, obtain a target output signal based on the input signal, and send the target output signal to a selection unit 204;
an
a key unit 203 for transmitting a key signal to the selection unit 204;
a selecting unit 204, configured to receive the target output signal sent by the target logic unit 201, the obfuscated output signal sent by the
It should be noted that the target logic unit 201 is any logic gate in the integrated circuit, in other words, the target logic unit 201 may be a logic gate actually required by the integrated circuit designer when designing the integrated circuit, such as an AND gate (AND), OR gate (OR), AND the like.
In some embodiments, the key unit 203 may be a key bit register, which receives a key bit input by a user, generates a key signal carrying the key bit based on the key bit, and sends the key signal to the selection unit 204.
Here, the user refers to a user who uses the integrated
For example, when the key signal includes N key bits, the user needs to provide N correct keys to output a correct output signal. The time complexity is 2N when the key signal with the length of N bits is to be cracked, so that the cracking difficulty is greatly increased. By time complexity is meant the time it takes to complete a certain event.
In some embodiments, the
It should be noted that the obfuscated
It should be noted that the selection unit 204 may be a one-out-of-multiple selector, that is, a path of output signal is selected from the output signals received by the target logic unit 201 and the
In some embodiments, when the key signal includes 2 key bits, the number of
It should be noted that the target logic unit 201 is specifically configured to: performing logic operation on the input signal to obtain a target output signal;
the
For example, if the target logic unit 201 is an OR gate (OR), the target logic unit 201 performs an OR logic operation on the input signal to obtain a target output signal. If the
Based on the above inventive concept, the embodiment of the present invention further provides an integrated circuit, which includes at least one
It should be noted that the
Illustratively, as shown in fig. 3, a schematic diagram of an integrated circuit structure including an integrated
It should be noted that, when an integrated circuit design includes M integrated
Based on the above inventive concept, an embodiment of the present invention further provides an electronic device, which includes the integrated circuit.
It should be noted that the integrated circuit including the integrated
For better understanding of the embodiments of the present invention, the inventive concept is illustrated below by taking a two-input logic gate as an example.
Fig. 4 is a schematic structural diagram of a dual-input integrated circuit chip according to an embodiment of the present invention, and as shown in fig. 4, the dual-input integrated
a target double-gate logic unit 401, configured to receive an input signal a and an input signal B, obtain a target output signal based on the input signal a and the input signal B, and send the target output signal to a 1-out-of-4 multiplexer 405;
a first aliasing logic unit 402, configured to receive an input signal a and an input signal B, obtain a first aliasing output signal based on the input signal a and the input signal B, and send the first aliasing output signal to a 1-out-of-4 multiplexer 405;
a second aliasing logic unit 403, configured to receive an input signal a and an input signal B, obtain a second aliasing output signal based on the input signal a and the input signal B, and send the second aliasing output signal to a 1-out-of-4 multiplexer 405;
a third aliasing logic unit 404, configured to receive an input signal a and an input signal B, obtain a third aliasing output signal based on the input signal a and the input signal B, and send the third aliasing output signal to a 1-out-of-4 multiplexer 405;
a one-out-of-4 multiplexer 405 for receiving the target output signal, the first obfuscated output signal, the second obfuscated output signal and a third obfuscated output signal, selecting an output signal from the target output signal, the first obfuscated output signal, the second obfuscated output signal and the third obfuscated output signal based on the key signal sent by the key unit 203, and outputting the selected output signal.
It should be noted that dual-input integrated
It should be noted that the first obfuscating logic unit 402, the second obfuscating logic unit 403, and the third obfuscating logic unit 404 are specific forms of the obfuscating
It should be noted that, according to the above description, the number of the obfuscating
In some embodiments, the key signal controls the logic of the 1-out-of-4 multiplexer to select an output signal from the target output signal, the first obfuscated output signal, the second obfuscated output signal, and a third obfuscated output signal, as shown in table 1.
K1
K2
Oi
0
0
0
1
1
0
1
1
O4
Wherein, in Table 1, OiThe output signal is selected by a 4-to-1 multiplexer; o is1Outputting a signal for a target; o is2A first aliased output signal; o is3A second aliased output signal; o is4Is the third aliased output signal.
For the above OiThe following formula can be used for this:
based on this, the structure of the 4-to-1 multiplexer, as shown in FIG. 5, is optional, and the reference numerals 1-4 are logic NOT gates, denoted by K1The function of the connected
As can be seen from Table 1, the designer of the dual input integrated
In some embodiments, the dual-input integrated
Illustratively, as shown in fig. 6, a schematic diagram of an integrated circuit structure including a dual-input integrated
It should be appreciated that reference throughout this specification to "one embodiment" or "some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of the processes should be determined by their functions and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention. The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
It should be noted that, in the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. The above-described terminal embodiments are only illustrative, for example, the division of the unit is only a logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
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