阅读说明：本技术 免保持动态d触发器 (Hold-free dynamic D flip-flop ) 是由 刘杰尧 张楠赓 吴敬杰 马晟厚 于 2018-06-25 设计创作，主要内容包括：本发明提供一种在计算设备中应用的免保持动态D触发器,包括一输入端、一输出端以及至一时钟信号端；一第一锁存单元,用于传输所述输入端的数据并在时钟信号控制下锁存所述数据；一第二锁存单元,用于锁存所述输出端的数据并在时钟信号控制下将所述第一锁存单元锁存的所述数据反相传输；一输出驱动单元,用于反相并输出从所述第二锁存单元接收到的所述数据；所述第一锁存单元、所述第二锁存单元以及所述输出驱动单元依次串接在所述输入端和所述输出端之间；其中,所述第二锁存单元在时钟信号控制下通过单一元件实现高电平、低电平和高阻三种状态的输出；所述第一锁存单元采用延迟单元。可以简化后端布局布线流程,降低设计难度,提高性能,增加实用性。(The invention provides a hold-free dynamic D trigger applied in computing equipment, which comprises an input end, an output end and a clock signal end, wherein the input end is connected with the clock signal end; the first latch unit is used for transmitting the data of the input end and latching the data under the control of a clock signal; the second latch unit is used for latching the data at the output end and transmitting the data latched by the first latch unit in an inverted way under the control of a clock signal; an output driving unit for inverting and outputting the data received from the second latch unit; the first latch unit, the second latch unit and the output driving unit are sequentially connected in series between the input end and the output end; the second latch unit outputs three states of high level, low level and high resistance through a single element under the control of a clock signal; the first latch unit adopts a delay unit. The back-end layout wiring process can be simplified, the design difficulty is reduced, the performance is improved, and the practicability is improved.)

1. A hold-free dynamic D flip-flop, comprising:

an input terminal, an output terminal and a clock signal terminal;

the first latch unit is used for transmitting the data of the input end and latching the data under the control of a clock signal;

the second latch unit is used for latching the data at the output end and transmitting the data latched by the first latch unit in an inverted way under the control of a clock signal;

an output driving unit for inverting and outputting the data received from the second latch unit;

the first latch unit, the second latch unit and the output driving unit are sequentially connected in series between the input end and the output end;

the second latch unit outputs three states of high level, low level and high resistance through a single element under the control of a clock signal; the first latch unit adopts a delay unit.

2. The hold-free dynamic D flip-flop of claim 1, wherein: the clock signal end is connected with a clock buffer, and the clock buffer adopts an ultra-low threshold unit.

3. The hold-free dynamic D flip-flop of claim 2, wherein: the second latch unit is a tri-state inverter.

4. The hold-free dynamic D flip-flop of claim 3, wherein: the tri-state inverter further comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are sequentially connected in series between a power supply and the ground.

5. The hold-free dynamic D flip-flop of claim 4, wherein: and the first PMOS transistor and the second NMOS transistor are subjected to switch control according to a clock signal, and the clock signals of the first PMOS transistor and the second NMOS transistor are in opposite phases.

6. The hold-free dynamic D flip-flop of claim 4, wherein: and the second PMOS transistor and the first NMOS transistor are subjected to switch control according to clock signals, and the clock signals of the second PMOS transistor and the first NMOS transistor are in reverse phase.

7. A data arithmetic unit comprises a control circuit, an arithmetic circuit and a plurality of hold-free dynamic D triggers which are connected in an interconnecting way, wherein the hold-free dynamic D triggers are connected in series and/or in parallel; the method is characterized in that: the plurality of keep-free dynamic D flip-flops are the keep-free dynamic D flip-flops of any one of claims 1-6.

8. A chip comprising a data arithmetic unit as claimed in any one of claim 7.

9. An algorithm board for a computing device comprising a plurality of said chips of any one of claim 8.

10. A computing device comprises a power panel, a control panel, a connecting plate, a radiator and a plurality of computing plates, wherein the control panel is connected with the computing plates through the connecting plate, the radiator is arranged around the computing plates, the power panel is used for providing power for the connecting plate, the control panel, the radiator and the computing plates, and the computing plates are characterized in that: the force calculation board is any one of the force calculation boards described in claim 9.

11. The computing device of claim 10, wherein: the computing device is for mining operations of virtual digital currency.

Technical Field

The present invention relates to a clocked memory device, and more particularly, to a hold-free dynamic D flip-flop for use in a computing device.

Background

Virtual currency (e.g., bitcoin, ethernet) is a digital currency in the form of P2P, which has received much attention since the 2009 bitcoin system. The system constructs the distributed shared general ledger based on the block chain, thereby ensuring the safety, reliability and decentralization of the system operation.

In hashing and proof of workload, bitcoin is the only correct hash value calculated to prove the workload to obtain accounting packed block right and thus the reward, which is proof of workload (Pow).

At present, no effective algorithm is available for hash operation except for brute force calculation. The bitcoin mining starts with low-cost hardware such as a CPU or a GPU, but with the prevalence of bitcoins, the mining process changes greatly. Today, excavation activities are transferred to Field Programmable Gate Arrays (FPGAs) or application specific chips (ASICs), which are very efficient in excavation mode.

The D trigger has wide application and can be used as a register of a digital signal, a shift register, a frequency division generator, a waveform generator and the like. The D flip-flop has two inputs, Data and Clock (CLK), with one output (Q), into or from which Data can be written or read.

CN1883116A discloses a positive feedback D flip-flop circuit 106 as shown in fig. 1, comprising an analog switch 300, an inverter 302, an analog switch 304, an inverter 306, an inverter 308, an analog switch 310, an inverter 312, and an analog switch 314. The analog switches 300, 304, 310, and 314 are analog switches using P-channel/N-channel transistors, and perform switching operations by CKP in phase with CK and CKN in phase opposite to CK. Inverters 302, 306, inverters 308, and 312 are CMOS inverters. It can be seen that a conventional D flip-flop basically needs 16 PMOS/NMOS transistors, which occupies a large area.

For a new generation of computing devices for mining virtual digital currency, the mining process is a logical computing pipeline that performs a large number of iterations, requiring several D-flip-flops to store data. Therefore, in a computing device requiring a large number of D flip-flops, the defects of increased chip area, slow operation speed and poor control of leakage can be caused.

CN1883116A also discloses a dynamic D flip-flop circuit 102 as shown in fig. 2, where the dynamic D flip-flop circuit 102 includes a 1 st analog switch 200, a 1 st inverter 202, a 2 nd analog switch 204, and a 2 nd inverter 206. The dynamic D flip-flop circuit 102 constitutes a sample-and-hold circuit by an analog switch of the 1 st analog switch 200 and the 2 nd analog switch 204, and a parasitic capacitance such as a gate capacitance and a wiring capacitance of the 1 st inverter 202 and the 2 nd inverter 206.

The register composed of the dynamic D trigger has the problems that an analog switch is difficult to control and the access speed is low.

Disclosure of Invention

In order to solve the above problems, the present invention provides a hold-free dynamic D flip-flop for a computing device, which can effectively reduce design difficulty, reduce chip area, reduce power consumption, and implement clock synchronization.

In order to achieve the above object, the present invention provides a hold-free dynamic D flip-flop, comprising:

an input terminal, an output terminal and a clock signal terminal;

the first latch unit is used for transmitting the data of the input end and latching the data under the control of a clock signal;

the second latch unit is used for latching the data at the output end and transmitting the data latched by the first latch unit in an inverted way under the control of a clock signal;

an output driving unit for inverting and outputting the data received from the second latch unit;

the first latch unit, the second latch unit and the output driving unit are sequentially connected in series between the input end and the output end;

the second latch unit outputs three states of high level, low level and high resistance through a single element under the control of a clock signal; the first latch unit adopts a delay unit.

In the hold-free dynamic D flip-flop, the clock signal terminal is connected to a clock buffer, and the clock buffer adopts an ultra-low threshold unit.

In the above-mentioned hold-free dynamic D flip-flop, the second latch unit is a tri-state inverter.

In the above-mentioned hold-free dynamic D flip-flop, the tri-state inverter further includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, and the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are sequentially connected in series between the power supply and the ground.

In the above-mentioned hold-free dynamic D flip-flop, the first PMOS transistor and the second NMOS transistor perform switching control according to a clock signal, and clock signals of the first PMOS transistor and the second NMOS transistor are inverted.

In the hold-free dynamic D flip-flop, the second PMOS transistor and the first NMOS transistor are switched according to a clock signal, and the clock signals of the second PMOS transistor and the first NMOS transistor are inverted.

By using the hold-free dynamic D trigger, the area of a chip can be reduced by nearly 30 percent, so that the production cost of the chip is reduced, and the product competitiveness is increased. The back-end layout and wiring design process can be simplified, the design difficulty is reduced, the performance is improved, and the practicability is improved.

In order to better achieve the above object, the present invention further provides a data operation unit, which includes a control circuit, an operation circuit, and a plurality of hold-free dynamic D flip-flops connected in series and/or in parallel; wherein the plurality of keep-free dynamic D flip-flops are any one of the keep-free dynamic D flip-flops.

In order to better achieve the above object, the present invention further provides a chip, which employs any one of the above data operation units.

In order to better achieve the above object, the present invention further provides a computing board for a computing device, which employs any one of the above chips.

In order to better achieve the above object, the present invention further provides a computing device, which includes a power board, a control board, a connecting board, a heat sink, and a plurality of computing boards, wherein the control board is connected to the computing boards through the connecting board, the heat sink is disposed around the computing boards, and the power board is configured to provide power to the connecting board, the control board, the heat sink, and the computing boards are any one of the computing boards.

Preferably, the computing device is for operations to mine virtual digital currency.

The computing equipment can better save the chip area, reduce the production cost and further reduce the power consumption of the computing equipment.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "connected" is intended to encompass any direct or indirect electrical connection. Indirect electrical connection means include connection by other means.

Drawings

FIG. 1 is a schematic diagram of a conventional positive feedback D flip-flop;

FIG. 2 is a diagram of a conventional dynamic D flip-flop;

FIG. 3A is a diagram illustrating a structure of a hold-free dynamic D flip-flop according to an embodiment of the present invention;

FIG. 3B is a schematic diagram of a keeper-free dynamic D flip-flop with clock control according to an embodiment of the present invention;

FIG. 4A is a circuit diagram of a hold-free dynamic D flip-flop according to an embodiment of the present invention;

FIG. 4B is a circuit diagram of a hold-free dynamic D flip-flop according to another embodiment of the present invention;

FIG. 5A is an equivalent circuit diagram of the hold-free dynamic D flip-flop writing data according to the present invention;

FIG. 5B is an equivalent circuit diagram of the data retention state of the retention-free dynamic D flip-flop according to the present invention;

FIG. 6 is a timing diagram of a hold-free dynamic D flip-flop according to the present invention;

FIG. 7 is a schematic diagram of a data operation unit according to the present invention;

FIG. 8 is a diagram of a chip according to the present invention;

FIG. 9 is a schematic view of a force computation plate according to the present invention;

FIG. 10 is a schematic diagram of a computing device of the present invention.

Wherein, the reference numbers:

100: parasitic capacitance 102: dynamic D flip-flop

106: positive feedback D flip-flop circuit

200, 204, 300, 304, 310, 314: analog switch

400, 400',500, 600: hold-free dynamic D flip-flop

401: the first latch unit 402: second latch unit

403: output drive unit 404: input terminal

405: output terminal 406: clock buffer

501, 601: transmission gates 502, 602: three-state inverter

202, 206, 302, 306, 308, 312, 503, 603: inverter with a capacitor having a capacitor element

506, 510, 511: PMOS transistors 507, 512, 513: NMOS transistor

508, 509, 514, 515: gate terminals 550, 551, 650, 651: node point

504, 604: input terminals 505, 605: output end

CLK, CLKN, CLKP, clock signal

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

fig. 3A is a schematic diagram of a hold-free dynamic D flip-flop according to an embodiment of the present invention. Referring to fig. 3A, a hold-free dynamic D flip-flop 400 is composed of a first latch unit 401, a second latch unit 402, and an output driving unit 403. The first latch unit 401, the second latch unit 402, and the output driving unit 403 are sequentially connected in series between the input terminal 404 and the output terminal 405 of the hold-free dynamic D flip-flop 400.

FIG. 3B is a diagram of a keeper-free dynamic D flip-flop with clock control according to an embodiment of the present invention. Referring to fig. 3B, the retention-free dynamic D flip-flop 400' with clock control is composed of the retention-free dynamic D flip-flop 400 and a clock buffer 406. The clock signal CLK provides a clock control signal to the hold-free dynamic D flip-flop 400 after being buffered by the clock buffer 406.

The first latch unit 401 of the hold-free dynamic D flip-flop of the present invention is designed as a delay unit, and the clock buffer 406 is designed as a high-speed unit. The following is a detailed description.