Isolator
阅读说明:本技术 隔离器 (Isolator ) 是由 马春宇 孙瑞亭 刘姗姗 李金良 于 2019-09-18 设计创作,主要内容包括:本发明公开了一种隔离器,涉及隔离器领域。包括:控制电路,以及依次连接的振荡电路、耦合传输电路、解调电路和输出电路,振荡电路设置有信号输入端、第一接地端和控制端,输出电路设置有信号输出端和第二接地端。本发明提供的隔离器,具有四个端口,能够兼容四端口光耦合器,极大地改善了隔离器的抗电磁干扰性能,具有芯片体积小、功耗低、抗电磁干扰性能好和可靠性高的优点。(The invention discloses an isolator, and relates to the field of isolators. The method comprises the following steps: the circuit comprises a control circuit, and an oscillation circuit, a coupling transmission circuit, a demodulation circuit and an output circuit which are connected in sequence, wherein the oscillation circuit is provided with a signal input end, a first grounding end and a control end, and the output circuit is provided with a signal output end and a second grounding end. The isolator provided by the invention has four ports, can be compatible with a four-port optical coupler, greatly improves the anti-electromagnetic interference performance of the isolator, and has the advantages of small chip volume, low power consumption, good anti-electromagnetic interference performance and high reliability.)
1. An isolator, comprising: control circuit to and the oscillating circuit, coupling transmission circuit, demodulation circuit and the output circuit who connects gradually, oscillating circuit is provided with signal input part, first earthing terminal and control end, output circuit is provided with signal output part and second earthing terminal, wherein:
the oscillating circuit is used for acquiring an input signal through the signal input end and converting the input signal into a first oscillating signal; the control circuit is connected with the oscillating circuit through the control end and is used for controlling the frequency of the first oscillating signal to change within a preset range to obtain a second oscillating signal; the coupling transmission circuit is used for transmitting the second oscillating signal to the demodulation circuit in an isolation manner; the demodulation circuit is used for demodulating the second oscillation signal; the output circuit is used for obtaining an output signal according to the demodulated second oscillating signal.
2. The isolator according to claim 1, wherein the control circuit is specifically configured to control the frequency of the first oscillating signal to randomly vary within a preset range, so as to obtain the second oscillating signal.
3. The isolator of claim 1, wherein the oscillating circuit comprises: the MOS transistor group comprises N MOS transistor groups and N control switch groups for respectively controlling each MOS transistor group, wherein the parasitic capacitance of each MOS transistor group is different from each other, and N is more than or equal to 2;
the control circuit is specifically configured to control the MOS transistor group connected to the oscillation circuit through the control switch group, and control the frequency of the first oscillation signal according to a parasitic capacitance of the MOS transistor group connected to the oscillation circuit.
4. An isolator as claimed in claim 3, wherein all of the MOS transistors of the first type in the first group of MOS transistors are the same size; the size of the MOS transistor of the first type in the first MOS transistor group is different from that of the MOS transistor of the first type in the second MOS transistor group;
the first MOS transistor group is any one of the N MOS transistor groups, the second MOS transistor group is any one of the N MOS transistor groups except the first MOS transistor group, and the first type MOS transistor is a PMOS transistor or an NMOS transistor.
5. The isolator of claim 3, wherein when the oscillating circuit is a complementary cross-coupled oscillating circuit, the oscillating circuit further comprises: the first electric capacity and first inductance, the nth MOS transistor group includes: first PMOS pipe, second PMOS pipe, first NMOS pipe and second NMOS pipe, nth control switch group include 4 control switches, set up the grid at every MOS transistor respectively, wherein:
the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and serves as the signal input end; the drain electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube, one end of the first capacitor, one end of the first inductor, the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube; the grid electrode of the first PMOS tube is respectively connected with the drain electrode of the second PMOS tube, the other end of the first capacitor, the other end of the first inductor, the grid electrode of the first NMOS tube and the drain electrode of the second NMOS tube; and the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and is used as the first grounding end, and N belongs to N.
6. The isolator of claim 3, wherein when the oscillating circuit is an NMOS cross-coupled oscillating circuit, the oscillating circuit further comprises: the second inductor is a center tap structure, a center end of the second inductor is used as the signal input end, and the nth MOS transistor group comprises: third NMOS pipe and fourth NMOS pipe, nth control switch group include 2 control switches, set up respectively at the grid of every MOS transistor, wherein:
the drain electrode of the third NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube, one end of the second capacitor and one end of the second inductor; the grid electrode of the third NMOS tube is respectively connected with the drain electrode of the fourth NMOS tube, the other end of the second capacitor and the other end of the second inductor; and the source electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube and serves as the first grounding end, and N belongs to N.
7. The isolator according to any one of claims 1 to 6, wherein the coupling transmission circuit is a transformer coupling transmission circuit or a capacitive coupling transmission circuit.
8. The isolator of claim 7, wherein the transformer-coupled transmission circuit comprises a cascade of transformers and the capacitive-coupled transmission circuit comprises a cascade of capacitors.
9. A package, comprising: a first chip and a second chip, wherein:
the first chip is packaged by the control circuit, the oscillating circuit and the coupling transmission circuit in the isolator of any one of claims 1 to 8;
the second chip is packaged by the demodulation circuit and the output circuit in the isolator of any one of claims 1 to 8.
10. An electronic device, characterized by comprising the isolator as claimed in any one of claims 1 to 8.
Technical Field
The invention relates to the field of isolators, in particular to an isolator compatible with four-port optical coupler pins.
Background
In electronic devices such as military electronic systems, aerospace devices, and medical devices, in order to eliminate signal noise and protect devices and users from high voltage, isolators are generally added to the electronic devices.
The optical coupler is always the main choice of the isolator, but has the defects of easy aging, high power consumption, short service life and the like, and the use scenes of the optical coupler are limited. The isolator manufactured by using the integrated circuit process has more advantages in the aspects of power consumption, performance, reliability and the like, and can be used for replacing the optical coupler.
However, when the optical coupler is replaced by the four-port isolator, the oscillator generates strong electromagnetic interference in the whole circuit, thereby resulting in poor anti-electromagnetic interference capability of the isolator used for replacing the optical coupler.
Disclosure of Invention
The invention aims to solve the technical problem of the prior art and provides an isolator compatible with four-port optical coupler pins.
The technical scheme for solving the technical problems is as follows:
an isolator, comprising: control circuit to and the oscillating circuit, coupling transmission circuit, demodulation circuit and the output circuit who connects gradually, oscillating circuit is provided with signal input part, first earthing terminal and control end, output circuit is provided with signal output part and second earthing terminal, wherein:
the oscillating circuit is used for acquiring an input signal through the signal input end and converting the input signal into a first oscillating signal; the control circuit is connected with the oscillating circuit through the control end and is used for controlling the frequency of the first oscillating signal to change within a preset range to obtain a second oscillating signal; the coupling transmission circuit is used for transmitting the second oscillating signal to the demodulation circuit in an isolation manner; the demodulation circuit is used for demodulating the second oscillation signal; the output circuit is used for obtaining an output signal according to the demodulated second oscillating signal.
The invention has the beneficial effects that: the isolator provided by the invention has four ports, can be compatible with a four-port optical coupler, changes the frequency of an oscillation signal generated by an oscillation circuit through a control circuit to enable the oscillation signal to change within a preset range, and then performs coupling transmission and demodulation on the oscillation signal to realize isolated transmission of an analog signal or a digital signal.
Another technical solution of the present invention for solving the above technical problems is as follows:
a package, comprising: a first chip and a second chip, wherein:
the first chip is formed by packaging a control circuit, an oscillating circuit and a coupling transmission circuit in the isolator in the technical scheme;
the second chip is formed by packaging the demodulation circuit and the output circuit in the isolator in the technical scheme.
Another technical solution of the present invention for solving the above technical problems is as follows:
an electronic device comprising the isolator according to the above technical solution.
Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic structural framework provided by an embodiment of the isolator of the present invention;
FIG. 2 is a schematic diagram showing a comparison of EMI spectra provided by an embodiment of the isolator of the present invention;
FIG. 3 is a schematic diagram of signal waveforms provided by an embodiment of an isolator according to the present invention;
FIG. 4 is a schematic circuit diagram of an isolator according to another embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of an isolator according to another embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of an isolator according to another embodiment of the present invention;
FIG. 7 is a schematic circuit diagram of an isolator according to another embodiment of the present invention;
fig. 8 is a schematic diagram of a transformer cascade structure provided in another embodiment of the isolator according to the present invention;
FIG. 9 is a schematic diagram of a capacitor cascade structure provided in another embodiment of the isolator of the present invention;
fig. 10 is a schematic diagram of a chip package structure according to an embodiment of the package.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth to illustrate, but are not to be construed to limit the scope of the invention.
As shown in fig. 1, a schematic structural framework is provided for an embodiment of the isolator of the present invention, the isolator including: control circuit 1 to and
the
It should be noted that the
The preset range can be set according to the actual requirements of the user.
The inventor finds that the electromagnetic interference is mainly caused by that an oscillator in a four-port isolator used for replacing an optical coupler operates at a constant frequency, the whole circuit generates strong electromagnetic interference at the constant frequency, and the frequency of an oscillating signal is controlled to change within a certain range and not be continuously constant at a certain frequency, so that the interference can be effectively suppressed.
As shown in fig. 2, an exemplary EMI (Electromagnetic Interference) spectrum comparison diagram is shown, in fig. 2, a graph of an EMI spectrum of an isolator operating in a constant frequency state and an isolator operating in a random frequency state within a fixed bandwidth is shown, wherein a horizontal axis f is a frequency of an oscillating signal, and a vertical axis E is an EMI energy value.
As can be seen from fig. 2, when the oscillator in the isolator operates at a constant frequency fc, the energy of the electromagnetic interference is concentrated at this frequency point, and the energy value of the spike is E0. When the oscillation frequency of the oscillator randomly changes in the bandwidth B, the energy of the electromagnetic interference can be uniformly dispersed, so that the electromagnetic interference on each frequency point is remarkably reduced, and the maximum energy E1 of the electromagnetic interference in the frequency band is far lower than E0. Therefore, the EMI performance of the isolator can be obviously improved by controlling the frequency of the oscillating signal to randomly change within a certain range.
Preferably, the
Preferably, an under-voltage lockout protection circuit may also be provided in the control circuit 1 to be inoperative during power-up and power-down.
Preferably, a resistor can be connected to the emitter of the triode, so that the linearity of the output signal can be improved.
It should be noted that, in addition to the
Fig. 3 is a schematic diagram of waveforms of digital signals during the operation of the isolator, and the operation principle of the isolator will be described below with reference to fig. 3 by taking the digital signals as an example.
As can be seen from fig. 3, when the input digital signal is a high-level signal, the oscillating
It should be understood that when an analog signal is input, the triode works in the amplification region, and the output signal and the input signal are in a linear relation; when a digital signal is input, the triode transistor operates in a cut-off region (input low level) and a saturation region (input high level), and an output signal is opposite in phase to the input signal.
It will be appreciated that the isolator has 4 ports, the
The isolator provided by the embodiment has four ports and can be compatible with a four-port optical coupler, the frequency of an oscillating signal generated by the oscillating
Optionally, in some embodiments, the control circuit 1 is specifically configured to control the frequency of the first oscillation signal to randomly change within a preset range, so as to obtain the second oscillation signal.
Specifically, the control can control the on and off of each MOS transistor gate switch by randomly generating a pseudo-random sequence, so as to generate a randomly varying frequency, which has no regularity, and thus, by randomly varying the frequency within a preset range, the electromagnetic interference can be reduced to the maximum extent.
Optionally, in some embodiments, the
the control circuit 1 is specifically configured to control the MOS transistor group connected to the
It should be noted that the number N of the MOS transistor groups may be set according to actual requirements, and the types and the numbers of the MOS transistors included in the MOS transistor groups are different for
The number of control switches in the control switch group is the same as the number of MOS transistors in the MOS transistor group, for example, for the complementary cross-coupled
For example, assuming that there are 5 MOS transistor groups in total, the control circuit 1 may send 5 control signals, each control signal controls each MOS transistor group, and assuming that the first control signal is high and the other control signals are low, it may indicate that switches of all MOS transistors in the first MOS transistor group are closed, the first MOS transistor group is connected to the
Similarly, when the second control signal is high and the other control signals are low, the
It should be understood that when the first control signal and the second control signal are high and the other control signals are low, the switches controlling all the MOS transistors in the first group and the second group of MOS transistors are closed and the other switches are open, and when the first group and the second group of MOS transistors are connected to the
Control circuit 1 is through the MOS transistor group of control switch group control
Optionally, in some embodiments, in the first MOS transistor group, all the MOS transistors of the first type are the same size; the size of the MOS transistor of the first type in the first MOS transistor group is different from that of the MOS transistor of the first type in the second MOS transistor group;
the first MOS transistor group is any one of the N MOS transistor groups, the second MOS transistor group is any one of the N MOS transistor groups except the first MOS transistor group, and the first type MOS transistor is a PMOS transistor or an NMOS transistor.
For example, if the
The sizes of the PMOS transistor in the first group of MOS transistor group and the PMOS transistor in the second group of MOS transistor group are different, and the sizes of the NMOS transistor in the first group of MOS transistor group and the NMOS transistor in the second group of MOS transistor group are also different.
The size generally refers to the width-to-length ratio of the MOS transistor, and when a circuit is designed, different MOS transistors have different width-to-length ratios, and the size of the MOS transistor affects the overcurrent capacity of the MOS transistor.
It should be understood that the over-current capability of all PMOS and NMOS transistors within the same group should be guaranteed to be substantially the same.
It should be noted that the oscillation frequency can be determined by the oscillation inductance and the oscillation capacitance, the oscillation capacitance is determined by both the original capacitance of the
By setting different sizes of each group of MOS transistor group, the obtained frequency change is more uniform, and the phenomenon that specific frequency is concentrated and appears for many times when the control circuit 1 controls the random change of the oscillation signal is prevented, so that the realization effect of the invention is influenced.
Optionally, in some embodiments, when the
the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and serves as a signal input end; the drain electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube, one end of the first capacitor, one end of the first inductor, the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube; the grid electrode of the first PMOS tube is respectively connected with the drain electrode of the second PMOS tube, the other end of the first capacitor, the other end of the first inductor, the grid electrode of the first NMOS tube and the drain electrode of the second NMOS tube; the source electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube and serves as a first grounding end, and N belongs to N.
It should be understood that each MOS transistor group has 2 PMOS transistors and 2 NMOS transistors, and the
Optionally, in some embodiments, when the
the drain electrode of the third NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube, one end of the second capacitor and one end of the second inductor; the grid electrode of the third NMOS tube is respectively connected with the drain electrode of the fourth NMOS tube, the other end of the second capacitor and the other end of the second inductor; and the source electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube and serves as a first grounding end, and N belongs to N.
It should be understood that each MOS transistor group has 2 NMOS transistors, and the
Optionally, in some embodiments, the
Next, referring to fig. 4, fig. 5, fig. 6, and fig. 7, a circuit structure of the isolator is further described.
In the example of the isolator of fig. 4, it comprises: control circuit 1,
The
The grid of each MOS transistor is provided with a control switch, the 1 st MOS transistor group comprises a control switch SP1.1, a control switch SP2.1, a control switch SN1.1 and a control switch SN2.1, the control switch SP1.1 controls a PMOS transistor MP1.1, the control switch SP2.1 controls the PMOS transistor MP2.1, the control switch SN1.1 controls an NMOS transistor MN1.1, and the control switch SN2.1 controls the NMOS transistor MN 2.1.
Similarly, the nth MOS transistor group includes a control switch sp1.N, a control switch sp2.N, a control switch sn1.N, and a control switch sn2.N, where the control switch sp1.N controls the PMOS transistor mp1.N, the control switch sp2.N controls the PMOS transistor mp2.N, the control switch sn1.N controls the NMOS transistor mn1.N, and the control switch sn2.N controls the NMOS transistor mn2. N.
It should be noted that the PMOS transistor MP1.1 represents the 1 st PMOS transistor in the 1 st MOS transistor group, the PMOS transistor MP2.1 represents the 2 nd PMOS transistor in the 1 st MOS transistor group, and similarly, the NMOS transistor MN1.1 represents the 1 st NMOS transistor in the 1 st MOS transistor group, and the NMOS transistor MN2.1 represents the 2 nd NMOS transistor in the 1 st MOS transistor group, and so on, and they are not listed again.
The connection relationship of the circuit configuration will be explained below.
Since the
Taking the first MOS transistor group as an example, the source of the PMOS transistor MP1.1 is connected to the source of the PMOS transistor MP2.1 as a signal input terminal; the drain electrode of the PMOS tube MP1.1 is respectively connected with the grid electrode of the PMOS tube MP2.1, one end of the capacitor C1, one end of the primary coil of the transformer T, the drain electrode of the NMOS tube MN1.1 and the grid electrode of the NMOS tube MN 2.1; the grid electrode of the PMOS tube MP1.1 is respectively connected with the drain electrode of the PMOS tube MP2.1, the other end of the capacitor C1, the other end of the primary coil of the transformer T, the grid electrode of the NMOS tube MN1.1 and the drain electrode of the NMOS tube MN 2.1; the source electrode of the NMOS pipe MN1.1 is connected with the source electrode of the NMOS pipe MN2.1 and serves as a first grounding end.
The connection relationships of the MOS transistor groups of other groups are the same, and are not described in detail herein.
It should be noted that since the gate of each MOS transistor is provided with a switch, the gate of the MOS transistor connected to the
Meanwhile, the control signal of the control circuit 1 directly acts on each control switch to control the on/off of each control switch, and does not directly exchange data with the input signal of the
The control circuit may send N control signals, which are control signal 1,
This will be explained in detail below.
When control signal 1 is high and the other control signals are low, switches SP1.1, SP2.1, SN1.1 and SN2.1 are closed and the other switches are turned off. At this time, the PMOS transistor MP1.1, the PMOS transistor MP2.1, the NMOS transistor MN1.1, and the NMOS transistor MN2.1 in the
When
Similarly, when the control signal N is high and the other control signals are low, the oscillation circuit generates an oscillation signal with a frequency f 13. The switching sequence of the control signals 1-N can be implemented by specific programming.
When two or more control signals are high at the same time, the PMOS tube or the NMOS tube at the same position are connected in parallel and then are used as the MOS tube of the oscillation circuit together. For example, when the control signal 1 and the
It should be understood that the control signal may be considered high above a reference voltage value and low below that value by setting the reference voltage value.
The demodulation circuit 4 adopts a full-bridge rectification circuit, the
The cathode of the diode D1 is connected to the cathode of the diode D3, one end of the resistor R1 and one end of the capacitor C2, respectively, and the other end of the resistor R1 is connected to one end of the capacitor C3 and the base of the
The anode of the diode D2 is connected to the anode of the diode D4, the other end of the capacitor C2, the other end of the capacitor C3, and the emitter of the
The collector of
By connecting the resistor R1 between the capacitor C2 and the capacitor C3, the resistor R can serve not only as a filter resistor but also limit the current value of the base of the
Preferably, the linearity of the output signal can also be improved by connecting a resistor to the emitter of the
In the example of the isolator of fig. 5, it comprises: control circuit 1,
The
The grid of each MOS transistor is provided with a control switch, the 1 st MOS transistor group comprises a control switch SN1.1 and a control switch SN2.1, the control switch SN1.1 controls an NMOS transistor MN1.1, and the control switch SN2.1 controls an NMOS transistor MN 2.1.
Similarly, the nth MOS transistor group includes a control switch sn1.N and a control switch sn2.N, where the control switch sn1.N controls the NMOS transistor mn1.N and the control switch sn2.N controls the NMOS transistor mn2. N.
It should be noted that the NMOS transistor MN1.1 represents the 1 st NMOS transistor in the 1 st MOS transistor group, the NMOS transistor MN2.1 represents the 2 nd NMOS transistor in the 1 st MOS transistor group, and so on, which is not listed again.
The connection relationship of the circuit configuration will be explained below.
It should be noted that, since the
Taking the first MOS transistor group as an example, the drain of the NMOS transistor MN1.1 is connected to the gate of the NMOS transistor MN2.1, one end of the capacitor C1, and one end of the primary coil of the transformer T, respectively; the grid electrode of the NMOS tube MN1.1 is respectively connected with the drain electrode of the NMOS tube MN2.1, the other end of the capacitor C1 and the other end of the primary coil of the transformer T; the source electrode of the NMOS transistor MN1.1 is connected with the source electrode of the NMOS transistor MN2.1 and is used as a first grounding end
The connection relationships of the MOS transistor groups of other groups are the same, and are not described in detail herein.
It should be noted that since the gate of each MOS transistor is provided with a switch, the gate of the MOS transistor connected to the
Meanwhile, the control signal of the control circuit 1 directly acts on each control switch to control the on/off of each control switch, and does not directly exchange data with the input signal of the
The control circuit can send out N control signals, which are respectively control signal 1,
This will be explained in detail below.
When the control signal 1 is high and the other control signals are low, the control switch SN1.1 and the control switch SN2.1 are closed, the other switches are opened, the NMOS transistor MN1.1 and the NMOS transistor MN2.1 become MOS transistors of the
When the
The same is true. When the control signal N is high and the other control signals are low, the
When two or more control signals are high at the same time, the corresponding NMOS transistors are connected in parallel and then are used as the MOS transistors of the
It should be understood that the control signal may be considered high above a reference voltage value and low below that value by setting the reference voltage value.
The demodulation circuit 4 adopts a full-bridge rectification circuit, the
The cathode of the diode D1 is connected to the cathode of the diode D3, one end of the resistor R1 and one end of the capacitor C2, respectively, and the other end of the resistor R1 is connected to one end of the capacitor C3 and the base of the
The anode of the diode D2 is connected to the anode of the diode D4, the other end of the capacitor C2, the other end of the capacitor C3, and the emitter of the
The collector of
By connecting the resistor R1 between the capacitor C2 and the capacitor C3, the resistor R can serve not only as a filter resistor but also limit the current value of the base of the
Preferably, the linearity of the output signal can also be improved by connecting a resistor to the emitter of the
In the example of the isolator of fig. 6, it comprises: control circuit 1,
The
The grid of each MOS transistor is provided with a control switch, the 1 st MOS transistor group comprises a control switch SP1.1, a control switch SP2.1, a control switch SN1.1 and a control switch SN2.1, the control switch SP1.1 controls a PMOS transistor MP1.1, the control switch SP2.1 controls the PMOS transistor MP2.1, the control switch SN1.1 controls an NMOS transistor MN1.1, and the control switch SN2.1 controls the NMOS transistor MN 2.1.
Similarly, the nth MOS transistor group includes a control switch sp1.N, a control switch sp2.N, a control switch sn1.N, and a control switch sn2.N, where the control switch sp1.N controls the PMOS transistor mp1.N, the control switch sp2.N controls the PMOS transistor mp2.N, the control switch sn1.N controls the NMOS transistor mn1.N, and the control switch sn2.N controls the NMOS transistor mn2. N.
It should be noted that the PMOS transistor MP1.1 represents the 1 st PMOS transistor in the 1 st MOS transistor group, the PMOS transistor MP2.1 represents the 2 nd PMOS transistor in the 1 st MOS transistor group, and similarly, the NMOS transistor MN1.1 represents the 1 st NMOS transistor in the 1 st MOS transistor group, and the NMOS transistor MN2.1 represents the 2 nd NMOS transistor in the 1 st MOS transistor group, and so on, and they are not listed again.
The connection relationship of the circuit configuration will be explained below.
Taking the first MOS transistor group as an example, the source of the PMOS transistor MP1.1 is connected to the source of the PMOS transistor MP2.1 as a signal input terminal; the drain electrode of the PMOS tube MP1.1 is respectively connected with the grid electrode of the PMOS tube MP2.1, one end of the capacitor C1, one end of the inductor L, the drain electrode of the NMOS tube MN1.1 and the grid electrode of the NMOS tube MN 2.1; the grid electrode of the PMOS tube MP1.1 is respectively connected with the drain electrode of the PMOS tube MP2.1, the other end of the capacitor C1, the other end of the inductor L, the grid electrode of the NMOS tube MN1.1 and the drain electrode of the NMOS tube MN 2.1; the source electrode of the NMOS pipe MN1.1 is connected with the source electrode of the NMOS pipe MN2.1 and serves as a first grounding end.
The
The connection relationships of the MOS transistor groups of other groups are the same, and are not described in detail herein.
It should be noted that since the gate of each MOS transistor is provided with a switch, the gate of the MOS transistor connected to the
Meanwhile, the control signal of the control circuit 1 directly acts on each control switch to control the on/off of each control switch, and does not directly exchange data with the input signal of the
The control circuit may send N control signals, which are control signal 1,
This will be explained in detail below.
When control signal 1 is high and the other control signals are low, switches SP1.1, SP2.1, SN1.1 and SN2.1 are closed and the other switches are turned off. At this time, the PMOS transistor MP1.1, the PMOS transistor MP2.1, the NMOS transistor MN1.1, and the NMOS transistor MN2.1 in the
When
Similarly, when the control signal N is high and the other control signals are low, the oscillation circuit generates an oscillation signal with a frequency f 33. The switching sequence of the control signals 1-N can be implemented by specific programming.
When two or more control signals are high at the same time, the PMOS tube or the NMOS tube at the same position are connected in parallel and then are used as the MOS tube of the oscillation circuit together. For example, when the control signal 1 and the
It should be understood that the control signal may be considered high above a reference voltage value and low below that value by setting the reference voltage value.
The demodulation circuit 4 adopts a full-bridge rectification circuit, the
The cathode of the diode D1 is connected to the cathode of the diode D3, one end of the resistor R1 and one end of the capacitor C2, respectively, and the other end of the resistor R1 is connected to one end of the capacitor C3 and the base of the
The anode of the diode D2 is connected to the anode of the diode D4, the other end of the capacitor C2, the other end of the capacitor C3, and the emitter of the
The collector of
By connecting the resistor R1 between the capacitor C2 and the capacitor C3, the resistor R can serve not only as a filter resistor but also limit the current value of the base of the
Preferably, the linearity of the output signal can also be improved by connecting a resistor to the emitter of the
In the example of the isolator of fig. 7, it comprises: control circuit 1,
The
The inductor L adopts a center tap structure, and the center end is used as a signal input end.
The grid of each MOS transistor is provided with a control switch, the 1 st MOS transistor group comprises a control switch SN1.1 and a control switch SN2.1, the control switch SN1.1 controls an NMOS transistor MN1.1, and the control switch SN2.1 controls an NMOS transistor MN 2.1.
Similarly, the nth MOS transistor group includes a control switch sn1.N and a control switch sn2.N, where the control switch sn1.N controls the NMOS transistor mn1.N and the control switch sn2.N controls the NMOS transistor mn2. N.
It should be noted that the NMOS transistor MN1.1 represents the 1 st NMOS transistor in the 1 st MOS transistor group, the NMOS transistor MN2.1 represents the 2 nd NMOS transistor in the 1 st MOS transistor group, and so on, which is not listed again.
The connection relationship of the circuit configuration will be explained below.
Taking the first MOS transistor group as an example, the drain of the NMOS transistor MN1.1 is connected to the gate of the NMOS transistor MN2.1, one end of the capacitor C1, and one end of the inductor L, respectively; the grid electrode of the NMOS tube MN1.1 is respectively connected with the drain electrode of the NMOS tube MN2.1, the other end of the capacitor C1 and the other end of the inductor L; the source electrode of the NMOS transistor MN1.1 is connected with the source electrode of the NMOS transistor MN2.1 and serves as a first grounding end.
The
The connection relationships of the MOS transistor groups of other groups are the same, and are not described in detail herein.
It should be noted that since the gate of each MOS transistor is provided with a switch, the gate of the MOS transistor connected to the
Meanwhile, the control signal of the control circuit 1 directly acts on each control switch to control the on/off of each control switch, and does not directly exchange data with the input signal of the
The control circuit can send out N control signals, which are respectively control signal 1,
This will be explained in detail below.
When the control signal 1 is high and the other control signals are low, the control switch SN1.1 and the control switch SN2.1 are closed, the other switches are opened, the NMOS transistor MN1.1 and the NMOS transistor MN2.1 become MOS transistors of the
When the
The same is true. When the control signal N is high and the other control signals are low, the
When two or more control signals are high at the same time, the corresponding NMOS transistors are connected in parallel and then are used as the MOS transistors of the
It should be understood that the control signal may be considered high above a reference voltage value and low below that value by setting the reference voltage value.
The demodulation circuit 4 adopts a full-bridge rectification circuit, the
The cathode of the diode D1 is connected to the cathode of the diode D3, one end of the resistor R1 and one end of the capacitor C2, respectively, and the other end of the resistor R1 is connected to one end of the capacitor C3 and the base of the
The anode of the diode D2 is connected to the anode of the diode D4, the other end of the capacitor C2, the other end of the capacitor C3, and the emitter of the
The collector of
By connecting the resistor R1 between the capacitor C2 and the capacitor C3, the resistor R can serve not only as a filter resistor but also limit the current value of the base of the
Preferably, the linearity of the output signal can also be improved by connecting a resistor to the emitter of the
Optionally, in some embodiments, the transformer T
As shown in fig. 8, an exemplary cascaded transformer structure is provided, in which a primary coil of the transformer is connected to the
As shown in fig. 9, an exemplary cascaded capacitor structure is shown, where the left side of the capacitor shows the inductance of the
It is understood that some or all of the alternative embodiments described above may be included in some embodiments.
As shown in fig. 10, a schematic diagram of a chip package structure provided for an embodiment of a package according to the present invention includes: a
the
the
The
Preferably, a diode and a resistor may be connected in series between the signal input terminal and the oscillation circuit, the diode is used for protecting the circuit, the resistor is used for limiting a current value of the input signal, and a capacitor may be connected in parallel between the signal input terminal and the first ground terminal for voltage stabilization.
Preferably, a resistor is also connected in series with the emitter of the triode, so that the linearity of the output signal can be improved.
The isolator is manufactured by adopting an integrated circuit process, and compared with a linear or nonlinear optical coupler, the isolator has the advantages of small chip area, high reliability and the like.
In other embodiments of the present invention, there is also provided an electronic device including the isolator as described in any of the above embodiments.
It is to be understood that electronic equipment refers to military electronic systems, aerospace electronic equipment, medical equipment, etc. incorporating the isolator described in any of the various embodiments above.
The reader should understand that in the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, a circuit may be divided into only one logic function, and may be actually implemented in another way, for example, a plurality of electronic components may be combined or may be integrated into another circuit.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
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