阅读说明：本技术 半导体装置的制造方法及扩展带 (Method for manufacturing semiconductor device and extension tape ) 是由 本田一尊 铃木直也 乃万裕一 于 2018-05-18 设计创作，主要内容包括：本发明提供一种扩展带(1),其为在半导体装置的制造方法中使用的扩展带(1),所述半导体装置的制造方法具备带扩展工序,该带扩展工序中,通过对扩展带(1)一边加热一边进行拉伸,从而将固定在扩展带(1)上的、被制成单片的半导体芯片(2)的间隔从100μm以下扩大至300μm以上,其中,所述扩展带在所述带扩展工序的加热温度下的拉伸应力为10MPa以下,并且室温下的拉伸应力比所述加热温度下的拉伸应力高5MPa以上。(The present invention provides an expansion tape (1) used in a method for manufacturing a semiconductor device, the method for manufacturing the semiconductor device comprising a tape expansion step of expanding an interval between semiconductor chips (2) which are fixed to the expansion tape (1) and are formed into a single piece, from 100 [ mu ] m or less to 300 [ mu ] m or more by stretching the expansion tape (1) while heating the tape, wherein a tensile stress of the expansion tape at a heating temperature in the tape expansion step is 10MPa or less, and a tensile stress at room temperature is higher than the tensile stress at the heating temperature by 5MPa or more.)

1. A spread tape used in a method for manufacturing a semiconductor device, the method comprising a tape spreading step of heating and stretching the spread tape to spread the pitch of semiconductor chips fixed to the spread tape and formed into individual pieces from 100 μm or less to 300 μm or more,

wherein the stretched tape has a tensile stress at a heating temperature in the tape stretching step of 10MPa or less, and a tensile stress at room temperature of 5MPa or more higher than the tensile stress at the heating temperature.

2. The extension tape according to claim 1, wherein the method for manufacturing a semiconductor device further comprises:

a tension maintaining step of maintaining the tension of the stretched extension tape;

a transfer step of transferring the semiconductor chip on the spread tape held in tension to a carrier; and

and a peeling step of peeling the extension tape from the semiconductor chip transferred to the carrier.

3. The extension tape according to claim 1 or 2, which has a base material layer and an adhesive layer.

4. The extension tape according to claim 3, wherein the adhesive layer is composed of an ultraviolet-curable adhesive.

5. A method for manufacturing a semiconductor device, comprising a tape expanding step of expanding the interval between semiconductor chips individually fixed to an expanded tape of any one of claims 1 to 4 from 100 μm or less to 300 μm or more by stretching the tape while heating the tape.

6. A method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, comprising:

a 1A step of preparing an expansion tape and a plurality of semiconductor chips in which a surface opposite to the circuit surface is fixed to the expansion tape;

a 2A step of stretching the extension tape to expand the intervals between the plurality of semiconductor chips fixed to the extension tape;

a 3A step of maintaining the tension of the stretched extension tape;

a 4A step of transferring the plurality of semiconductor chips onto a carrier so that the circuit surface is fixed to the carrier;

a 5A step of peeling the extension tape from the plurality of semiconductor chips;

a 6A step of sealing the plurality of semiconductor chips on the carrier with a sealing material; and

and a 7A step of peeling the carrier from the plurality of semiconductor chips sealed with the sealing material.

7. A method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, comprising:

a 1B step of preparing an expansion tape and a plurality of semiconductor chips having the circuit surfaces fixed to the expansion tape;

a 2B step of stretching the extension tape to increase the intervals between the plurality of semiconductor chips fixed to the extension tape;

a 3B step of maintaining the tension of the stretched extension tape;

a 4B step of transferring the plurality of semiconductor chips onto a carrier so that a surface opposite to the circuit surface is fixed to the carrier;

a 5B step of peeling the extension tape from the plurality of semiconductor chips; and

and a 6B step of sealing the plurality of semiconductor chips on the carrier with a sealing material.

8. A method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, comprising:

a 1C step of preparing an expansion tape and a plurality of semiconductor chips in which a surface opposite to the circuit surface is fixed to the expansion tape;

a 2C step of stretching the extension tape to increase the intervals between the plurality of semiconductor chips fixed to the extension tape;

a 3C step of maintaining the tension of the stretched extension tape;

a 4C step of transferring the plurality of semiconductor chips onto a carrier so that the circuit surface is fixed to the carrier;

a 5C step of peeling the extension tape from the plurality of semiconductor chips;

a 6C step of sealing the plurality of semiconductor chips on the carrier with a sealing material;

a 7C step of peeling the carrier from the plurality of semiconductor chips sealed with the sealing material; and

and an 8C step of singulating the plurality of semiconductor chips sealed with the sealing material into individual semiconductor chips to form a plurality of semiconductor packages.

9. A method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, comprising:

a 1D step of preparing an expansion tape and a plurality of semiconductor chips having circuit surfaces fixed to the expansion tape;

a 2D step of stretching the extension tape to expand the intervals between the plurality of semiconductor chips fixed to the extension tape;

a 3D step of maintaining the tension of the stretched extension tape;

a 4D step of transferring the plurality of semiconductor chips onto a carrier so that a surface opposite to the circuit surface is fixed to the carrier;

a 5D step of peeling the extension tape from the plurality of semiconductor chips;

a 6D step of sealing the plurality of semiconductor chips on the carrier with a sealing material;

a 7D step of polishing the sealing material to expose the gasket;

a 8D step of peeling the carrier from the plurality of semiconductor chips sealed with the sealing material; and

and a 9D step of singulating the plurality of semiconductor chips sealed with the sealing material into individual semiconductor chips to form a plurality of semiconductor packages.

Technical Field

The invention relates to a method for manufacturing a semiconductor device and an extension tape.

Background

In recent years, with the miniaturization, high functionality, and high integration of semiconductor devices, the number of pins of semiconductors has increased, the density of semiconductors has increased, and the pitch of wirings has been narrowed. Therefore, it is desired to apply a technology for improving reliability by applying a fragile layer such as a low-K layer for the purpose of miniaturization of pins and wirings and lowering a dielectric constant.

Under such circumstances, Wafer Level Package (WLP) technology has been developed that can achieve high reliability, high productivity, and the like.

WLP technology is characterized in that assembly is performed in a wafer state, and the wafer is made into individual pieces by dicing in its final process. Since the wafer level packaging (sealing) is performed at the same time, it is a technique that can achieve high productivity and high reliability.

In the WLP technique, a rewiring layer in which a rewiring pattern is formed of polyimide, copper wiring, or the like is formed on an insulating film on a circuit surface of a semiconductor chip, and a metal pad, solder ball, or the like is mounted on the rewiring to form a connection terminal bump.

Among WLPs, a semiconductor Package having a Package area equivalent to that of a semiconductor Chip, such as a WLCSP (Wafer Level Chip Scale Package) or an FI-WLP (Fan In Wafer Level Package); and a semiconductor Package such as FO-WLP (Fan Out Wafer Level Package) which has a larger Package area than the semiconductor chip area and can extend terminals to the outside of the chip. Since such a semiconductor package is rapidly miniaturized and thinned, in order to ensure reliability, a periphery of a semiconductor chip is protected by sealing at a wafer level, and then a rewiring layer is formed, a package-by-package singulation, and the like are performed.

By performing such processes as sealing at the wafer level and then performing secondary mounting thereafter, reliability is ensured. In the field of mounting a single-function semiconductor such as a discrete semiconductor, in order to reduce cracks of a semiconductor chip or stress applied to a gasket peripheral portion at the time of handling, the periphery of the semiconductor chip is protected by sealing at the wafer level, and then, the semiconductor chip is diced into individual pieces one by one, and the process proceeds to the subsequent step (SMT process or the like). Discrete semiconductors are smaller than system LCIs in many cases, and sealing of 5 or 6 surfaces of a semiconductor chip is particularly required to protect the semiconductor chip to a higher degree.

However, in order to seal the side surfaces of the semiconductor chips, it is necessary to increase the intervals between the semiconductor chips after the semiconductor chips are fabricated by singulating the wafer. As a method for enlarging the pitch of semiconductor chips, a method including a rearrangement step of rearranging individual semiconductor chips obtained by dicing a semiconductor wafer on a carrier or the like has been proposed (for example, see non-patent document 1).

Disclosure of Invention

Technical problem to be solved by the invention

However, since the number of semiconductor chips per wafer is increased due to the miniaturization of the semiconductor chips, there is a problem that the time required for the rearrangement process of rearranging the semiconductor chips by using a chip mounter, flip chip bonding, or the like becomes long. Further, when die bonding in the rearrangement step is performed due to thinning of the semiconductor chip or the like, there is a possibility that damage may occur to the chip.

In view of the above circumstances, an object of the present invention is to provide a method for manufacturing a semiconductor device, which can be performed in a shorter time and causes less damage to chips than in a conventional process including a rearrangement step, and an extension tape applicable to the manufacturing method.

Means for solving the problems

As a result of intensive studies, the present inventors have found that the above-mentioned problems can be solved by the inventions described in the following [1] to [9 ].

[1] A spread tape used in a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising a tape spreading step of spreading a pitch of a singulated semiconductor chip fixed to the spread tape from 100 μm or less to 300 μm or more by stretching the spread tape while heating the tape, wherein a tensile stress at a heating temperature in the tape spreading step is 10MPa or less, and the tensile stress at room temperature is higher than the tensile stress at the heating temperature by 5MPa or more.

[2] The extended tape according to [1], wherein the method for manufacturing a semiconductor device further comprises:

a tension maintaining step of maintaining the tension of the stretched extension tape;

a transfer step of transferring the semiconductor chip on the tension-maintained spreading tape to a carrier; and

and a peeling step of peeling the spread tape from the semiconductor chip transferred to the carrier.

[3] The stretched tape according to [1] or [2], which comprises a base material layer and an adhesive layer.

[4] The expander according to [3], wherein the adhesive layer is formed of an ultraviolet-curable adhesive.

[5] A method for manufacturing a semiconductor device, comprising a tape expanding step of expanding the interval between semiconductor chips fixed to an expanded tape and formed into individual pieces from 100 μm or less to 300 μm or more by stretching the expanded tape according to any one of [1] to [4] while heating.

[6] A method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, comprising:

a 1A step of preparing an expansion tape and a plurality of semiconductor chips having a surface opposite to a circuit surface fixed to the expansion tape;

a 2A step of expanding the interval between the plurality of semiconductor chips fixed on the extension tape by stretching the extension tape;

a 3A step of maintaining the tension of the stretched tape;

a 4A step of transferring the plurality of semiconductor chips onto a carrier so that the circuit surface thereof is fixed to the carrier;

a 5A step of peeling the extension tape from the plurality of semiconductor chips;

a 6A step of sealing the plurality of semiconductor chips on the carrier with a sealing material; and

and a 7A step of peeling the carrier from the plurality of semiconductor chips sealed with the sealing material.

[7] A method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, comprising:

a 1B step of preparing an expansion tape and a plurality of semiconductor chips having circuit surfaces fixed to the expansion tape;

a 2B step of expanding the interval between the plurality of semiconductor chips fixed on the extension tape by stretching the extension tape;

a 3B step of maintaining the tension of the stretched tape;

a 4B step of transferring the plurality of semiconductor chips onto the carrier so that a surface opposite to the circuit surface is fixed to the carrier;

a 5B step of peeling the extension tape from the plurality of semiconductor chips; and

and a 6B step of sealing the plurality of semiconductor chips on the carrier with a sealing material.

[8] A method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, comprising:

a 1C step of preparing an expansion tape and a plurality of semiconductor chips having a surface opposite to a circuit surface fixed to the expansion tape;

a 2C step of expanding the interval between the plurality of semiconductor chips fixed on the extension tape by stretching the extension tape;

a 3C step of maintaining the tension of the stretched tape;

a 4C step of transferring the plurality of semiconductor chips onto a carrier so that the circuit surface is fixed to the carrier;

a 5C step of peeling the extension tape from the plurality of semiconductor chips;

a 6C step of sealing the plurality of semiconductor chips on the carrier with a sealing material;

a 7C step of peeling the carrier from the plurality of semiconductor chips sealed with the sealing material; and

and an 8C step of forming a plurality of semiconductor packages by singulating the plurality of semiconductor chips sealed with the sealing material into individual semiconductor chips.

[9] A method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, comprising:

a 1D step of preparing an expansion tape and a plurality of semiconductor chips having circuit surfaces fixed to the expansion tape;

a 2D step of expanding the interval between the plurality of semiconductor chips fixed on the extension tape by stretching the extension tape;

a 3D step of maintaining the tension of the stretched tape;

a 4D step of transferring the plurality of semiconductor chips onto the carrier so that a surface opposite to the circuit surface is fixed to the carrier;

a 5D step of peeling the extension tape from the plurality of semiconductor chips;

a 6D step of sealing the plurality of semiconductor chips on the carrier with a sealing material;

a 7D step of polishing the sealing material to expose the gasket;

a 8D step of peeling the carrier from the plurality of semiconductor chips sealed with the sealing material; and

and a 9D step of singulating the plurality of semiconductor chips sealed with the sealing material into individual semiconductor chips to form a plurality of semiconductor packages.

Effects of the invention

According to the present invention, a method for manufacturing a semiconductor device, which can be performed in a shorter time than a conventional process including a rearrangement step and causes less damage to a chip, and an extension tape applicable to the manufacturing method can be provided.

Drawings

Fig. 1 is a schematic cross-sectional view for explaining one embodiment of steps 1A to 4A in the method for manufacturing the 1 st semiconductor device.

Fig. 2 is a schematic cross-sectional view for explaining one embodiment of the 5 th to 7 th steps in the method for manufacturing the 1 st semiconductor device.

Fig. 3 is a schematic cross-sectional view for explaining one embodiment of the 8 th step and the 9 th step in the method for manufacturing the 1 st semiconductor device.

Fig. 4 is a schematic cross-sectional view for explaining one embodiment of the 1B to 4B steps in the method for manufacturing the 2 nd semiconductor device.

Fig. 5 is a schematic cross-sectional view for explaining one embodiment of the 5B th to 8B th steps in the method for manufacturing the 2 nd semiconductor device.

Fig. 6 is a schematic cross-sectional view for explaining another embodiment of the 7B th step and the 8B th step in the method for manufacturing the 2 nd semiconductor device.

Fig. 7 is a schematic cross-sectional view for explaining one embodiment of the 9B th step and the 10B th step in the method for manufacturing the 2 nd semiconductor device.

Fig. 8 is a schematic cross-sectional view for explaining one embodiment of the 1C st step to the 4C th step in the method for manufacturing the 3 rd semiconductor device.

Fig. 9 is a schematic cross-sectional view for explaining one embodiment of the 5 th to 8 th steps in the method for manufacturing the 3 rd semiconductor device.

Fig. 10 is a schematic cross-sectional view for explaining another embodiment of the 4 th to 8 th steps in the method for manufacturing the 3 rd semiconductor device.

Fig. 11 is a schematic cross-sectional view for explaining one embodiment of the 1D step to the 4D step in the method for manufacturing the 4 th semiconductor device.

Fig. 12 is a schematic cross-sectional view for explaining one embodiment of the 5D step to the 9D step in the method for manufacturing the 4 th semiconductor device.

Fig. 13 is a schematic cross-sectional view for explaining another embodiment of the 7D step and the 8D step in the method for manufacturing the 4 th semiconductor device.

Fig. 14 is a schematic cross-sectional view for explaining one embodiment of a method for manufacturing a 5 th semiconductor device.

Fig. 15 is a schematic cross-sectional view for explaining another embodiment of the method for manufacturing the 5 th semiconductor device.

Detailed Description

The present embodiment will be described in detail below with reference to the drawings. In the following description, the same or corresponding portions are denoted by the same reference numerals, and redundant description thereof is omitted. The positional relationship such as up, down, left, right, and the like is based on the positional relationship shown in the drawings, unless otherwise specified. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

(method of manufacturing semiconductor device)

[ method for manufacturing a semiconductor device ] 1

The method for manufacturing a semiconductor device according to embodiment 1 is a method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, and includes the steps of:

a 1A step of preparing an expansion tape and a plurality of semiconductor chips having a surface opposite to a circuit surface fixed to the expansion tape;

a 2A step of expanding the interval between the plurality of semiconductor chips fixed on the extension tape by stretching the extension tape;

a 3A step of maintaining the tension of the stretched tape;

a 4A step of transferring the plurality of semiconductor chips onto a carrier so that the circuit surface thereof is fixed to the carrier;

a 5A step of peeling the extension tape from the plurality of semiconductor chips;

a 6A step of sealing the plurality of semiconductor chips on the carrier with a sealing material;

a 7A step of peeling the carrier from the plurality of semiconductor chips sealed with the sealing material;

a 8A step of forming a rewiring layer having a rewiring pattern by a pad of the plurality of semiconductor chips sealed with the sealing material, and providing a connection terminal pad connected to the semiconductor chip through the rewiring pattern outside the semiconductor chip region; and

and a 9A step of forming a plurality of semiconductor packages by singulating the semiconductor chips and the connection terminal pads connected thereto as a set.

According to the method of manufacturing the 1 st semiconductor device of the present embodiment, a semiconductor package (FO-WLP) having a package area larger than that of a semiconductor chip and capable of expanding terminals to the outside of the chip can be manufactured.

FO-WLP is also used for applications having a larger number of terminals than the chip area, and therefore, is being developed. In flip chip BGA in which a semiconductor chip is connected to a package substrate by solder bumps or the like and solder balls are mounted on the package substrate, FO-WLP is connected from the semiconductor chip to a rewiring layer, and metal pads (connection terminals) are provided on the rewiring layer and the solder balls are mounted thereon. Therefore, FO-WLP contributes to miniaturization and thinning of packages, and further, since the wiring length is shortened, high-speed transfer (high-performance) and cost reduction due to no package substrate become possible.

In FO-WLP, in order to fabricate connection terminal pads outside semiconductor chips through a rewiring layer after dicing a semiconductor wafer, the pitch of the semiconductor chips needs to be increased. As a method for enlarging the pitch of semiconductor chips, a method including a rearrangement step of rearranging individual semiconductor chips obtained by dicing a conventional semiconductor wafer on a carrier or the like has been proposed (for example, see non-patent document 1).

However, since the number of semiconductor chips per wafer is increased due to the miniaturization of the semiconductor chips, there is a problem that a long time is required for a rearrangement step of rearranging the semiconductor chips by using a chip mounter, flip chip bonding, or the like. Further, due to thinning of the semiconductor chip, there is a possibility that damage may occur to the chip when the chip is mounted in the rearrangement step. In contrast, according to the method for manufacturing the semiconductor device of embodiment 1, these problems can be solved.

The above-described 1A to 9A steps will be described below with reference to fig. 1 to 3. Fig. 1 is a schematic cross-sectional view for explaining one embodiment of the 1 st to 4 th steps, fig. 2 is a schematic cross-sectional view for explaining one embodiment of the 5 th to 7 th steps, and fig. 3 is a schematic cross-sectional view for explaining one embodiment of the 8 th and 9 th steps.

First, in the step 1A, an extension tape 1 and a plurality of semiconductor chips 2 fixed to the extension tape 1 are prepared. The extension tape 1 has an adhesive layer 1a and a base material film 1b, and the adhesive layer 1a is in contact with the semiconductor chip 2. The semiconductor chip 2 has a circuit surface provided with a pad (circuit) 3, and the surface opposite to the circuit surface is fixed to the extension tape 1 (fig. 1 (a)). The plurality of semiconductor chips 2 are arranged at intervals.

In the step 2A, the spread tape 1 is stretched to widen the interval between the plurality of semiconductor chips 2 fixed to the spread tape 1 (fig. 1 (b)).

In the step 3A, the stretched extension tape 1 is fixed by using the fixing jig 4, and the tension of the extension tape 1 is maintained (fig. 1 (c)).

In the 4A step, the plurality of semiconductor chips 2 are transferred onto the carrier 5 so that the circuit surface is fixed to the carrier (fig. 1 d). In the transfer, the pad 3 may be embedded in the carrier 5 (fig. 1 d), or only the pad 3 may be in contact with the carrier 5, and a gap (not shown) may be present between the circuit surface of the semiconductor chip 2 and the carrier 5.

In the 5A step, the extension tape 1 is peeled from the plurality of semiconductor chips 2 (fig. 2 a).

In the 6A step, the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6 (fig. 2 (b)). When the gasket 3 is embedded in the carrier 5 and the circuit surface of the semiconductor chip 2 is in contact with the carrier 5, the total of 5 surfaces of the surface of the semiconductor chip opposite to the circuit surface and 4 side surfaces is sealed without sealing the circuit surface (fig. 2 (b)). On the other hand, if there is a sufficient gap between the circuit surface of the semiconductor chip 2 and the carrier 5 to allow the sealing material 6 to flow, the circuit surface is also sealed, and the entire 6 surfaces of the semiconductor chip are sealed (not shown).

In the 7A step, the carrier 5 is peeled off from the plurality of semiconductor chips 2 sealed with the sealing material 6 (fig. 2 c).

Fig. 3(a) is an enlarged view of fig. 2 (c).

In the 8A step, a rewiring layer 8 having a rewiring pattern 7 is formed from the pads 3 of the plurality of semiconductor chips 2 sealed with the sealing material 6, and a connection terminal pad 9 connected to the semiconductor chip 2 through the rewiring pattern 7 is provided outside the region of the semiconductor chip 2 (fig. 3 (b)).

In the 9A step, the semiconductor chip 2 and the connection terminal pads 9 connected thereto are singulated as a set to form a plurality of semiconductor packages 10 (fig. 3 c).

Hereinafter, each step will be described in detail.

< step 1A >

The method of preparing the spreading tape and the plurality of semiconductor chips fixed on the spreading tape is not particularly limited. For example, a semiconductor wafer may be laminated on a dicing tape or the like, and then diced by a blade or a laser to obtain a plurality of semiconductor chips which are made into a single piece, and then transferred to an expansion tape to be manufactured.

The cutting may be performed by forming a fragile layer by laser and expanding the fragile layer. In addition, from the viewpoint of omitting the transfer and improving productivity, the semiconductor wafer may be produced by directly laminating the semiconductor wafer on an expansion tape and dicing the semiconductor wafer by the above-described method.

From the viewpoint of improving productivity and reducing cost, the initial semiconductor chip pitch (the pitch of the semiconductor chips before the 2A step) is preferably narrow, and is preferably 100 μm or less, more preferably 80 μm or less, and still more preferably 60 μm or less. The cutting of the wafer by dicing is preferably narrow as described above from the viewpoint of cost reduction because the wider the chip pitch is, the more the semiconductor wafer is wasted. When the chip pitch is enlarged, the pitch of the initial semiconductor chips is preferably 10 μm or more so as not to apply stress to the semiconductor chips. When the thickness is less than 10 μm, the expansion band region between the plurality of semiconductor chips is small, and therefore, it is difficult to expand the size.

The type of the pad on the circuit surface of the semiconductor chip is not particularly limited as long as it can be formed on the circuit surface of the semiconductor chip, and may be a bump (protruding electrode) such as a copper bump or a solder bump, or a relatively flat metal pad such as a Ni/Au plated pad.

< step 2A >

The space between the plurality of semiconductor chips is expanded by stretching the extension tape.

Examples of the stretching method of the extension tape include a jack-up method and a stretching method. The jack-up method is a method in which after an extension band is fixed, the extension band is extended by raising a table having a predetermined shape. The stretching method is as follows: after the extension tape is fixed, the extension tape is stretched in a predetermined direction parallel to the surface of the extension tape to be set, whereby the extension tape is stretched. The lift-up method is preferable in terms of uniformly extending the intervals of the semiconductor chips and in terms of small and compact required (occupied) device area.

The stretching conditions may be appropriately set according to the properties of the stretched tape. For example, the jack-up amount (stretch amount) in the jack-up method is preferably 10mm to 500mm, more preferably 10mm to 300 mm. When the thickness is 10mm or more, the spacing between the plurality of semiconductor chips is easily increased, and when the thickness is 500mm or less, the semiconductor chips are less likely to be scattered or displaced.

The temperature may be set as appropriate depending on the characteristics of the extension tape, and may be, for example, 10 to 200 ℃, 10 to 150 ℃, or 20 to 100 ℃. When the temperature is 10 ℃ or higher, the expandable tape is easily stretched, and when the temperature is 200 ℃ or lower, it is difficult to cause deformation due to thermal expansion or low elasticity of the expandable tape, or positional deviation of the semiconductor chip (peeling between the expandable tape and the semiconductor chip) due to relaxation, or scattering of the semiconductor chip.

The ejecting speed may be set as appropriate depending on the characteristics of the extension tape, and may be, for example, 0.1 mm/sec to 500 mm/sec, 0.1 mm/sec to 300 mm/sec, or 0.1 mm/sec to 200 mm/sec. When the thickness is 0.1 mm/sec or more, productivity is improved. When the thickness is 500 mm/sec or less, peeling between the semiconductor chip and the extension tape is less likely to occur.

The interval between the plurality of semiconductor chips after the step 2A is preferably 500 μm or more in order to secure a space necessary for providing the rewiring pattern and the connection terminal pad outside the region of the semiconductor chip. In a semiconductor package having a higher density and higher functionality, the total number of rewiring layers is also increased, and therefore, it is necessary to provide a connection terminal pad on the outer side of the semiconductor chip. Therefore, the semiconductor chip pitch is preferably wide. From the above viewpoint, the interval between the plurality of semiconductor chips after the 2A step is preferably 1mm or more, and more preferably 2mm or more. The upper limit is not particularly limited, and may be 5mm or less.

< step 3A >

In order to prevent the stretched extension tape from returning to its original state, the tension of the extension tape is maintained.

The method of holding the tension of the spread tape is not particularly limited as long as the tension is held and the pitch of the semiconductor chips does not return to the original value. Examples thereof include a method of fixing with a fixing jig such as a clamp ring (produced by TECHNOLVISION); and a method of heating and shrinking (heat shrinking) the outer periphery of the extension tape to maintain tension.

< step 4A >

A plurality of semiconductor chips are transferred (laminated) onto a carrier in such a manner that the circuit surface is fixed on the carrier. The laminating method is not particularly limited, and a roll laminator, a diaphragm laminator, a vacuum roll laminator, a vacuum diaphragm laminator, or the like can be used.

The lamination conditions may be appropriately set depending on the physical properties and characteristics of the spreading tape, the semiconductor chip, and the carrier. For example, in the case of a roll laminator, the temperature may be from room temperature (25 ℃) to 200 ℃, preferably from room temperature (25 ℃) to 150 ℃, and more preferably from room temperature (25 ℃) to 100 ℃. When the temperature is at room temperature or higher, the semiconductor chip is easily transferred (laminated) onto the carrier, and when the temperature is at 200 ℃ or lower, the semiconductor chip is less likely to be displaced (peeled off between the expansion tape and the semiconductor chip) or scattered due to the position deviation of the semiconductor chip (peeling between the expansion tape and the semiconductor chip) or relaxation caused by thermal expansion or low elasticity of the expansion tape. In the case of a diaphragm laminator, the temperature conditions are the same as those in the roll laminator described above. The pressure-bonding time may be 5 seconds to 300 seconds, preferably 5 seconds to 200 seconds, and more preferably 5 seconds to 100 seconds. When the time is 5 seconds or more, the semiconductor chip is easily transferred (laminated) onto the carrier, and when it is 300 seconds or less, the productivity is improved. The pressure may be 0.1MPa to 3MPa, preferably 0.1MPa to 2MPa, and more preferably 0.1MPa to 1 MPa. When the pressure is 0.1MPa or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when the pressure is 2MPa or less, damage to the semiconductor chip can be reduced.

< step 5A >

The extension tape is peeled (removed) from the plurality of semiconductor chips.

When peeling the spread tape, it is necessary to appropriately set the adhesion force between the spread tape and the carrier, between the spread tape and the semiconductor chip, and between the semiconductor chip and the carrier so that the semiconductor chip transferred onto the carrier does not shift in position or peel off from the carrier. For example, the adhesion force of the expansion band to the semiconductor chip is preferably equal to or smaller than the adhesion force of the semiconductor chip to the carrier.

The spread tape or the support surface may be provided with a UV curing function, and the adhesion force (adhesive force) may be changed up or down by UV irradiation. In this case, the extension tape is removed after UV irradiation (additional UV irradiation step). For example, after the step 3A, UV irradiation is performed to reduce the adhesion force (adhesive force) of the spread tape, and then the spread tape may be laminated on the carrier and peeled off from the semiconductor chip. This makes it possible to reduce stress on the semiconductor chip and to smoothly transfer the semiconductor chip without causing positional deviation.

< step 6A >

The plurality of semiconductor chips on the carrier are sealed with a sealing material.

The sealing method is not particularly limited, and examples thereof include compression molding (the sealing material is in the form of a liquid material, a solid material, a particulate material, a film material, etc.), transfer molding (the sealing material is in the form of a liquid material, a solid material, a particulate material, a film material, etc.), lamination of a film-like sealing material, and the like.

After the 6A step, a heat treatment step including post-curing may be added from the viewpoint of adjusting the physical properties of the sealing material. After the step 6A or after the additional heat treatment step, the carrier needs to be peeled off. When the peeling is performed, a heating treatment, a UV treatment process, or the like may be added. After the above-described steps, it is necessary to set the adhesion force of the carrier (carrier + adhesive layer, carrier + temporary fixing material, etc.) so that the carrier is peeled off without damaging the semiconductor chip and the sealing material.

< step 7A >

The carrier is peeled off from the plurality of semiconductor chips sealed with the sealing material. Before the carrier is peeled off, the following steps may be introduced: by heat treatment or UV irradiation, a chemical or mechanical change is applied to the surface layer of the carrier in contact with the sealing material side, so that the carrier is easily peeled off.

In the 4A to 7A steps, the semiconductor chip is transferred from the spreading tape to the carrier, whereby the risk of heat resistance in a heating step such as a sealing step can be reduced. For example, when the sealing is performed in a state where the semiconductor chip is present on the expansion tape (without using a carrier), there is a possibility that the semiconductor chip may be misaligned or scattered due to deformation of the expansion tape having stretchability, deformation due to thermal expansion, or the like. When the misalignment or the chip scattering occurs, the productivity is lowered and the cost is increased, and therefore, the semiconductor chip needs to be transferred to a carrier.

< step 8A >

A rewiring layer having a rewiring pattern is formed on a pad of a plurality of semiconductor chips sealed with a sealing material, and a connection terminal pad connected to the semiconductor chip through the rewiring pattern is provided outside the area of the semiconductor chip. In a semiconductor chip with higher density and higher functionality, a rewiring layer is formed due to a narrow terminal pitch, and a pad for a connection terminal is provided outside the region of the semiconductor chip, thereby enlarging a bump pitch (FO-WLP). This improves reliability such as reduction of stress applied to the bump, improvement of insulation, and improvement of connection reliability. This step can be performed by a conventionally known method.

< step 9A >

A plurality of semiconductor packages are formed by singulating the semiconductor chips and the connection terminal pads connected thereto as a set. When dicing is performed with the doctor blade, it is necessary to set the pitch of the semiconductor chips in the 2 nd process in consideration of the width of the doctor blade (the portion that is not to be cut). This step can be performed by a conventionally known method.

When the thickness of the semiconductor package is reduced for the purpose of downsizing and thinning, a back grinding step (a step of thinning the semiconductor chip by cutting off the sealing material on the back surface side of the circuit surface of the semiconductor chip) may be introduced. The back grinding step may be introduced after the 6th step, after the 7 th step, or after the 8 th step, for example.

Next, materials used in the respective steps will be described.

(extension band)

The spreading tape that can be used in the method for manufacturing the 1 st semiconductor device is not particularly limited as long as it has stretchability that can expand the interval between the plurality of semiconductor chips. Preferably, the chip pitch between MD and TD after the 2A step (after the semiconductor chip pitch is widened) is uniform, and when the semiconductor chip and the connection terminal pads connected thereto are singulated as a set after the 6A step (after sealing), the MD and TD may be non-uniform in width as long as the dicing can be performed without damaging the semiconductor chip (as long as the semiconductor chip is not damaged by the doctor blade). When cutting is performed, the cutting interval widths of MD and TD may be different. However, it is preferable that the MD lines and the TD lines are uniform.

The spreading tape may have a multi-layer structure such as a base film (base material layer) which greatly contributes to stretchability, an adhesive layer for controlling adhesion, and the like.

The substrate film is not particularly limited as long as it has stretchability and maintains the stability of the semiconductor chip pitch after the tension maintaining step (step 3A).

The substrate film may be a polyester film such as a polyethylene terephthalate film; a homopolymer of an α -olefin such as a polytetrafluoroethylene film, a polyethylene film, a polypropylene film, a polymethylpentene film, a polyvinyl acetate film, or a poly-4-methylpentene-1, a copolymer thereof, and a polyolefin film containing the homopolymer or an ionomer of the copolymer; a polyvinyl chloride film; and a polyimide film; various plastic films such as urethane resin films. The substrate film is not limited to a single-layer film, and may be a multilayer film obtained by combining 2 or more kinds of the above plastic films or 2 or more kinds of the same plastic films.

The substrate film is preferably a polyolefin film or a urethane resin film from the viewpoint of stretchability. The base film may contain various additives such as an antiblocking agent, if necessary.

The thickness of the base film may be appropriately set as needed, and is preferably 50 μm to 500 μm. When the thickness is less than 50 μm, the stretchability is lowered, and when the thickness is more than 500. mu.m, defects such as deformation and deterioration in handling property are liable to occur.

The thickness of the base film is appropriately selected within a range that does not impair the operability. However, when a high-energy-ray (particularly, ultraviolet-ray) -curable adhesive is used as the adhesive constituting the adhesive layer, the thickness thereof is required to be a thickness that does not inhibit the transmission of the high-energy-ray. From this viewpoint, the thickness of the base film may be usually 10 to 500. mu.m, preferably 50 to 400. mu.m, and more preferably 70 to 300. mu.m.

When the base material layer is formed of a plurality of base material films, the thickness of the entire base material layer is preferably adjusted to be within the above range. The base film may be subjected to chemical or physical surface treatment as necessary in order to improve adhesion to the adhesive layer. Examples of the surface treatment include corona treatment, chromic acid treatment, ozone exposure, flame exposure, high-voltage shock exposure, and ionizing radiation treatment.

The adhesive layer is not particularly limited as long as it can control the adhesive force (set so that the semiconductor chips are not positionally displaced or scattered in each step).

The adhesive layer is preferably composed of an adhesive component having an adhesive force at room temperature and an adhesive force to the semiconductor chip. Examples of the matrix resin constituting the adhesive component of the adhesive layer include acrylic resins, synthetic rubbers, natural rubbers, polyimide resins, and the like.

The matrix resin preferably has a functional group (hydroxyl group, carboxyl group, or the like) capable of reacting with other additives, from the viewpoint of reducing the residual gum of the binder component. As the binder component, a resin that is cured by high-energy rays such as ultraviolet rays and radiation, or by heat can be used. When such a curable resin is used, the adhesive force can be reduced by curing the resin. In addition, the adhesive component may further contain a crosslinking agent capable of crosslinking with the functional group of the matrix resin in order to adjust the adhesive strength. The crosslinking agent preferably has at least 1 functional group selected from an epoxy group, an isocyanate group, an aziridine group and a melamine group. These crosslinking agents may be used alone, or 2 or more kinds may be used in combination.

When the reaction rate is low, a catalyst such as amine or tin may be used as necessary. The pressure-sensitive adhesive component may further contain any optional component such as a tackifier such as a rosin-based resin or a terpene resin, and various surfactants, as appropriate, for the purpose of adjusting the pressure-sensitive adhesive properties.

The thickness of the adhesive layer is usually 1 to 100 μm, preferably 2 to 50 μm, and more preferably 5 to 40 μm. Since the adhesive layer has a thickness of 1 μm or more, sufficient adhesive force with the semiconductor chip can be secured, and therefore, scattering of the semiconductor chip can be easily suppressed in the step 2A (i.e., the semiconductor chip pitch is widened). On the other hand, even if the thickness exceeds 100 μm, there is no advantage in the characteristics, and it is uneconomical.

When the adhesive layer is 10 μm or more, the base film is not damaged (e.g., scratched) even when the semiconductor wafer is cut on the dicing tape without using the dicing tape, and therefore, in the step 1A, the step of transferring (attaching) the semiconductor wafer after the dicing tape is cut on the dicing tape to the expansion tape can be omitted.

(method of manufacturing expansion band)

The extension band may be manufactured according to techniques well known in the art. For example, the production can be carried out by the following method. A varnish containing a binder component and a solvent is applied to the protective film by a doctor blade coating method, a roll coating method, a spray coating method, a gravure coating method, a bar coating method, a curtain coating method, or the like, and the solvent is removed to form an adhesive layer. Specifically, the heating is preferably performed at 50 to 200 ℃ for 0.1 to 90 minutes. The condition under which the organic solvent is volatilized to 1.5% or less is preferable as long as it does not affect the generation of voids or the adjustment of viscosity in each step.

The produced protective film with the adhesive layer and the base film are laminated so that the adhesive layer and the base film face each other at a temperature of from room temperature to 60 ℃.

The spreading tape (base film or base film + adhesive layer) is used after the protective film is peeled off.

Examples of the protective Film include A-63 (modified silicone system as a release agent manufactured by Teijin Dupont Film Co., Ltd.), A-31 (Pt silicone system as a release agent manufactured by Teijin Dupont Film Co., Ltd.), and the like.

The thickness of the protective film is appropriately selected within a range that does not impair the workability, and is generally preferably 100 μm or less from the viewpoint of economy. The thickness of the protective film is preferably 10 to 75 μm, and more preferably 25 to 50 μm. When the thickness of the protective film is 10 μm or more, defects such as film cracking are not easily caused when the spreading tape is manufactured. When the thickness of the protective film is 75 μm or less, the protective film can be easily peeled off when the spreading tape is used.

(Carrier)

The carrier is not particularly limited as long as it can withstand the temperature and pressure at the time of transfer (chip breakage does not occur, chip pitch does not change), and also can withstand the temperature and pressure at the time of sealing in the 6A step. For example, when the sealing temperature is 100 to 200 ℃, it is preferable to have heat resistance capable of withstanding the temperature range. The thermal expansion coefficient is preferably 100 ppm/DEG C or less, more preferably 50 ppm/DEG C or less, and still more preferably 20 ppm/DEG C or less. When the thermal expansion coefficient is large, a defect such as a positional deviation of the semiconductor chip occurs. Further, since deformation or warpage occurs when the thermal expansion coefficient is smaller than that of the semiconductor chip, the thermal expansion coefficient is preferably 3 ppm/DEG C or more.

The material of the carrier is not particularly limited, and examples thereof include silicon (wafer), glass, SUS, iron, Cu, and other plates, glass epoxy substrates, and the like.

The thickness of the carrier may be 100 to 5000. mu.m, preferably 100 to 4000. mu.m, more preferably 100 to 3000. mu.m. When the particle size is 100 μm or more, the handling property is improved. However, even if the thickness is large, a significant improvement in handling property cannot be expected, and it is only necessary to be 5000 μm or less from the economical viewpoint.

The carrier may also be composed of a plurality of layers. From the viewpoint of imparting adhesion control, a layer in which an adhesive layer or a temporary fixing material is laminated in addition to the layer responsible for the heat resistance and handling property may be used. The adhesion force may be appropriately set in consideration of the adhesion force of the semiconductor chip or the extension tape. The thickness is also not particularly limited, and may be, for example, 1 to 300. mu.m, preferably 1 to 200. mu.m. By being 1 μm or more, sufficient adhesion to the semiconductor chip can be secured. On the other hand, even if the thickness exceeds 300. mu.m, there is no advantage in the characteristics, and it is uneconomical.

(sealing Material (Molding Material))

The sealing method is not particularly limited, and examples thereof include compression molding (the sealing material is in the form of a liquid material, a solid material, a particulate material, a film material, etc.), transfer molding (the sealing material is in the form of a liquid material, a solid material, a particulate material, a film material, etc.), lamination of a film-like sealing material, and the like.

The shape, properties and sealing conditions of the sealing material can be appropriately set for each of the above-described sealing methods. The shape, characteristics, and sealing conditions of the sealing material need to be appropriately set so that the semiconductor chip on the carrier does not move or peel off or damage the semiconductor chip at the time of sealing.

For example, the sealing temperature is preferably 80 to 220 ℃, more preferably 90 to 210 ℃, and still more preferably 100 to 200 ℃. When the sealing temperature is 80 ℃ or higher, the underfill around the semiconductor chip can be sufficiently suppressed. When the sealing temperature is 220 ℃ or lower, it is possible to prevent unfilled sealing due to too rapid curing of the sealing material, increase in the amount of warpage after sealing, and the like.

After the sealing step (step 6A), a heat treatment step including post-curing may be added from the viewpoint of adjusting the physical properties of the sealing material. The post-curing time is set to 100 to 200 ℃ for 10 minutes to 5 hours, depending on the curing properties of the sealing material. When a heat treatment step for suppressing warpage is required, the post-curing may be followed by a treatment for 10 minutes to 3 hours at a temperature (200 ℃ or lower) lower than that of the post-curing.

[ method for manufacturing a semiconductor device ] of the second embodiment

The method for manufacturing a 2 nd semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, and includes the steps of:

a 1B step of preparing an expansion tape and a plurality of semiconductor chips having circuit surfaces fixed to the expansion tape;

a 2B step of expanding the interval between the plurality of semiconductor chips fixed on the extension tape by stretching the extension tape;

a 3B step of maintaining the tension of the stretched tape;

a 4B step of transferring the plurality of semiconductor chips onto the carrier so that a surface opposite to the circuit surface is fixed to the carrier;

a 5B step of peeling the extension tape from the plurality of semiconductor chips;

a 6B step of sealing the plurality of semiconductor chips on the carrier with a sealing material;

a 7B step of polishing the sealing material to expose the gasket;

a 8B step of peeling the carrier from the plurality of semiconductor chips sealed with the sealing material;

a 9B step of forming a rewiring layer having a rewiring pattern from a pad of the plurality of semiconductor chips sealed with the sealing material, and providing a connection terminal pad connected to the semiconductor chip through the rewiring pattern outside the semiconductor chip region; and

and a 10B step of forming a plurality of semiconductor packages by singulating the semiconductor chips and the connection terminal pads connected thereto as a set.

According to the method of manufacturing the 2 nd semiconductor device of the present embodiment, it is possible to manufacture a semiconductor package (FO-WLP) having a package area larger than that of a semiconductor chip and capable of expanding terminals to the outside of the chip. According to the method for manufacturing the 2 nd semiconductor device of the present embodiment, the problems in the conventional method for manufacturing the FO-WLP can be solved, similarly to the method for manufacturing the 1 st semiconductor device of the present embodiment.

The 1B to 10B steps are described with reference to FIGS. 4 to 7. Fig. 4 is a schematic cross-sectional view for explaining one embodiment of the 1B to 4B steps, fig. 5 is a schematic cross-sectional view for explaining one embodiment of the 5B to 8B steps, fig. 6 is a schematic cross-sectional view for explaining another embodiment of the 7B and 8B steps, and fig. 7 is a schematic cross-sectional view for explaining one embodiment of the 9B and 10B steps.

First, in the 1B step, an extension tape 1 and a plurality of semiconductor chips 2 fixed to the extension tape 1 are prepared. The extension tape 1 has an adhesive layer 1a and a base material film 1b, and the adhesive layer 1a is in contact with the semiconductor chip 2. The semiconductor chip 2 has a circuit surface provided with a pad (circuit) 3, and the circuit surface is fixed to the extension tape 1 (fig. 4 a). The plurality of semiconductor chips 2 are arranged at intervals. In addition, the spacer 3 may be embedded in the extension band 1 when the fixing is performed.

In the step 2B, the spread tape 1 is stretched to widen the interval between the plurality of semiconductor chips 2 fixed to the spread tape 1 (fig. 4 (B)).

In the step 3B, the stretched extension tape 1 is fixed by using the fixing jig 4, and the tension of the extension tape 1 is maintained (fig. 4 (c)).

In the 4B step, the plurality of semiconductor chips 2 are transferred onto the carrier 5 so that the surface opposite to the circuit surface is fixed to the carrier 5 (fig. 4 d).

In the 5B step, the extension tape 1 is peeled off from the plurality of semiconductor chips 2 (fig. 5 a).

In the 6B step, the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6 (fig. 5B). At this time, since the surface of the semiconductor chip 2 opposite to the circuit surface is in contact with the carrier 5, the circuit surface and the total of 5 surfaces of the 4 side surfaces of the semiconductor chip 2 are sealed without sealing the surface.

In the 7B step, the sealing material 6 is polished to expose the gasket 3.

In the 8B step, the carrier 5 is peeled off from the plurality of semiconductor chips 2 sealed with the sealing material 6.

The order of the 7B step and the 8B step may be changed. That is, the carrier 5 may be peeled off from the plurality of semiconductor chips 2 sealed with the sealing material 6 (fig. 5 d) after the sealing material 6 is polished to expose the gasket 3 (fig. 5 c), or the carrier 5 may be peeled off from the plurality of semiconductor chips 2 sealed with the sealing material 6 (fig. 6 a) and then the sealing material 6 may be polished to expose the gasket 3 (fig. 6 b).

Fig. 7(a) is an enlarged view of fig. 5(d) or fig. 6 (b).

In the 9B step, a rewiring layer 8 having a rewiring pattern 7 is formed from the pads 3 of the plurality of semiconductor chips 2 sealed with the sealing material 6, and a connection terminal pad 9 connected to the semiconductor chip 2 through the rewiring pattern 7 is provided outside the region of the semiconductor chip 2 (fig. 7B).

In the 10B step, the semiconductor chip 2 and the connection terminal pads 9 connected thereto are singulated as a set to form a plurality of semiconductor packages 10 (fig. 7 c).

The 1B to 6B steps may be performed by the same method as the 1A to 6A steps, and the 8B to 10B steps may be performed by the same method as the 7B to 9B steps. In the 7B step, the sealing material is polished to expose the gasket. The polishing can be performed by using a conventionally known polishing apparatus or the like. In the case where the sealing can be achieved with the circuit surface pads exposed in step 6B, step 7B is not necessarily provided.

As the material used in each step, the same material as that used in the method for manufacturing the semiconductor device of the 1 st embodiment can be used, but the carrier 5 may be a material obtained by laminating a sealing material and a material capable of protecting a chip on a layer that is responsible for the heat resistance and the handling property by coating, spin coating, lamination, or the like, from the viewpoint of protecting the surface of the semiconductor chip on the opposite side to the circuit surface.

[3 rd method for manufacturing semiconductor device ]

The method for manufacturing a 3 rd semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, and includes the steps of:

a 1C step of preparing an expansion tape and a plurality of semiconductor chips each having a surface opposite to a circuit surface fixed to the expansion tape;

a 2C step of expanding the interval between the plurality of semiconductor chips fixed on the extension tape by stretching the extension tape;

a 3C step of maintaining the tension of the stretched tape;

a 4C step of transferring the plurality of semiconductor chips onto a carrier so that the circuit surface is fixed to the carrier;

a 5C step of peeling the extension tape from the plurality of semiconductor chips;

a 6C step of sealing the plurality of semiconductor chips on the carrier with a sealing material;

a 7C step of peeling the carrier from the plurality of semiconductor chips sealed with the sealing material; and

and an 8C step of forming a plurality of semiconductor packages by singulating the plurality of semiconductor chips sealed with the sealing material into individual semiconductor chips.

The above-described 1C to 8C steps are described below with reference to fig. 8 to 10. Fig. 8 is a schematic cross-sectional view for explaining one embodiment of the 1C to 4C steps, fig. 9 is a schematic cross-sectional view for explaining one embodiment of the 5C to 8C steps, and fig. 10 is a schematic cross-sectional view for explaining another embodiment of the 4C to 8C steps.

First, in the 1C step, an extension tape 1 and a plurality of semiconductor chips 2 fixed to the extension tape 1 are prepared. The extension tape 1 has an adhesive layer 1a and a base material film 1b, and the adhesive layer 1a is in contact with the semiconductor chip 2. The semiconductor chip 2 has a circuit surface provided with a pad (circuit) 3, and the surface opposite to the circuit surface is fixed to the extension tape 1 (fig. 8 (a)). The plurality of semiconductor chips 2 are arranged at intervals.

In the 2C step, the spread tape 1 is stretched to widen the interval between the plurality of semiconductor chips 2 fixed to the spread tape 1 (fig. 8 (b)).

In the 3C step, the stretched extension tape 1 is fixed by using the fixing jig 4, and the tension of the extension tape 1 is maintained (fig. 8 (C)).

In the 4C step, the plurality of semiconductor chips 2 are transferred onto the carrier 5 so that the circuit surface is fixed to the carrier 5. In the transfer, the pad 3 may be completely embedded in the carrier 5, and the circuit surface of the semiconductor chip 2 may be in contact with the carrier 5 (fig. 8(d)), or only a part of the pad 3 may be embedded in the carrier 5, or only the end surface of the pad 3 may be in contact with the carrier 5, and a space may be present between the circuit surface of the semiconductor chip 2 and the carrier 5 (fig. 10 (a)).

In the 5C step, the extension tape 1 is peeled from the plurality of semiconductor chips 2 (fig. 9a or 10 b).

In the 6C step, the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6. After the 5C step, when the circuit surface of the semiconductor chip 2 is in contact with the carrier 5 (fig. 9(a)), the circuit surface is not sealed, but a total of 5 surfaces of the surface of the semiconductor chip 2 opposite to the circuit surface and 4 side surfaces are sealed (fig. 9 (b)). On the other hand, after the 5C step, if there is a sufficient gap between the circuit surface of the semiconductor chip 2 and the carrier 5 to allow the sealing material 6 to flow therein (fig. 10(b)), the circuit surface is also sealed, and the entire 6 surfaces of the semiconductor chip 2 are sealed (fig. 10 (C)).

In the 7C step, the carrier 5 is peeled off from the plurality of semiconductor chips 2 sealed with the sealing material 6 (fig. 9C or 10 d).

In the 8C step, the plurality of semiconductor chips 2 sealed with the sealing material 6 are singulated from semiconductor chip 2 to semiconductor package 10 (fig. 9d or 10 e).

The respective steps will be described in detail below.

< step 1C >

The method of preparing the spreading tape and the plurality of semiconductor chips fixed on the spreading tape is not particularly limited. For example, a semiconductor wafer may be laminated on a dicing tape or the like, and then diced by a blade or a laser to obtain a plurality of semiconductor chips which are made into a single piece, and then transferred to an expansion tape to be manufactured.

The cutting may be performed by forming a fragile layer by laser and expanding the fragile layer. In addition, from the viewpoint of omitting the transfer and improving productivity, the semiconductor wafer may be produced by directly laminating the semiconductor wafer on an expansion tape and dicing the semiconductor wafer by the above-described method.

From the viewpoint of improving productivity and reducing cost, the initial semiconductor chip pitch (the pitch of the semiconductor chips before the 2A step) is preferably narrow, and is preferably 100 μm or less, more preferably 80 μm or less, and still more preferably 60 μm or less. The cutting of the wafer by dicing is preferably narrow as described above from the viewpoint of cost reduction because the wider the chip pitch is, the more the semiconductor wafer is wasted. When the chip pitch is enlarged, the pitch of the initial semiconductor chips is preferably 10 μm or more so as not to apply stress to the semiconductor chips. When the thickness is less than 10 μm, the expansion band region between the plurality of semiconductor chips is small, and therefore, it is difficult to expand the size.

The type of the pad on the circuit surface of the semiconductor chip is not particularly limited as long as it can be formed on the circuit surface of the semiconductor chip, and may be a bump (protruding electrode) such as a copper bump or a solder bump, or a relatively flat metal pad such as a Ni/Au plated pad.

< step 2C >

The space between the plurality of semiconductor chips is expanded by stretching the extension tape.

Examples of the stretching method of the extension tape include a jack-up method and a stretching method. The jack-up method is a method in which after an extension band is fixed, the extension band is extended by raising a table having a predetermined shape. The stretching method is as follows: after the extension tape is fixed, the extension tape is stretched in a predetermined direction parallel to the surface of the extension tape to be set, whereby the extension tape is stretched. The lift-up method is preferable in terms of uniformly extending the intervals of the semiconductor chips and in terms of small and compact required (occupied) device area.

The stretching conditions may be appropriately set according to the properties of the stretched tape. For example, the jack-up amount (stretch amount) in the jack-up method is preferably 10mm to 500mm, more preferably 10mm to 300 mm. When the thickness is 10mm or more, the spacing between the plurality of semiconductor chips is easily increased, and when the thickness is 500mm or less, the semiconductor chips are less likely to be scattered or displaced.

The temperature may be set as appropriate depending on the characteristics of the extension tape, and may be, for example, 10 to 200 ℃, 10 to 150 ℃, or 20 to 100 ℃. When the temperature is 10 ℃ or higher, the expandable tape is easily stretched, and when the temperature is 200 ℃ or lower, it is difficult to cause deformation due to thermal expansion or low elasticity of the expandable tape, or positional deviation of the semiconductor chip (peeling between the expandable tape and the semiconductor chip) due to relaxation, or scattering of the semiconductor chip.

The ejecting speed may be set as appropriate depending on the characteristics of the extension tape, and may be, for example, 0.1 mm/sec to 500 mm/sec, 0.1 mm/sec to 300 mm/sec, or 0.1 mm/sec to 200 mm/sec. When the thickness is 0.1 mm/sec or more, productivity is improved. When the thickness is 500 mm/sec or less, peeling between the semiconductor chip and the extension tape is less likely to occur.

The interval between the plurality of semiconductor chips after the 2C step is preferably 300 μm or more in view of more reliably protecting the side surface of the semiconductor chip with the sealing material in the sealing step (6C step). From the viewpoint of handling properties, the interval between the plurality of semiconductor chips after the 2C step is more preferably 500 μm or more, and still more preferably 1mm or more. The upper limit is not particularly limited, and may be 5mm or less.

< step 3C >

In order to prevent the stretched extension band from returning to the original state, the tension of the extension band is maintained.

The method of holding the tension of the spread tape is not particularly limited as long as the tension is maintained and the pitch of the semiconductor chips does not return to the original state. Examples thereof include a method of fixing with a fixing jig such as a clamp ring (manufactured by TECHNOLOGIES CO., LTD.) and a method of heating and shrinking (heat shrinking) the outer peripheral portion of the extension tape to maintain the tension.

< step 4C >

A plurality of semiconductor chips are transferred (laminated) onto a carrier in such a manner that the circuit surface is fixed on the carrier. The laminating method is not particularly limited, and a roll laminator, a diaphragm laminator, a vacuum roll laminator, a vacuum diaphragm laminator, or the like can be used.

The lamination conditions may be appropriately set depending on the physical properties and characteristics of the spreading tape, the semiconductor chip, and the carrier. For example, in the case of a roll laminator, the temperature may be from room temperature (25 ℃) to 200 ℃, preferably from room temperature (25 ℃) to 150 ℃, and more preferably from room temperature (25 ℃) to 100 ℃. When the temperature is at room temperature or higher, the semiconductor chip is easily transferred (laminated) onto the carrier, and when the temperature is at 200 ℃ or lower, the semiconductor chip is less likely to be displaced (peeled off between the expansion tape and the semiconductor chip) or scattered due to the position deviation of the semiconductor chip (peeling between the expansion tape and the semiconductor chip) or relaxation caused by thermal expansion or low elasticity of the expansion tape. In the case of a diaphragm laminator, the temperature conditions are the same as those in the roll laminator described above. The pressure-bonding time may be 5 seconds to 300 seconds, preferably 5 seconds to 200 seconds, and more preferably 5 seconds to 100 seconds. When the time is 5 seconds or more, the semiconductor chip is easily transferred (laminated) onto the carrier, and when it is 300 seconds or less, the productivity is improved. The pressure may be 0.1MPa to 3MPa, preferably 0.1MPa to 2MPa, and more preferably 0.1MPa to 1 MPa. When the pressure is 0.1MPa or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when the pressure is 2MPa or less, damage to the semiconductor chip can be reduced.

< step 5C >

The extension tape is peeled (removed) from the plurality of semiconductor chips.

When peeling the spread tape, it is necessary to appropriately set the adhesion force between the spread tape and the carrier, between the spread tape and the semiconductor chip, and between the semiconductor chip and the carrier so that the semiconductor chip transferred onto the carrier does not shift in position or peel off from the carrier. For example, the adhesion force of the expansion band to the semiconductor chip is preferably equal to or smaller than the adhesion force of the semiconductor chip to the carrier.

The spread tape or the support surface may be provided with a UV curing function, and the adhesion force (adhesive force) may be changed up or down by UV irradiation. In this case, the extension tape is removed after UV irradiation (additional UV irradiation step). For example, after the step 3C, UV irradiation is performed to reduce the adhesion force (adhesive force) of the spread tape, and then the spread tape may be laminated on the carrier and peeled off from the semiconductor chip. This makes it possible to reduce stress on the semiconductor chip and to smoothly transfer the semiconductor chip without causing positional deviation.

< step 6C >

The plurality of semiconductor chips on the carrier are sealed with a sealing material.

The sealing method is not particularly limited, and examples thereof include compression molding (the sealing material is in the form of a liquid material, a solid material, a particulate material, a film material, etc.), transfer molding (the sealing material is in the form of a liquid material, a solid material, a particulate material, a film material, etc.), lamination of a film-like sealing material, and the like.

After the 6C step, a heat treatment step including post-curing may be added from the viewpoint of adjusting the physical properties of the sealing material. After the 6C step or after the additional heat treatment step, the carrier needs to be peeled off. When the peeling is performed, a heating treatment, a UV treatment process, or the like may be added. After the above-described steps, it is necessary to set the adhesion force of the carrier (carrier + adhesive layer, carrier + temporary fixing material, etc.) so that the carrier is peeled off without damaging the semiconductor chip and the sealing material.

< 7C Process >

The carrier is peeled off from the plurality of semiconductor chips sealed with the sealing material. Before the carrier is peeled off, the following steps may be introduced: by heat treatment or UV irradiation, a chemical or mechanical change is applied to the surface layer of the carrier in contact with the sealing material side, so that the carrier is easily peeled off.

In the 4C step to the 7C step, the semiconductor chip is transferred from the spreading tape to the carrier, whereby the risk of heat resistance in a heating step such as a sealing step can be reduced. For example, when the sealing is performed in a state where the semiconductor chip is present on the expansion tape (without using a carrier), there is a possibility that the semiconductor chip may be misaligned or scattered due to deformation of the expansion tape having stretchability, deformation due to thermal expansion, or the like. When the misalignment or the chip scattering occurs, the productivity is lowered and the cost is increased, and therefore, the semiconductor chip needs to be transferred to a carrier.

< step 8C >

The plurality of semiconductor chips sealed with the sealing material are singulated one by one to form a plurality of semiconductor packages. This step can be performed by a conventionally known method.

When dicing is performed with the doctor blade, it is necessary to set the pitch of the semiconductor chips in the 2C step in consideration of the width of the doctor blade (the portion that is not to be cut). For example, when it is desired to leave a sealing material having a thickness of 50 μm on the side surface of the semiconductor chip, when the doctor blade width is 250 μm, the characteristics of the spread tape and the lift-up condition (spread condition) may be set so that the interval between the plurality of semiconductor chips after the 2C step becomes 350 μm.

The size of the semiconductor chip is not particularly limited, but is preferably 20mm square or less, more preferably 15mm square or less, and still more preferably 10mm square or less, from the viewpoint of the size necessary for protection by the sealing material.

When the thickness of the semiconductor package is reduced for the purpose of downsizing and thinning, a back grinding step (a step of thinning the semiconductor chip by cutting off the sealing material on the back surface side of the circuit surface of the semiconductor chip) may be introduced. The back grinding step may be introduced after the 6C step or after the 7C step, for example.

In the 6C step, when the circuit surface of the semiconductor chip is sealed so as to cover (6-surface sealing), a back-grinding step (removal of the sealing material on the circuit surface side) of exposing the gasket by back-grinding may be introduced.

As a material used in each step, the same material as that used in the method for manufacturing the 1 st semiconductor device can be used.

[4 th method for manufacturing semiconductor device ]

The method for manufacturing a 4 th semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device having a semiconductor chip with a pad provided on a circuit surface, and includes the steps of:

a 1D step of preparing an expansion tape and a plurality of semiconductor chips having circuit surfaces fixed to the expansion tape;

a 2D step of expanding the interval between the plurality of semiconductor chips fixed on the extension tape by stretching the extension tape;

a 3D step of maintaining the tension of the stretched tape;

a 4D step of transferring the plurality of semiconductor chips onto the carrier so that a surface opposite to the circuit surface is fixed to the carrier;

a 5D step of peeling the extension tape from the plurality of semiconductor chips;

a 6D step of sealing the plurality of semiconductor chips on the carrier with a sealing material;

a 7D step of polishing the sealing material to expose the gasket;

a 8D step of peeling the carrier from the plurality of semiconductor chips sealed with the sealing material; and

and a 9D step of singulating the plurality of semiconductor chips sealed with the sealing material into individual semiconductor chips to form a plurality of semiconductor packages.

The above-described 1D to 9D steps will be described below with reference to fig. 11 to 13. Fig. 11 is a schematic cross-sectional view for explaining one embodiment of the 1D to 4D steps, fig. 12 is a schematic cross-sectional view for explaining one embodiment of the 5D to 9D steps, and fig. 13 is a schematic cross-sectional view for explaining another embodiment of the 7D and 8D steps.

First, in the 1D step, the spread tape 1 and the plurality of semiconductor chips 2 fixed to the spread tape 1 are prepared. The extension tape 1 has an adhesive layer 1a and a base material film 1b, and the adhesive layer 1a is in contact with the semiconductor chip 2. The semiconductor chip 2 has a circuit surface provided with a pad (circuit) 3, and the circuit surface is fixed to the extension tape 1 (fig. 11 a). The plurality of semiconductor chips 2 are arranged at intervals. In addition, the spacer 3 may be embedded in the extension band 1 at the time of fixing.

In the 2D step, the extension tape 1 is stretched to widen the interval between the plurality of semiconductor chips 2 fixed to the extension tape 1 (fig. 11 (b)).

In the 3D step, the stretched extension tape 1 is fixed by using the fixing jig 4, and the tension of the extension tape 1 is maintained (fig. 11 (c)).

In the 4D step, the plurality of semiconductor chips 2 are transferred onto the carrier 5 so that the surface opposite to the circuit surface is fixed to the carrier 5 (fig. 11D).

In the 5D step, the extension tape 1 is peeled from the plurality of semiconductor chips 2 (fig. 12 a).

In the 6D step, the plurality of semiconductor chips 2 on the carrier 5 are sealed with the sealing material 6 (12 (b)). At this time, since the surface of the semiconductor chip 2 opposite to the circuit surface is in contact with the carrier 5, the surface is not sealed, and a total of 5 surfaces of the circuit surface and 4 side surfaces of the semiconductor chip 2 are sealed.

In the 7D step, the sealing material 6 is polished to expose the gasket 3.

In the 8D step, the carrier 5 is peeled off from the plurality of semiconductor chips 2 sealed with the sealing material 6.

In addition, the order of the 7D-th step and the 8D-th step may be changed. That is, the carrier 5 may be peeled off from the plurality of semiconductor chips 2 sealed with the sealing material 6 (fig. 12 d) after the sealing material 6 is polished to expose the gasket 3, or the carrier 5 may be peeled off from the plurality of semiconductor chips 2 sealed with the sealing material 6 (fig. 13 a) and then the sealing material 6 may be polished to expose the gasket 3 (fig. 13 b).

In the 9D step, the plurality of semiconductor chips 2 sealed with the sealing material 6 are singulated from semiconductor chip 2 to semiconductor package 10 (fig. 12 e).

The 1D to 6D steps may be performed by the same method as the 1C to 6C steps, and the 8D and 9D steps may be performed by the same method as the 7C and 8C steps, respectively. In the 7D step, the sealing material is polished to expose the gasket. The polishing can be performed by using a conventionally known polishing apparatus or the like. In addition, when the sealing is performed in the 6D step with the circuit surface pads exposed, the 7D step is not necessarily provided.

As the material used in each step, the same material as that used in the method for manufacturing the semiconductor device of the 1 st embodiment can be used, but the carrier 5 may be a material having a layer in which a sealing material and a material capable of protecting a chip are laminated by coating, spin coating, lamination, or the like on a layer responsible for the heat resistance and handling property described above, from the viewpoint of protecting the surface of the semiconductor chip on the opposite side to the circuit surface.

[5 th method for manufacturing semiconductor device ]

The method for manufacturing a 5 th semiconductor device according to the present embodiment includes a tape expanding step of expanding the interval between the semiconductor chips which are fixed to the expanding tape and which are formed into individual pieces from 100 μm or less to 300 μm or more by stretching the expanding tape while heating. The method for manufacturing a semiconductor device according to the present embodiment may further include: a tension maintaining step of maintaining the tension of the stretched extension tape; a transfer step of transferring the semiconductor chip on the tension-maintained spreading tape to a carrier; and a peeling step of peeling the extension tape from the semiconductor chip transferred to the carrier. The respective steps will be explained below.

Fig. 14 is a schematic cross-sectional view for explaining one embodiment of a method for manufacturing a 5 th semiconductor device, and fig. 15 is a schematic cross-sectional view for explaining another embodiment of the method for manufacturing the 5 th semiconductor device.

First, an extension tape 1 to which a singulated semiconductor chip 2 is fixed is prepared (hereinafter, also referred to as a "preparation step"). The extension tape 1 has an adhesive layer 1a and a base material film 1b, and the adhesive layer 1a is in contact with the semiconductor chip 2. In addition, the semiconductor chip 2 has a circuit surface provided with a pad (circuit) 3. The semiconductor chip 2 may be fixed to the expansion tape 1 on the surface opposite to the circuit surface (fig. 14 a), or the circuit surface may be fixed to the expansion tape 1 (fig. 15 a).

In the tape expanding step, the expanded tape 1 is stretched while being heated, thereby expanding the interval between the semiconductor chips 2 fixed to the expanded tape 1 (fig. 14(b) or fig. 15 (b)).

In the tension holding step, the stretched extension tape 1 is fixed by using the fixing jig 4, and the tension of the extension tape 1 is held (fig. 14(c) or fig. 15 (c)).

In the transfer step, the semiconductor chip 2 is transferred onto the carrier 5. In the preparation step, when the surface of the semiconductor chip 2 opposite to the circuit surface is fixed to the extension tape 1, the circuit surface is fixed to the carrier 5 by the transfer (fig. 14(d)), and when the circuit surface of the semiconductor chip 2 is fixed to the extension tape 1 in the preparation step, the surface opposite to the circuit surface is fixed to the carrier 5 by the transfer (fig. 15 (d)).

In the peeling step, the extension tape 1 is peeled from the semiconductor chip 2 (fig. 14 e or fig. 15 e).

The respective steps will be described in detail below.

< preparation Process >

The method of preparing the extension tape to which the monolithically fabricated semiconductor chip is fixed is not particularly limited. For example, a semiconductor wafer may be laminated on a dicing tape or the like, and then diced by a blade or a laser to obtain a plurality of semiconductor chips which are made into a single piece, and then transferred to an expansion tape to be manufactured.

The cutting may be performed by forming a fragile layer by laser and expanding the fragile layer. In addition, from the viewpoint of omitting the transfer and improving productivity, the semiconductor wafer may be produced by directly laminating the semiconductor wafer on an expansion tape and dicing the semiconductor wafer by the above-described method.

From the viewpoint of improving productivity and reducing cost, the initial semiconductor chip pitch (the pitch of the semiconductor chips before the tape expanding step) is preferably narrow, and is preferably 100 μm or less, more preferably 80 μm or less, and still more preferably 60 μm or less. The cutting of the wafer by dicing is preferably narrow as described above from the viewpoint of cost reduction because the wider the chip pitch is, the more the semiconductor wafer is wasted. When the chip pitch is enlarged, the pitch of the initial semiconductor chips is preferably 10 μm or more so as not to apply stress to the semiconductor chips. When the thickness is less than 10 μm, the expansion band region between the plurality of semiconductor chips is small, and therefore, it is difficult to expand the size.

The type of the pad on the circuit surface of the semiconductor chip is not particularly limited as long as it can be formed on the circuit surface of the semiconductor chip, and may be a bump (protruding electrode) such as a copper bump or a solder bump, or a relatively flat metal pad such as a Ni/Au plated pad.

< tape expanding step >

The extension tape is stretched while being heated, thereby expanding the interval between the semiconductor chips that are fixed to the extension tape and that are formed into a single piece.

Examples of the stretching method of the extension tape include a jack-up method and a stretching method. The jack-up method is a method in which after an extension band is fixed, the extension band is extended by raising a table having a predetermined shape. The stretching method is as follows: after the extension tape is fixed, the extension tape is stretched in a predetermined direction parallel to the surface of the extension tape to be set, whereby the extension tape is stretched. The lift-up method is preferable in terms of uniformly extending the intervals of the semiconductor chips and in terms of small and compact required (occupied) device area.

The stretching conditions may be appropriately set according to the properties of the stretched tape. For example, the jack-up amount (stretch amount) in the jack-up method is preferably 10mm to 500mm, more preferably 10mm to 300 mm. When the thickness is 10mm or more, the spacing between the plurality of semiconductor chips is easily increased, and when the thickness is 500mm or less, the semiconductor chips are less likely to be scattered or displaced.

The temperature may be set as appropriate depending on the characteristics of the extension tape, and may be, for example, 25 to 200 ℃, more preferably 25 to 150 ℃, and still more preferably 30 to 100 ℃. When the temperature is 25 ℃ or higher, the expandable tape is easily stretched, and when the temperature is 200 ℃ or lower, it is difficult to cause deformation due to thermal expansion or low elasticity of the expandable tape, or positional deviation of the semiconductor chip (peeling between the expandable tape and the semiconductor chip) due to relaxation, or scattering of the semiconductor chip.

The ejecting speed may be set as appropriate depending on the characteristics of the extension tape, and may be, for example, 0.1 mm/sec to 500 mm/sec, 0.1 mm/sec to 300 mm/sec, or 0.1 mm/sec to 200 mm/sec. When the thickness is 0.1 mm/sec or more, productivity is improved. When the thickness is 500 mm/sec or less, peeling between the semiconductor chip and the extension tape is less likely to occur.

The interval of the semiconductor chips after the tape expanding step may be 300 μm or more, and an appropriate interval may be selected according to the application.

In the FO-WLP application, it is preferable that the thickness is 500 μm or more in order to secure a space necessary for providing a rewiring pattern and a connection terminal pad outside the region of the semiconductor chip. In a semiconductor package with higher density and higher functionality, the total number of rewiring layers is also increased, and therefore, it is necessary to provide a pad for a connection terminal on the outer side of the semiconductor chip. Therefore, the semiconductor chip pitch is preferably wide. From the above viewpoint, the interval between the plurality of semiconductor chips after the tape expanding step is preferably 1mm or more, and more preferably 2mm or more.

The interval between the semiconductor chips after the tape expanding step is 300 μm or more in the FI-WLP application or the discrete semiconductor chip mounting application, from the viewpoint of more reliably protecting the side surface of the semiconductor chip with the sealing material in the sealing step. The interval between the plurality of semiconductor chips after the tape expanding step is preferably 500 μm or more, more preferably 1mm, from the viewpoint of handling property.

The upper limit of the pitch of the semiconductor chips after the tape expanding step is not particularly limited, and may be 5mm or less.

< tension maintaining step >

In order to prevent the stretched extension tape from returning to the original state, the tension of the extension tape is maintained.

The method of holding the tension of the spread tape is not particularly limited as long as the tension is maintained and the pitch of the semiconductor chips is not returned to the original state. Examples thereof include a method of fixing with a fixing jig such as a clamp ring (produced by TECHNOLVISION); and a method of heating and shrinking (heat shrinking) the outer periphery of the extension tape to maintain tension.

< transfer step >

The semiconductor chip is transferred (laminated) onto the carrier in such a manner that the semiconductor chip is fixed. The laminating method is not particularly limited, and a roll laminator, a diaphragm laminator, a vacuum roll laminator, a vacuum diaphragm laminator, or the like can be used.

The lamination conditions may be appropriately set depending on the physical properties and characteristics of the spreading tape, the semiconductor chip, and the carrier. For example, in the case of a roll laminator, the temperature may be from room temperature (25 ℃) to 200 ℃, preferably from room temperature (25 ℃) to 150 ℃, and more preferably from room temperature (25 ℃) to 100 ℃. When the temperature is at room temperature or higher, the semiconductor chip is easily transferred (laminated) onto the carrier, and when the temperature is at 200 ℃ or lower, the semiconductor chip is less likely to be displaced (peeled off between the expansion tape and the semiconductor chip) or scattered due to the position deviation of the semiconductor chip (peeling between the expansion tape and the semiconductor chip) or relaxation caused by thermal expansion or low elasticity of the expansion tape. In the case of a diaphragm laminator, the temperature conditions are the same as those in the roll laminator described above. The pressure-bonding time may be 5 seconds to 300 seconds, preferably 5 seconds to 200 seconds, and more preferably 5 seconds to 100 seconds. When the time is 5 seconds or more, the semiconductor chip is easily transferred (laminated) onto the carrier, and when it is 300 seconds or less, the productivity is improved. The pressure may be 0.1MPa to 3MPa, preferably 0.1MPa to 2MPa, and more preferably 0.1MPa to 1 MPa. When the pressure is 0.1MPa or more, the semiconductor chip is easily transferred (laminated) to the carrier, and when the pressure is 2MPa or less, damage to the semiconductor chip can be reduced.

By transferring the semiconductor chip from the extension tape to the carrier, the risk of heat resistance in a heating process such as a sealing process described later can be reduced.

< stripping Process >

The extension tape is peeled off (removed) from the semiconductor chip.

When peeling the spread tape, it is necessary to appropriately set the adhesion force between the spread tape and the carrier, between the spread tape and the semiconductor chip, and between the semiconductor chip and the carrier so that the semiconductor chip transferred onto the carrier does not shift in position or peel off from the carrier. For example, the adhesion force of the expansion band to the semiconductor chip is preferably equal to or smaller than the adhesion force of the semiconductor chip to the carrier.

The spread tape or the support surface may be provided with a UV curing function, and the adhesion force (adhesive force) may be changed up or down by UV irradiation. In this case, the extension tape is removed after UV irradiation (additional UV irradiation step). For example, after the tension maintaining step, UV irradiation is performed to reduce the adhesion force (adhesive force) of the spread tape, and then the spread tape may be laminated on the carrier and peeled off from the semiconductor chip. This makes it possible to reduce stress on the semiconductor chip and to smoothly transfer the semiconductor chip without causing positional deviation.

< sealing Process >

The method for manufacturing a semiconductor device may further include a sealing step (not shown) of sealing the semiconductor chip fixed to the carrier with a sealing material after the peeling step. According to the method of manufacturing a semiconductor device of the present embodiment, since the semiconductor chips have a sufficient interval therebetween, a total of 5 surfaces of at least 4 side surfaces of the semiconductor chips and a surface opposite to the surface not fixed to the carrier are sealed. In addition, according to the method of manufacturing a semiconductor device of the present embodiment, since the intervals between the semiconductor chips can be sufficiently increased in the tape expanding step, the semiconductor chips after the sealing step can be applied to the WLP technique described above without the rearrangement step.

The sealing step may be a sealing step of sealing the semiconductor chip fixed to the spreading tape with a sealing material after the tension holding step.

The sealing method is not particularly limited, and examples thereof include compression molding (the sealing material is in the form of a liquid material, a solid material, a particulate material, a film material, etc.), transfer molding (the sealing material is in the form of a liquid material, a solid material, a particulate material, a film material, etc.), lamination of a film-like sealing material, and the like.

After the sealing step, a heat treatment step including post-curing may be added from the viewpoint of adjusting the physical properties of the sealing material. After the sealing step or after the additional heat treatment step, the carrier needs to be peeled off. When the peeling is performed, a heating treatment, a UV treatment process, or the like may be added. After the above-described steps, it is necessary to set the adhesion force of the carrier (carrier + adhesive layer, carrier + temporary fixing material, etc.) so that the carrier is peeled off without damaging the semiconductor chip and the sealing material.

When the thickness of the semiconductor package is reduced for the purpose of downsizing and thinning, a back grinding step (a step of thinning the semiconductor chip by cutting the sealing material on the back surface side of the circuit surface of the semiconductor chip) may be introduced after the sealing step.

In the method for manufacturing the 5 th semiconductor device, the same material as that used in the method for manufacturing the 1 st semiconductor device described above can be used, and the extension tape of the present embodiment described below can be particularly preferably used. The extended band of the present embodiment can be manufactured by the same method as the method for manufacturing the extended band in the method for manufacturing the semiconductor device of the above-described 1 st embodiment.

The stretched tape of the present embodiment has a tensile stress of 10MPa or less at the heating temperature (e.g., 50 ℃) in the tape stretching step, and a tensile stress at room temperature (25 ℃) of 5MPa or more higher than the tensile stress at the heating temperature. The reason why the spread tape of the present embodiment can be preferably applied to the above-described method for manufacturing a semiconductor device, particularly, the tape spreading step, is not clear, but the present inventors believe as follows.

In the tape expanding step, the extension of the expanding tape in the region where the semiconductor chip is fixed contributes to the expansion of the semiconductor chip pitch, and the extension of the edge portion of the expanding tape does not contribute to the expansion of the semiconductor chip pitch. In the tape expanding step, the expanding tape in the region (the region of the stage) where the semiconductor chip is fixed is heated, and the edge portion of the expanding tape is not heated and is at room temperature. Further, the tensile stress of the extension tape is reduced by heating, and the extension tape is more easily elongated as the tensile stress is smaller.

Therefore, by setting the tensile stress of the expandable tape at the heating temperature in the tape expanding step to a smaller value than the predetermined range and setting the tensile stress of the expandable tape at room temperature to be higher than the tensile stress at the heating temperature by the predetermined value or more, the extension of the expandable tape in the region where the semiconductor chips are fixed in the tape expanding step is sufficiently larger than the extension of the edge portion of the expandable tape, and the pitch of the semiconductor chips can be further increased.

In order to further widen the interval between the semiconductor chips after expansion, the tensile stress at the heating temperature of the expansion tape is preferably 9MPa or less, more preferably 8MPa or less.

The tensile stress at the heating temperature of the stretched tape is not particularly limited, but is preferably 0.1MPa or more. When the pressure is less than 0.1MPa, the chip is easily deformed or the tape is easily loosened.

In order to further widen the interval between the semiconductor chips after expansion, the tensile stress at room temperature (25 ℃) of the expanded tape is preferably higher than the tensile stress at the heating temperature by 6MPa or more, more preferably 7MPa or more.

The tensile stress is a value at which the tensile strain measured by a Micro Force frictional wear tester (INSTRON, INSTRON5948) is 1 (mm/mm). The drawing speed was 5 mm/sec.

The die pitch between MD and TD after the tape expanding step is preferably uniform, but when the semiconductor chip and the connection terminal pads connected thereto are singulated as a set after sealing, the MD and TD may be non-uniform in width as long as the dicing can be performed without damaging the semiconductor chip (as long as the semiconductor chip is not damaged by the doctor blade). When cutting is performed, the cutting interval widths of MD and TD may be different. However, it is preferable that the MD lines and the TD lines are uniform.

The spreading tape may have a multi-layer structure such as a base film (base material layer) which greatly contributes to stretchability, an adhesive layer for controlling adhesion, and the like.

The substrate film preferably has stretchability and maintains the stability of the semiconductor chip pitch after the tension maintaining step.

The substrate film may be a polyester film such as a polyethylene terephthalate film; a homopolymer of an α -olefin such as a polytetrafluoroethylene film, a polyethylene film, a polypropylene film, a polymethylpentene film, a polyvinyl acetate film, or a poly-4-methylpentene-1, a copolymer thereof, and a polyolefin film containing the homopolymer or an ionomer of the copolymer; a polyvinyl chloride film; and a polyimide film; various plastic films such as urethane resin films. The substrate film is not limited to a single-layer film, and may be a multilayer film obtained by combining 2 or more kinds of the above plastic films or 2 or more kinds of the same plastic films.

The substrate film is preferably a polyolefin film or a urethane resin film from the viewpoint of stretchability. The base film may contain various additives such as an antiblocking agent, if necessary.

The thickness of the base film may be appropriately set as needed, and is preferably 50 μm to 500 μm. When the thickness is less than 50 μm, the stretchability is lowered, and when the thickness is more than 500. mu.m, defects such as deformation and deterioration in handling property are liable to occur.

The thickness of the base film is appropriately selected within a range that does not impair the operability. However, when a high-energy-ray (particularly, ultraviolet-ray) -curable adhesive is used as the adhesive constituting the adhesive layer, the thickness thereof is required to be a thickness that does not inhibit the transmission of the high-energy-ray. From this viewpoint, the thickness of the base film may be usually 10 to 500. mu.m, preferably 50 to 400. mu.m, and more preferably 70 to 300. mu.m.

When the base material layer is formed of a plurality of base material films, the thickness of the entire base material layer is preferably adjusted to be within the above range. The base film may be subjected to chemical or physical surface treatment as necessary in order to improve adhesion to the adhesive layer. Examples of the surface treatment include corona treatment, chromic acid treatment, ozone exposure, flame exposure, high-voltage shock exposure, and ionizing radiation treatment.

The adhesive layer is not particularly limited as long as it can control the adhesive force (set so that the semiconductor chips are not positionally displaced or scattered in each step).

The adhesive layer is preferably composed of an adhesive component having an adhesive force at room temperature and an adhesive force to the semiconductor chip. Examples of the matrix resin constituting the adhesive component of the adhesive layer include acrylic resins, synthetic rubbers, natural rubbers, polyimide resins, and the like.

The matrix resin preferably has a functional group (hydroxyl group, carboxyl group, or the like) capable of reacting with other additives, from the viewpoint of reducing the residual gum of the binder component. As the binder component, a resin that is cured by high-energy rays such as ultraviolet rays and radiation (particularly, an ultraviolet-curable resin) or a resin that is cured by heat (a thermosetting resin) can be used. When such a curable resin is used, the adhesive force can be reduced by curing the resin. In particular, an ultraviolet-curable adhesive including an ultraviolet-curable resin can be preferably used.

In addition, the adhesive component may further contain a crosslinking agent capable of crosslinking with the functional group of the matrix resin in order to adjust the adhesive strength. The crosslinking agent preferably has at least 1 functional group selected from an epoxy group, an isocyanate group, an aziridine group and a melamine group. These crosslinking agents may be used alone, or 2 or more kinds may be used in combination. When the reaction rate is low, a catalyst such as amine or tin may be used as necessary. The pressure-sensitive adhesive may further contain optional components such as a tackifier such as a rosin-based resin and a terpene resin, and various surfactants, for the purpose of adjusting the pressure-sensitive adhesive properties.

The thickness of the adhesive layer is usually 1 to 100 μm, preferably 2 to 50 μm, and more preferably 5 to 40 μm. By setting the thickness of the adhesive layer to 1 μm or more, sufficient adhesive force with the semiconductor chip can be secured, and therefore, scattering of the semiconductor chip is easily suppressed in the tape spreading step. On the other hand, even if the thickness exceeds 100 μm, there is no advantage in the characteristics, and it is uneconomical.

When the adhesive layer is 10 μm or more, the base film is not damaged (e.g., scratched) even when the semiconductor wafer is cut on the dicing tape without using the dicing tape, and therefore, the step of transferring (attaching) the semiconductor wafer after the semiconductor wafer is cut on the dicing tape to the expansion tape can be omitted in the preparation step.