Semiconductor substrate, array substrate, inverter circuit, and switching circuit
阅读说明:本技术 半导体基板、阵列基板、逆变器电路及开关电路 (Semiconductor substrate, array substrate, inverter circuit, and switching circuit ) 是由 高逸群 林欣桦 于 2018-06-26 设计创作,主要内容包括:本发明一种半导体基板,其包括基板、设置于基板上的第一薄膜晶体管以及第二薄膜晶体管,该第一薄膜晶体管为金属氧化物薄膜晶体管,该第二薄膜晶体管为低温多晶硅薄膜晶体管;该第一薄膜晶体管包括该第一源极以及第一漏极,该第二薄膜晶体管包括第二源极以及第二漏极。该第一源极或第一漏极中的一者与该第二源极或第二漏极中的一者电性连接。本发明还提供应用上述半导体基板的阵列基板、逆变器电路及开关电路,本发明的半导体基板包括金属氧化物薄膜晶体管,且金属氧化物薄膜晶体管与低温多晶硅薄膜晶体管共用源/漏极,可以减小使用该半导体基板的电子元件体积和漏电流。(The invention relates to a semiconductor substrate, which comprises a substrate, a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are arranged on the substrate; the first thin film transistor comprises a first source electrode and a first drain electrode, and the second thin film transistor comprises a second source electrode and a second drain electrode. One of the first source or the first drain is electrically connected with one of the second source or the second drain. The invention also provides an array substrate, an inverter circuit and a switch circuit applying the semiconductor substrate, wherein the semiconductor substrate comprises a metal oxide thin film transistor, and the metal oxide thin film transistor and the low-temperature polycrystalline silicon thin film transistor share a source/drain electrode, so that the volume of an electronic element using the semiconductor substrate and leakage current can be reduced.)
1. A semiconductor substrate comprises a substrate, a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are arranged on the substrate, and the semiconductor substrate is characterized in that:
the first thin film transistor is a top gate type metal oxide thin film transistor, and the second thin film transistor is a bottom gate type low-temperature polycrystalline silicon thin film transistor;
the first thin film transistor comprises a first grid electrode, a metal oxide semiconductor layer, a first source electrode and a first drain electrode, wherein the first grid electrode and the metal oxide semiconductor layer are arranged on the substrate, and the first source electrode and the first drain electrode are connected with the metal oxide semiconductor layer and are spaced from each other;
the second thin film transistor comprises a polycrystalline silicon semiconductor layer, a second grid electrode, a second source electrode and a second drain electrode, wherein the polycrystalline silicon semiconductor layer and the second grid electrode are arranged on the substrate in sequence; and
one of the first source or the first drain is electrically connected with one of the second source or the second drain.
2. The semiconductor substrate of claim 1, wherein: one of the first source electrode or the first drain electrode and one of the second source electrode or the second drain electrode are arranged on the same layer and are directly connected.
3. The semiconductor substrate of claim 2, wherein: the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are formed by patterning the same conductive layer.
4. The semiconductor substrate of claim 1, wherein: the metal oxide semiconductor layer is positioned on one side of the first source electrode and the first drain electrode, which is far away from the substrate.
5. The semiconductor substrate of claim 1, wherein: the semiconductor substrate further comprises a gate insulating layer formed on the substrate and covering the first gate and the second gate;
the grid insulation layer comprises a first grid insulation layer and a second grid insulation layer which are sequentially stacked along the direction far away from the substrate; and
the second gate insulating layer is provided with at least one through hole penetrating through the second gate insulating layer in the thickness direction, and the first source electrode and the first drain electrode are in direct contact with the first gate insulating layer through the at least one through hole.
6. The semiconductor substrate of claim 5, wherein: the first gate and the second gate are patterned from the same conductive layer.
7. The semiconductor substrate of claim 1, wherein: the semiconductor substrate comprises a first grid insulating layer and a second grid insulating layer which are sequentially stacked on the substrate, the second grid is positioned on one side, away from the second grid insulating layer, of the first grid insulating layer, and the first grid is positioned between the first grid insulating layer and the second grid insulating layer.
8. An array substrate comprising the semiconductor substrate of any one of claims 1-7.
9. An inverter circuit comprising the semiconductor substrate according to any one of claims 1 to 7.
10. A switching circuit comprising the semiconductor substrate of any one of claims 1-7.
Technical Field
The invention relates to a semiconductor substrate, an array substrate, an inverter circuit and a switch circuit.
Background
The flat display device has many advantages of thin body, power saving, no radiation, etc., and is widely used. Conventional flat panel Display devices mainly include Liquid Crystal Displays (LCDs) and Organic electroluminescent devices (OELDs), which are also called Organic Light Emitting Diodes (OLEDs). Generally, an array substrate of a display includes a substrate on which a pixel array including a plurality of pixel units and a driving circuit for driving the pixel array are disposed, and the driving circuit is applied to a thin film transistor. In addition, a peripheral circuit of the display device is also applied to the thin film transistor. The electron mobility of the polysilicon thin film transistor manufactured by using a Low Temperature Polysilicon (LTPS) technology is greater than that of the metal oxide thin film transistor, but the leakage current of the polysilicon thin film transistor is higher than that of the metal oxide thin film transistor, which affects the performance of the array substrate or the peripheral circuit.
Disclosure of Invention
In view of the above, it is desirable to provide a semiconductor substrate with good performance.
A semiconductor substrate comprises a substrate, a first thin film transistor and a second thin film transistor, wherein the first thin film transistor and the second thin film transistor are arranged on the substrate; the first thin film transistor comprises a first grid electrode, a metal oxide semiconductor layer, a first source electrode and a first drain electrode, wherein the first grid electrode and the metal oxide semiconductor layer are arranged on the substrate, and the first source electrode and the first drain electrode are connected with the metal oxide semiconductor layer and are spaced from each other; the second thin film transistor comprises a polycrystalline silicon semiconductor layer, a second grid electrode, a second source electrode and a second drain electrode, wherein the polycrystalline silicon semiconductor layer and the second grid electrode are arranged on the substrate in sequence; one of the first source or the first drain is electrically connected with one of the second source or the second drain.
The invention also provides an array substrate, an inverter circuit and a switch circuit, which comprise the semiconductor substrate.
Compared with the prior art, the semiconductor substrate comprises the metal oxide thin film transistor, and the metal oxide thin film transistor and the low-temperature polycrystalline silicon thin film transistor share the source/drain electrode, so that the volume of an electronic element using the semiconductor substrate and the leakage current can be reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor substrate according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor substrate according to a second embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a semiconductor substrate according to a third embodiment of the invention.
Fig. 4 is a schematic plan view of an array substrate to which an embodiment of the invention is applied.
Fig. 5 is an equivalent circuit diagram of a pixel driving circuit in a pixel unit according to an embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention.
Fig. 7 is an equivalent circuit diagram of an inverter circuit according to an embodiment of the present invention.
Fig. 8 is a schematic plan view of an inverter circuit according to an embodiment of the present invention.
Fig. 9 is an equivalent circuit diagram of a switch circuit according to an embodiment of the invention.
Description of the main elements
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a
As shown in fig. 1, in the present embodiment, the
The first thin film transistor T1 is a Bottom-gate thin film transistor, which includes a
The second thin film transistor T2 is located beside the first thin film transistor T1, and is a Top-gate (Top-gate) thin film transistor, which includes a Poly-silicon (Poly-silicon)
In this embodiment, the
One of the
In the embodiment, the metal
In the present embodiment, the
For convenience of description, in the following embodiments, elements having the same structure and function as those in the first embodiment are not described herein again, and the reference numerals in the first embodiment are used.
Referring to fig. 2, fig. 2 is a schematic cross-sectional view of a
In the present embodiment, since the second
Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a
In the present embodiment, the
In this embodiment, the first
In the present embodiment, the
In the present embodiment, the
The
Referring to fig. 4, fig. 4 is a schematic plan view of an array substrate 100 to which an embodiment of the invention is applied. The array substrate 100 of an embodiment of the invention is an organic electroluminescent (OLED) display panel, and the array substrate 100 includes a substrate 11, wherein the substrate 11 is provided with a plurality of scan lines S1-Sn parallel to each other and a plurality of data lines D1-Dn parallel to each other and intersecting with the scan lines S1-Sn. The scan lines S1-Sn are electrically connected to the first driving circuit 12, and the data lines D1-Dn are electrically connected to the second driving circuit 13. The scan lines S1-Sn intersect the data lines D1-Dn in a vertically isolated manner to define a plurality of pixel units 14. Each pixel cell 14 has a corresponding pixel drive circuit 15 (shown in figure 5). In the present embodiment, the first driving circuit 12 may include a multiplexing circuit and a gate driving circuit. The second driving circuit 13 is a data driving circuit.
Referring to fig. 5, fig. 5 is an equivalent circuit diagram of the
The gate of the third tft T3 is electrically connected to the first scan line S1, the drain is electrically connected to the data line D1, and the source is electrically connected to the gate of the first tft T1 through the first node a. The drain of the first thin film transistor T1 is electrically connected to the source of the second thin film transistor T2, and the source of the first thin film transistor T1 is electrically connected to the Anode (Anode) of the organic light emitting diode OLED through a second node B. The gate of the second tft T2 is electrically connected to the third scan line S3, and the drain of the second tft T2 is electrically connected to the power line VDD. The gate of the fourth tft T4 is electrically connected to the second scan line S2, and the drain of the fourth tft T4 is electrically connected to the second node B. The anode of the organic light emitting diode OLED is electrically connected to the source of the first thin film transistor T1, and the cathode thereof is electrically connected to the ground Vss. The storage capacitor Cs is electrically connected between the gate and the source of the first thin film transistor T1. The parasitic capacitance COLEDAnd the organic light emitting diode OLED is electrically connected between the cathode and the anode of the organic light emitting diode OLED.
It is understood that the pixel unit 14 is not limited to the structure shown in fig. 5, and may also be a pixel structure of 5T1C (including 5 Thin Film Transistors (TFTs) and a capacitor C) (not shown), so long as it is adapted to a structure in which one of the
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of an array substrate 100 according to an embodiment of the invention. For convenience of description, the first thin film transistor T1 and the second thin film transistor T2 are illustrated in fig. 6, and other elements such as the third thin film transistor T3 and the fourth thin film transistor T4 are omitted. The array substrate 100 in this embodiment uses the
As shown in fig. 6, the array substrate 100 further includes a
In the array substrate 100 of the embodiment, the second thin film transistor T2 is a metal oxide thin film transistor, and compared with an array substrate that only uses a low temperature polysilicon thin film transistor, the second thin film transistor T2 that is a metal oxide thin film transistor has a smaller volume and a simpler process, and has a low leakage current to reduce power consumption and improve the performance of the array substrate 100.
In the present embodiment, the
Referring to fig. 7 and 8, fig. 7 is an equivalent circuit diagram of an inverter circuit 30 according to an embodiment of the invention. Fig. 8 is a schematic plan view of the inverter circuit 30 according to the embodiment of the present invention. In the present embodiment, the inverter circuit 30 is applied to the
As shown in fig. 8, the
Referring to fig. 9, fig. 9 is an equivalent circuit diagram of a switch circuit 40 according to an embodiment of the invention. In this embodiment, the
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention.
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