Transmission apparatus and interleaving method thereof
阅读说明:本技术 传输设备及其交织方法 (Transmission apparatus and interleaving method thereof ) 是由 明世澔 金庆中 郑鸿实 安索瑞归·丹尼尔·罗百帝 贝勒卡西姆·穆霍什 于 2015-05-21 设计创作,主要内容包括:提供了一种传输设备。所述传输设备包括:编码器,配置成基于包括信息字位和奇偶校验位的奇偶校验矩阵通过对输入位进行低密度奇偶校验(LDPC)编码来生成LDPC码字,所述LDPC码字包括多个位组,所述多个位组中的每个位组包括多个位;交织器,配置成对所述LDPC码字进行交织;以及调制器,配置成将所交织的LDPC码字映射到调制符号上,其中,所述交织器还配置成对所述LDPC码字进行交织以使得在构成所述LDPC码字的所述多个位组之中的预定位组中包括的位在所述调制符号的预定位上。(A transmission apparatus is provided. The transmission apparatus includes: an encoder configured to generate an LDPC codeword by Low Density Parity Check (LDPC) encoding input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups, each of the plurality of bit groups including a plurality of bits; an interleaver configured to interleave the LDPC codewords; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group among the plurality of bit groups constituting the LDPC codeword is on a predetermined bit of the modulation symbol.)
1. The transmission method comprises the following steps:
encoding input bits based on a low density parity having a code rate of 5/15 and a codeword length of 16200 bits, thereby generating parity bits;
partitioning a codeword comprising the input bits and the parity bits into a plurality of groups of bits;
interleaving the plurality of groups of bits to provide an interleaved codeword; and
mapping bits of the interleaved codeword onto modulation symbols based on 16-QAM,
wherein the interleaving interleaves the plurality of groups of bits based on the following equation:
Yj=Xπ(j)(0≤j<Ngroup),
wherein, XjIs the jth bit group, Y, of said plurality of bit groupsjIs the jth bit group, N, of the plurality of bit groups after interleavinggroupIs the total number of the plurality of bit groups, and pi (j) is the interleaving order in which the interleaving is performed, and where pi (j) is expressed as follows:
2. the transmission method of claim 1, further comprising:
and interleaving the plurality of interleaved bit groups.
3. The transmission method according to claim 1, wherein pi (j) is determined based on at least one of a length of the low density parity check codeword, a modulation method, and a code rate.
Technical Field
Apparatuses and methods consistent with exemplary embodiments relate to a transmission apparatus and an interleaving method thereof, and more particularly, to a transmission apparatus that processes and transmits data and an interleaving method thereof.
Background
In the 21 st century of information-oriented society, broadcast communication services are entering the era of digitization, multi-channel, broadband, and high quality. In particular, as high-quality digital televisions, portable multimedia players, and portable broadcasting devices are increasingly used in recent years, demands for methods for various receiving methods supporting a digital broadcasting service are gradually increasing.
To meet such demands, standardization organizations are establishing various standards and providing a variety of services to meet the needs of users. Therefore, a method for providing improved services to users with high decoding and receiving performance is required.
Disclosure of Invention
Technical problem
Exemplary embodiments of the inventive concept may overcome the above disadvantages and other disadvantages not described above. However, it should be understood that the exemplary embodiments need not overcome the disadvantages described above, and may not overcome any of the problems described above.
Technical scheme
Exemplary embodiments provide a transmission apparatus that may map bits included in a predetermined bit group among a plurality of bit groups of a Low Density Parity Check (LDPC) codeword to predetermined bits of a modulation symbol and transmit the bits, and an interleaving method of the transmission apparatus.
According to an aspect of the exemplary embodiments, there is provided a transmission apparatus including: an encoder configured to generate an LDPC codeword by LDPC encoding; an interleaver configured to interleave the LDPC codewords; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map bits included in a predetermined bit group among a plurality of bit groups constituting the LDPC codeword onto predetermined bits of the modulation symbol.
Each bit group of the plurality of bit groups may be formed of M bits. M may be NldpcAnd KldpcAnd can be determined to satisfy Qldpc=(Nldpc-Kldpc) and/M. In this case, QldpcMay be a value of a cyclic shift parameter, N, associated with a column of a column group of an information word sub-matrix of the parity check matrixldpcMay be the length of the LDPC codeword, and KldpcMay be the length of the information word bits of the LDPC codeword.
The interleaver may include: a parity interleaver configured to interleave parity bits of an LDPC codeword; a group interleaver configured to divide the parity-check-bit-interleaved LDPC codeword into a plurality of bit groups and rearrange an order of the plurality of bit groups by bit group; and a block interleaver configured to interleave the plurality of bit groups, the order of which is rearranged.
The group interleaver may be configured to rearrange the order of the plurality of bit groups in bit groups by using the following equation:
Yj=Xπ(j)(0≤j<Ngroup)
wherein, XjIs the jth bit group before the interleaving of the plurality of bit groups,YjIs the jth bit group, N, after interleaving of multiple bit groupsgroupIs the total number of the plurality of bit groups, and pi (j) is a parameter indicating the interleaving order.
Here, pi (j) may be determined based on at least one of a length, a modulation method, and a code rate of the LDPC codeword.
When the length of the LDPC codeword is 16200, the modulation method is 16-QAM, and the code rate is 5/15, pi (j) may be defined as in table 15.
The block interleaver may be configured to interleave by writing the plurality of bit groups bitwise into each of a plurality of columns in a column direction and reading each row of the plurality of columns in which the plurality of bit groups are written bitwise in a row direction.
The block interleaver may be configured to successively write at least some bit groups, which may be written in the plurality of columns by bit group, among the plurality of bit groups, in the plurality of columns, and to divide and write other bit groups in a region remaining after writing the at least some bit groups in the plurality of columns by bit group.
According to an aspect of another exemplary embodiment, there is provided an interleaving method of a transmission apparatus, the method including: generating an LDPC codeword through LDPC encoding; interleaving the LDPC codeword; and mapping the interleaved LDPC codeword onto a modulation symbol, wherein the mapping includes mapping bits included in a predetermined bit group among a plurality of bit groups constituting the LDPC codeword onto predetermined bits of the modulation symbol.
Each bit group of the plurality of bit groups may be formed of M bits, and M may be NldpcAnd KldpcAnd may be determined to satisfy Qldpc=(Nldpc-Kldpc) and/M. In this case, QldpcMay be a value of a cyclic shift parameter, N, associated with a column of a column group of an information word sub-matrix of the parity check matrixldpcMay be the length of the LDPC codeword, and KldpcMay be the length of the information word bits of the LDPC codeword.
The interleaving may include: interleaving parity check bits of the LDPC codeword; dividing the parity-check-bit-interleaved LDPC codeword into a plurality of bit groups and rearranging an order of the plurality of bit groups by bit group; and interleaving the plurality of bit groups whose order is rearranged.
Rearranging the order of the plurality of bit groups by bit group may include rearranging the order of the plurality of bit groups by bit group by using the following equation:
Yj=Xπ(j)(0≤j<Ngroup)
wherein, XjIs the jth bit group, Y, before the interleaving of the plurality of bit groupsjIs the jth bit group, N, after interleaving of multiple bit groupsgroupIs the total number of the plurality of bit groups, and pi (j) is a parameter indicating the interleaving order.
Here, pi (j) may be determined based on at least one of a length, a modulation method, and a code rate of the LDPC codeword.
When the length of the LDPC codeword is 16200, the modulation method is 16-QAM, and the code rate is 5/15, pi (j) may be defined as in table 15.
Interleaving the plurality of bit groups may comprise: interleaving is performed by bitwise writing the plurality of bit groups into each of a plurality of columns in a column direction and reading each row of the plurality of columns in which the plurality of bit groups are bitwise written in a row direction.
Interleaving the plurality of bit groups may include successively writing at least some bit groups, which may be written in the plurality of columns by bit group, among the plurality of bit groups, in the plurality of columns, and dividing and writing other bit groups in an area remaining after writing the at least some bit groups in the plurality of columns by bit group.
Advantageous effects
According to various exemplary embodiments, improved decoding and reception performance may be provided.
Drawings
The foregoing and/or other aspects will become more apparent by describing in detail exemplary embodiments with reference to the attached drawings in which:
fig. 1 to 12 are views showing a transmission apparatus according to an exemplary embodiment;
fig. 13 to 18 are views showing a receiving apparatus according to an exemplary embodiment;
fig. 19 is a block diagram showing a configuration of a transmission apparatus according to an exemplary embodiment;
fig. 20 to 22 are views showing a configuration of a parity check matrix according to an exemplary embodiment;
fig. 23 is a block diagram showing a configuration of an interleaver according to an exemplary embodiment;
fig. 24 to 26 are views illustrating an interleaving method according to an exemplary embodiment;
fig. 27 to 32 are views illustrating an interleaving operation of a block interleaver according to an exemplary embodiment;
FIG. 33 is a block diagram illustrating the operation of a demultiplexer in accordance with the illustrative embodiments;
fig. 34 is a view illustrating a method for designing an interleaving pattern according to an exemplary embodiment;
fig. 35 is a view showing a configuration of a reception apparatus according to an exemplary embodiment;
fig. 36 is a view showing a configuration of a deinterleaver according to an exemplary embodiment;
fig. 37 is a view illustrating a deinterleaving operation of a block deinterleaver according to an exemplary embodiment;
fig. 38 is a flowchart illustrating an interleaving method according to an exemplary embodiment;
fig. 39 is a block diagram showing a configuration of a receiving apparatus according to an exemplary embodiment;
FIG. 40 is a block diagram illustrating a demodulator according to an example embodiment; and
fig. 41 is a flowchart for illustrating an operation of a reception apparatus from the time when a user selects a service until the selected service is reproduced according to an exemplary embodiment.
Detailed Description
Various exemplary embodiments will be described in more detail below with reference to the accompanying drawings.
In the following description, like reference numerals depicted in different drawings denote like elements. Matters defined in the description such as a detailed construction and elements are provided to assist in a comprehensive understanding of the exemplary embodiments. It is therefore evident that the illustrative embodiments may be practiced without these specifically defined matters. Further, functions or elements known in the related art are not described in detail since they would obscure the exemplary embodiments in unnecessary detail.
Fig. 1A is used to illustrate a transmission device according to an example embodiment.
According to fig. 1A, a transmission apparatus 10000 according to an exemplary embodiment may include input formatting blocks (or portions) 11000, 11000-1, Bit Interleaving and Coded Modulation (BICM) blocks 12000, 12000-1, framing/interleaving blocks 13000, 13000-1, and waveform generating blocks 14000, 14000-1.
The transmission apparatus 10000 according to the exemplary embodiment shown in fig. 1A includes a standard block shown by a solid line and an information block shown by a dotted line. Here, the block shown by the solid line is a standard block and the block shown by the dotted line is a block that can be used when implementing information Multiple Input Multiple Output (MIMO).
The input formatting blocks 11000, 11000-1 generate baseband frames (BBFRAME) from the input data stream to be serviced. Herein, the input stream may be a Transport Stream (TS), an Internet Protocol (IP) stream, a General Stream (GS), a General Stream Encapsulation (GSE), or the like.
The BICM blocks 12000, 12000-1 determine a Forward Error Correction (FEC) coding rate and a constellation order according to a region (e.g., a fixed PHY frame or a mobile PHY frame) where data to be serviced is to be transmitted, and then perform coding. Depending on the system implementation, the signaling information on the data to be serviced may be encoded by a separate BICM encoder (not shown) or by sharing the
The framing/interleaving blocks 13000, 13000-1 combine the time interleaved data with the signaling information to generate a transmission frame.
The waveform generation blocks 14000, 14000-1 generate an OFDM signal in a time domain on the generated transmission frame, modulate the generated OFDM signal to a Radio Frequency (RF) signal, and transmit the modulated RF signal to a receiver.
Fig. 1B and 1C are used to illustrate a method of multiplexing according to an exemplary embodiment.
FIG. 1B illustrates a block diagram implementing Time Division Multiplexing (TDM), according to an example embodiment.
In TDM system architectures, there are four main blocks (or parts): an
Data is input and formatted in an input formatting block and forward error correction is applied and mapped to constellations in a
Fig. 1C shows a block diagram implementing hierarchical multiplexing (LDM) according to another exemplary embodiment.
There are several different blocks in an LDM system architecture compared to a TDM system architecture. Specifically, there are two separate input formatting blocks 11000, 11000-1 and BICM blocks 12000, 12000-1, one for each layer in the LDM. These input formatting blocks and BICM blocks are combined prior to the framing/
Fig. 2 is a block diagram showing a detailed configuration of the input formatting block shown in fig. 1A.
As shown in fig. 2, the
The input data packet input to the
The
The functional assets of the
In addition, the operation of the
Furthermore, a maximum of four PLPs should be used for each service. Multiple services consisting of multiple time interleaved blocks can be constructed, up to a total of 64 PLPs for bandwidths of 6, 7 or 8 MHz. As shown in fig. 3A, the
As shown in fig. 3B, the
The baseband frame header structure blocks 3200, 3200-1, … 3200-n configure the baseband frame headers. As shown in fig. 3B, the baseband frame header 3500-1 is composed of three parts, including a
The primary feature of the
For example, the extension field (or extension header) 3730 may be used later for baseband frame packet counts, baseband frame timestamps, and additional signaling, among others.
The baseband
To ensure that the payload data is not always mapped to the same point when mapped to a constellation (such as when the payload mapped to a constellation consists of a repeated sequence), the payload data should always be scrambled before forward error correction coding.
The scrambling code sequence should be generated by a 16-bit shift register with 9 feedback taps. Eight of the shift register outputs are selected as fixed random bytes, with each bit from the byte being used to individually perform an exclusive or (XOR) operation with the corresponding input data. The Most Significant Bit (MSB) is xored with the data bits for the MSB, and so on until the Least Significant Bit (LSB) is for the LSB. The generator polynomial is G (X) 1+ X3+X6+X7+X11+X12+X13+X16。
Fig. 4 shows a shift register of a Pseudo Random Binary Sequence (PRBS) encoder for scrambling baseband according to an exemplary embodiment, where the sequence should be loaded into the PRBS register starting at the beginning of each baseband frame, as shown in fig. 4.
Fig. 5 is a block diagram for explaining a detailed configuration of the BICM block shown in fig. 1A.
As shown in fig. 5, the BICM blocks include FEC blocks 12100, 12100-1, …, 12100-n, bit
The input to the FEC blocks 1200, 12100-1, …, 12100-n is a length KpayloadAnd the output from the FEC block is an FEC frame. The FEC blocks 12100, 12100-1, …, 12100-n are implemented by concatenation of an outer code and an inner code with the information portion. The FEC frame has a length Ninner. Two different lengths of LDPC codes are defined as: n is a radical ofinner64800 bits and Ninner16200 bits.
The outer code is implemented as one of a BCH (Bose, Ray-Chaudhuri and Hocquenghem) outer code, a Cyclic Redundancy Check (CRC), or other code. The inner code is implemented as a Low Density Parity Check (LDPC) code. Both BCH and LDPC FEC codes are systematic codes, where the information part I is contained within the codeword. The resulting codeword is thus a concatenation of the information or payload portion, the BCH or CRC parity bits and the LDPC parity bits, as shown in fig. 6A.
The use of LDPC codes is mandatory and is used to provide the redundancy required for code detection. Two different LDPC structures are defined, these being referred to as type a and type B. Type a has a code structure that exhibits better performance at low code rates, while type B code structures exhibit better performance at high code rates. In general, it is contemplated to use Ninner64800 bit code. However, N may also be used for applications that are delay critical, or for applications that prefer a simple encoder/decoder structureinner16200 bits of code.
The outer code and CRC include MouterBits are added to the incoming baseband frame. The outer BCH code is used to reduce the inherent LDPC error floor by correcting a predetermined number of bit errors. When BCH codes are used, MouterIs 192 bits (N)inner64800 bit code) and 168 bits (for N)inner16200 bits of code). When CRC is used, MouterIs 32 bits in length. When in useWhen neither BCH nor CRC is used, MouterIs zero. The outer code may be omitted if it is determined that the error correction capability of the inner code is sufficient for the application. When there is no outer code, the structure of the FEC frame is as shown in fig. 6B.
Fig. 7 is a block diagram for explaining a detailed configuration of the bit interleaver block shown in fig. 5.
The LDPC codeword (i.e., FEC frame) of the LDPC encoder should be bit interleaved by the bit
The
In addition, the LDPC code bits interleaved by parity bits are divided into Ngroup=NinnerThe/360 bit groups and the
The
Specifically, the
In this case, the bits constituting the bit group in
Returning to fig. 5, mapper blocks 12300, 12300-1, …, 12300-n map the FEC encoded and bit interleaved bits to complex-valued Quadrature Amplitude Modulation (QAM) constellation points. For the highest robustness level, Quadrature Phase Shift Keying (QPSK) is used. For higher order constellations (16-QAM up to 4096-QAM), non-uniform constellations are defined and the constellations are tailored for each code rate.
Each FEC frame should be mapped to an FEC block by first demultiplexing the input bits into parallel data unit words and then mapping these unit words into constellation values.
Fig. 8 is a block diagram for explaining a detailed configuration of the framing/interleaving block shown in fig. 1A.
As shown in fig. 8, the framing/
The inputs to the time interleaving block 14310 and the framing block 14320 may be comprised of M-PLPs, whereas the output of the framing block 14320 is OFDM symbols arranged in frames. The frequency interleaver included in the frequency interleaving block 14330 operates on OFDM symbols.
The Time Interleaver (TI) configuration included in the time interleaving block 14310 depends on the number of PLPs used. When there is only a single PLP or when LDM is used, a pure convolutional interleaver is used, and for a plurality of PLPs, a hybrid interleaver composed of a cell interleaver, a block interleaver, and a convolutional interleaver is used. The input to the time interleaving block 14310 is the stream of units output from the mapper block (fig. 5, 12300-1, …, 12300-n), and the output of the time interleaving block 14310 is also the stream of time interleaved units.
Fig. 9A shows a time interleaving block for a single PLP (S-PLP), and it is composed of only a convolutional interleaver.
Fig. 9B shows a time-interleaved block for multiple PLPs (M-PLPs), and it may be divided into several sub-blocks, as shown.
Framing block 14320 maps the interleaved frame onto at least one transmitter frame. Framing block 14320 specifically receives input (e.g., data units) from at least one physical layer lane and outputs symbols.
In addition, framing block 14320 creates at least one special symbol, referred to as a preamble symbol. These symbols undergo the same processing in the waveform blocks mentioned below.
Fig. 10 is a view illustrating an example of a transmission frame according to an exemplary embodiment.
As shown in fig. 10, the transmission frame is composed of three parts: bootstrap (bootstrap), preamble, and data payload. Each of the three parts is made up of at least one symbol.
In addition, the purpose of the frequency interleaving block 14330 is to ensure that persistent interference in a portion of the spectrum does not disproportionately degrade the performance of a particular PLP as compared to other PLPs. A frequency interleaver 14330, operating on all data units of one OFDM symbol, maps the data units from the framing block 14320 onto N data carriers.
Fig. 11 is a block diagram for explaining a detailed configuration of the waveform generation block shown in fig. 1A.
As shown in fig. 11, the
Pilot insertion block 14100 inserts pilots into various cells within an OFDM frame.
Various cells within an OFDM frame are modulated with reference information whose transmitted values are known to the receiver.
The unit containing the reference information is transmitted at a boosted power level. The cells are referred to as scattered pilot, continual pilot, edge pilot, preamble pilot, or frame tail pilot cells. The value of the pilot information is derived from a reference sequence, which is a series of values, one for each transmission carrier on any given symbol.
The pilot may be used for frame synchronization, frequency synchronization, time synchronization, channel estimation, transmission pattern identification, and may also be used to follow phase noise.
The pilots are modulated according to reference information, and a reference sequence is applied to all pilots (e.g., scattered pilots, continual pilots, edge pilots, preamble pilots, or tail pilots) in each symbol, including the preamble and tail symbols of the frame.
In addition to the preamble and tail symbols of the frame, reference information in the form of a reference sequence is transmitted in scattered pilot cells in each symbol.
In addition to the scattered pilots described above, a number of continuous pilots are inserted into each symbol of the frame except for the preamble and the end-of-frame symbols. The number and location of the continual pilots depends on the FFT size and scattered pilot pattern used.
MISO block 14200 applies MISO processing.
The transmit diversity code filter bank is a MISO predistortion technique that artificially decorrelates signals with multiple transmitters in a single frequency network, thereby minimizing potential destructive interference. A linear frequency domain filter is used so that compensation in the receiver can be implemented as part of the equalizer process. The filter design is based on creating all-pass filters with minimized cross-correlation across all filter pairs, subject to the constraints of the number of transmitters M E {2,3,4} and the time-domain span of the filters N E {64,256 }. A longer time domain span filter will increase the de-correlation level but the effective guard interval length will be reduced by the filter time domain span and this should be taken into account when selecting a filter bank for a particular network topology.
The IFFT block 14300 specifies the OFDM structure for each transmission mode. The transmitted signals are organized in frames. Each frame having a TFAnd by LFAn OFDM symbol. The N frames constitute a superframe. Each symbol is composed of a duration TSA set of transmitted KtotalAnd (3) a vector. Each symbol is formed by a symbol having a duration TUAnd a guard interval having a duration delta. Guard interval is extended by the period of the available part by TUConstructed and inserted before it.
The PAPR block 14400 applies a peak-to-average power reduction technique.
GI insertion block 14500 inserts a guard interval into each frame.
The boot block 14600 prepends a boot signal to the front of each frame.
Fig. 12 is a block diagram for explaining a configuration of signaling information according to an exemplary embodiment.
The
The n service data are mapped to
The
Fig. 13 shows a structure of a receiving apparatus according to an embodiment of the present invention.
The
The synchronization and
The
The demapping and
The
The signaling
Fig. 14 illustrates a synchronization and demodulation module according to an embodiment of the present invention.
As shown in fig. 14, the synchronization and
The
The
The ADC block 212000 may convert a signal output from the
The
The
When the apparatus 10000 for transmitting a broadcast signal has performed inverse waveform transformation, the
The time/
The
The
When the
The above blocks may be omitted or replaced by blocks having similar or identical functions, depending on the design.
Fig. 15 illustrates a frame parsing module according to an embodiment of the present invention.
As shown in fig. 15, the
The
The cell demapper 22200 can extract cells corresponding to common data, cells corresponding to data pipes, and cells corresponding to PLS data from the received signal frame. The unit demapper 22200 can combine the data of the scatter transmission and output the data as a stream if necessary. When two consecutive unit input data pieces are processed as a pair and mapped in the apparatus 10000 for transmitting a broadcast signal, the
In addition, the
The above blocks may be omitted or replaced by blocks having similar or identical functions, depending on the design.
Fig. 16 illustrates a demapping and decoding module according to an embodiment of the present invention.
The demapping and
The bit interleaving and coding and modulation module of the apparatus 10000 for transmitting a broadcast signal according to an embodiment of the present invention may process input data pipes by independently applying Single Input Single Output (SISO), MISO, and MIMO for respective paths, as described above. Accordingly, the demapping and
As illustrated in fig. 16, the demapping and
A description will be given of each block of the demapping and
The
The
The cell deinterleaver block 23120 may perform the inverse of the process performed by the cell interleaver block shown in fig. 9 b. That is, the
Cell-to-bit
The bit
The
The
The
The
The
The
The basic roles of the time deinterleaver block, the cell deinterleaver block, the constellation demapper block, the cell-to-bit multiplexer block, and the bit deinterleaver block included in the
The shortening/puncturing
The above blocks may be omitted or replaced by blocks having similar or identical functions, depending on the design.
The demapping and decoding module according to an embodiment of the present invention may output the data pipe and PLS information processed for the corresponding path to an output processor, as shown in fig. 16.
Fig. 17 and 18 illustrate an output processor according to an embodiment of the present invention.
FIG. 17 illustrates an
The
The BB scrambler block 24100 may descramble the input bitstream by generating the same PRBS as the device transmitting the broadcast signal uses for the input bitstream and performing an exclusive or operation on the PRBS and the bitstream.
The
The CRC-8
The BB
The above blocks may be omitted or replaced by blocks having similar or identical functions, depending on the design.
Fig. 18 shows an output processor according to another embodiment of the present invention. The
The
The de-jitter buffer block 2450 included in the output processor shown in fig. 18 can compensate for a delay for synchronizing a plurality of data pipes, which is inserted by a device transmitting a broadcast signal according to a recovered TTO (output time) parameter.
Referring to the restored DNP (delete null packet) and the output common data, the null
Based on ISCR (input stream time reference) information, the TS
The
The in-band signaling decoding block 24900 may decode and output the in-band physical layer signaling information transmitted over the padding bit field in each FEC frame of the data pipe.
The output processor shown in fig. 18 can perform BB descrambling on the pre-PLS information and the post-PLS information input through the PLS-pre path and the PLS-post path, respectively, and decode the descrambled data to recover the original PLS data. The recovered PLS data is transmitted to a system controller included in an apparatus for receiving a broadcast signal. The system controller may provide parameters required for a synchronization and demodulation module, a frame parsing module, a demapping and decoding module, and an output processor module of a device for receiving a broadcast signal.
The above blocks may be omitted or replaced by blocks having similar or identical functions, depending on the design.
Fig. 19 is a block diagram showing a configuration of a transmission apparatus according to an exemplary embodiment. Referring to fig. 19, the
The
Specifically, the
The LDPC codeword is formed of information word bits and parity bits. For example, LDPC codewords are composed of NldpcA number of bits formed and including KldpcNumber of information bits and Nparity=Nldpc-KldpcA number of parity bits.
In this case, the
For LDPC encoding, the
For example, the
Hereinafter, a parity check matrix according to various exemplary embodiments will be described in detail with reference to the accompanying drawings. In the parity check matrix, elements other than the element having 1 have 0.
For example, the parity check matrix according to an exemplary embodiment may have the configuration of fig. 20.
Referring to fig. 20, a parity check matrix 200 is formed of an information word submatrix (or information submatrix) 210 corresponding to information word bits and a parity submatrix 220 corresponding to parity bits.
The information word submatrix 210 includes KldpcA number of columns, and the parity-check submatrix 220 includes Nparity=Nldpc-KldpcThe number of columns. The number of rows of the parity check matrix 200 is the same as the number of columns of the sub-parity check matrix 220, Nparity=Nldpc-Kldpc。
Further, in the parity check matrix 200, NldpcIs the length of the LDPC codeword, KldpcIs the length of the information word bit, and Nparity=Nldpc-KldpcIs the length of the parity bit. The lengths of the LDPC codeword, the information word bits, and the parity bits refer to the number of bits included in each of the LDPC codeword, the information word bits, and the parity bits.
Hereinafter, the configuration of the information word submatrix 210 and the parity submatrix 220 will be described in detail.
The information word submatrix 210 includes KldpcNumber of columns (i.e., 0 th column to K th column)ldpcColumn-1) and the following rules are followed:
first, K of the information word submatrix 210ldpcM number of columns among the number of columns belong to the same group, and KldpcThe number of columns is divided into Kldpca/M number of column groups. In each column group, the column is cyclically shifted by Q from the adjacent previous columnldpc. Namely, QldpcMay be the value of a cyclic shift parameter on a column of the column groups of the information word submatrix 210 of the parity check matrix 200.
Here, M is a pattern letter of a column group including a plurality of columnsThe interval of repetition in the information sub-matrix 210 (e.g., M-360), and QldpcIs the size of a cyclic shift of one column from the adjacent previous column in the same column group in the information word submatrix 210. Further, M is NldpcAnd KldpcAnd is determined to satisfy Qldpc=(Nldpc-Kldpc) and/M. Here, M and QldpcIs an integer, and Kldpcand/M is also an integer. According to the length of LDPC codeword and code rate or Code Rate (CR) (or code rate), M and QldpcAnd may have various values.
For example, when M is 360 and the length N of the LDPC codewordldpcIs 64800, QldpcCan be defined as the
Code rate
Nldpc
M
Qldpc
5/15
64800
360
120
6/15
64800
360
108
7/15
64800
360
96
8/15
64800
360
84
9/15
64800
360
72
10/15
64800
360
60
11/15
64800
360
48
12/15
64800
360
36
13/15
64800
360
24
TABLE 1
Code rate
Nldpc
M
Qldpc
5/15
16200
360
30
6/15
16200
360
27
7/15
16200
360
24
8/15
16200
360
21
9/15
16200
360
18
10/15
16200
360
15
11/15
16200
360
12
12/15
16200
360
9
13/15
16200
360
6
TABLE 2
Second, when the ith column group (i ═ 0, 1., K)ldpc
wherein k is 0, 1,2i-1;i=0、1、...、
wherein k is 0, 1,2i-1;i=0、1、...、
In the above-described equation, the equation,
is the index of theTherefore, reference to these equations is only made in
When known, it is only possible to know the index of theAccording to the above rule, all columns belonging to the ith column group have the same order Di. Therefore, the LDPC codeword storing information on the parity check matrix according to the above rule can be simply expressed as follows.
For example, when N isldpcIs 30, KldpcIs 15 and QldpcAnd 3, the position information of the row in which 1 is located in the 0 th column of the three column groups can be represented by the sequence of
Wherein
Is the index of theThe weight-1 position sequence of
TABLE 3
Table 3 shows the positions of elements having a value of 1 in the parity check matrix, and the ith weight-1 position sequence is represented by an index of a row having 1 in the 0 th column belonging to the ith column group.
Based on the above description, the information word submatrix 210 of the parity check matrix according to an exemplary embodiment may be defined as in the following table 4 to table 12.
In particular, tables 4 to 12 show the index of 1 row located in
Herein, the index of a row having 1 in the 0 th column of the ith column group refers to "the address of the parity bit accumulator". The "address of the parity bit accumulator" has the same meaning as that defined in the DVB-C2/S2/T2 standard or the ATSC 3.0 standard being currently established, and thus, a detailed description thereof is omitted.
For example, when the LDPC code word is longDegree NldpcIs 16200, the code rate is 5/15 and M is 360, the index of the row with 1 in
TABLE 4
In another example, when the length of the LDPC codeword is NldpcIs 16200, the code rate is 7/15, and M is 360, the index of the row of 1 located in
i
1 index of a row located in
0
553 742 901 1327 1544 2179 2519 3131 3280 3603 3789 3792 4253 5340
5934 5962 6004 6698 7793 8001 8058 8126 8276 8559
1
503 590 598 1185 1266 1336 1806 2473 3021 3356 3490 3680 3936 4501
4659 5891 6132 6340 6602 7447 8007 8045 8059 8249
2
795 831 947 1330 1502 2041 2328 2513 2814 2829 4048 4802 6044 6109
6461 6777 6800 7099 7126 8095 8428 8519 8556 8610
3
601 787 899 1757 2259 2518 2783 2816 2823 2949 3396 4330 4494 4684
4700 4837 4881 4975 5130 5464 6554 6912 7094 8297
4
4229 5628 7917 7992
5
1506 3374 4174 5547
6
4275 5650 8208 8533
7
1504 1747 3433 6345
8
3659 6955 7575 7852
9
607 3002 4913 6453
10
3533 6860 7895 8048
11
4094 6366 8314
12
2206 4513 5411
13
32 3882 5149
14
389 3121 4625
15
1308 4419 6520
16
2092 2373 6849
17
1815 3679 7152
18
3582 3979 6948
19
1049 2135 3754
20
2276 4442 6591
TABLE 5
i
1 index of a row located in
0
432 655 893 942 1285 1427 1738 2199 2441 2565 2932 3201 4144 4419
4678 4963 5423 5922 6433 6564 6656 7478 7514 7892
1
220 453 690 826 1116 1425 1488 1901 3119 3182 3568 3800 3953 4071
4782 5038 5555 6836 6871 7131 7609 7850 8317 8443
2
300 454 497 930 1757 2145 2314 2372 2467 2819 3191 3256 3699 3984
4538 4965 5461 5742 5912 6135 6649 7636 8078 8455
3
24 65 565 609 990 1319 1394 1465 1918 1976 2463 2987 3330 3677
4195 4240 4947 5372 6453 6950 7066 8412 8500 8599
4
1373 4668 532 47777
5
189 3930 5766 6877
6
3 2961 4207 5747
7
1108 4768 6743 7106
8
1282 2274 2750 6204
9
2279 2587 2737 6344
10
2889 3164 7275 8040
11
133 2734 5081 8386
12
437 3203 7121
13
4280 7128 8490
14
619 4563 6206
15
2799 6814 6991
16
244 4212 5925
17
1719 7657 8554
18
53 1895 6685
19
584 5420 6856
20
2958 5834 8103
TABLE 6
In another example, when the length of the LDPC codeword is NldpcIs 16200, the code rate is 9/15, and M is 360, the index of the row of 1 existing in the 0 th column of the ith column group of the information word submatrix 210 is defined as the following table 7 or table 8.
i
1 index of a row located in
0
212 255 540 967 1033 1517 1538 3124 3408 3800 4373 4864 4905 5163
5177 6186
1
275 660 1351 2211 2876 3063 3433 4088 4273 4544 4618 4632 5548
6101 6111 6136
2
279 335 494 865 1662 1681 3414 3775 4252 4595 5272 5471 5796 5907
5986 6008
3
345 352 3094 3188 4297 4338 4490 4865 5303 6477
4
222 681 1218 3169 3850 4878 4954 5666 6001 6237
S
172 512 1536 1559 2179 2227 3334 4049 6464
6
716 93 41694 2890 3276 3608 4332 4468 5945
7
1133 1593 1825 2571 3017 4251 5221 5639 5845
8
1076 1222 6465
9
159 506 46078
10
374 4073 5357
11
2833 5526 5845
12
1594 3639 5419
13
1028 1392 4239
14
115 622 2175
15
300 1748 6245
16
2724 3276 5349
17
1433 6117 6448
18
485 663 4955
19
711 1132 4315
20
177 3266 4339
21
1171 4841 4682
22
33 1584 3692
23
2820 3485 4249
24
1716 2428 3125
25
250 2275 6338
26
108 1719 4961
TABLE 7
i
1 index of a row located in
0
350 462 1291 1383 1821 2235 2493 3328 3353 3772 3872 3923 4259
4426 4542 4972 5347 6217 6246 6332 6386
l
177 869 1214 1253 13981482 1737 2014 2161 2331 310 83297 3438 4388
4430 4456 4522 4783 5273 6037 6395
2
347 501 658 966 1622 1659 193 42117 2527 3168 3231 3379 3427 3739
4218 4497 4894 5000 5167 5728 5975
3
319 398 599 1143 1796 3198 3521 3886 4139 4453 4556 4636 4688 4753
4986 5199 5224 5496 5698 5724 6123
4
162 257 30 4524 945 1695 1855 2527 2780 2902 2958 3439 3484 4224
4769 4928 5156 5303 5971 6358 6477
S
807 1695 2941 4276
6
2652 2857 4660 6358
7
329 2100 2412 3632
8
1151 1231 3872 4869
9
1561 3565 513 85303
10
407 794 1455
11
3438 5683 5749
12
150 41985 3563
13
440 5021 6321
14
194 3645 5923
1S
1217 1462 6422
16
1212 4715 5973
17
4098 5100 5642
18
5512 5857 6226
19
2583 5506 5933
20
784 1801 4890
21
4734 4779 4875
22
938 5081 5377
23
127 4125 4704
24
124 42178 3352
25
3659 6350 6465
26
1686 346 44336
TABLE 8
In another example, when the length of the LDPC codeword is NldpcIs 16200, the code rate is 11/15, and M is 360, the index of the row of 1 existing in the 0 th column of the ith column group of the information word submatrix 210 is defined as the following table 9 or table 10.
i
1 index of a row located in
0
49 719 784 794 968 2382 2685 2873 2974 2995 3540 4179
1
272 281 374 1279 2034 2067 2112 3429 3613 3815 3838 4216
2
206 714 820 1800 1925 2147 2168 2769 2806 3253 3415 4311
3
62 159 166 605 1496 1711 2652 3016 3347 3517 3654 4113
4
363 733 1118 2062 2613 2736 3143 3427 3664 4100 4157 4314
5
57 142 436 983 1364 2105 2113 3074 3639 3835 4164 4242
6
870 921 950 1212 1861 2128 2707 2993 3730 3968 3983 4227
7
185 2684 3263
8
2035 2123 2913
9
883 2221 3521
10
1344 1773 4132
11
438 3178 3650
12
543 756 1639
13
1057 2337 2898
14
171 3298 3929
15
1626 2960 3503
16
484 3050 3323
17
2283 2336 4189
18
2732 4132 4318
19
225 2335 3497
20
600 2246 2658
21
1240 2790 3020
22
301 1097 3539
23
1222 1267 2594
24
1364 2004 3603
25
1142 1185 2147
26
564 1505 2086
27
697 991 2908
28
1467 2073 3462
29
2574 2818 3637
30
748 2577 2772
31
1151 1419 4129
32
164 1238 3401
TABLE 9
i
1 index of a row located in
0
108 297 703 742 1345 1443 1495 1628 1812 2341 2559 2669 2810 2877
3442 3690 3755 3904 4264
1
180 211 477 788 824 1090 1272 1578 1685 1948 2050 2195 2233 2546
2757 2946 3147 3299 3544
2
627 741 1135 1157 1226 1333 1378 1427 1454 1696 1757 1772 2099
2208 2592 3354 3580 4066 4242
3
9 795 959 989 1006 1032 1135 1209 1382 1484 1703 18551985 2043
2629 2845 3136 3450 3742
4
230 413 801 829 1108 1170 1291 1759 1793 1827 1976 2000 2423 2466
2917 3010 3600 3782 4143
5
56 142 236 381 1050 1141 1372 1627 1985 2247 2340 3023 3434 3519
3957 4013 4142 4164 4279
6
298 1211 2548 3643
7
73 1070 1614 1748
8
1439 2141 3614
9
284 1564 2629
10
607 660 855
11
1195 2037 2753
12
49 1198 2562
13
296 1145 3540
14
1516 2315 2382
15
154 722 4016
16
759 2375 3825
17
162 194 1749
18
2335 2422 2632
19
6 1172 2583
20
726 1325 1428
21
985 2708 2769
22
255 2801 3181
23
2979 3720 4090
24
208 1428 4094
25
199 3743 3757
26
1229 2059 4282
27
458 1100 1387
28
1199 2481 3284
29
1161 1467 40060
30
959 3014 4144
31
2666 3960 4125
32
2809 3834 4318
Watch 10
In another example, when the length of the LDPC codeword is NldpcIs 16200, the code rate is 13/15, and M is 360, the index of the row of 1 existing in the 0 th column of the ith column group of the information word submatrix 210 is defined as the following table 11 or table 12.
i
1 index of a row located in
0
71 334 645 779 786 1124 1131 1267 1379 1554 1766 1798 1939
1
6 183 36 4506 512 922 972 981 1039 1121 1537 1840 2111
2
6 71 153 204 253 268 781 799 873 1118 1194 1661 2036
3
6 247 353 581 921 940 1108 1146 1208 1268 1511 1527 1671
4
6 37 466 548 747 1142 1203 1271 1512 1516 1837 1904 2125
5
6 171 863 953 1025 1244 1378 1396 1723 1783 1816 1914 2121
6
126 81360 1647 1769
7
6 458 1231 1414
8
183 535 1244 1277
9
107 360 498 1456
10
6 2007 2059 2120
11
1480 1523 1670 1927
12
139 573 711 1790
13
6 1541 1889 2023
14
6 374 957 1174
15
287 423 872 1285
16
6 1809 1918
17
65 818 1396
18
590 766 2107
19
192 814 1843
20
775 1163 1256
21
42 735 1415
22
334 1008 2055
23
109 596 1785
24
406 534 1852
25
684 719 1543
26
401 465 1040
27
112 392 621
28
82 897 1950
29
887 1962 2125
30
793 1088 2159
31
723 919 1139
32
610 839 1302
33
218 1080 1816
34
627 1646 1749
35
496 1165 1741
36
916 1055 1662
37
182 722 945
38
5 595 1674
TABLE 11
i
1 index of a row located in column 0 of the ith column group
0
37 144 161 199 220 496 510 589 731 808 834 965 1249 1264 1311
1377 1460 1520 1598 1707 1958 2055 2099 2154
1
20 27 165 462 546 583 742 796 1095 1110 1129 1145 11691190 1254
1363 1383 1463 1718 18351 870 1879 2108 2128
2
288 362 463 505 638 691 745 861 1006 1083 1124 1175 12471275 1337
1353 1378 1506 1588 1632 1720 1868 1980 2135
3
405 464 478 511 566 574 641 766 785 802 836 996 112812391247 1449
1491 1537 1616 1643 1668 1950 1975 2149
4
86 192 245 357 363 374 700 713 852 903 992 1174 1245 1277 1342
1369 1381 1417 1463 1712 1900 1962 2053 2118
5
101 327 378 550
6
186 723 1318 1550
7
118 277 504 1835
8
199 407 1776 1965
9
387 1253 1328 1975
10
62 144 1163 2017
11
100 475 572 2136
12
431 865 1568 2055
13
283 640 981 1172
14
220 1038 1903 2147
15
483 1318 1358 2118
16
92 961 1709 1810
17
112 403 1485 2042
18
431 1110 1130 1365
19
587 1005 1206 1588
20
704 1113 1943
21
3751487 2100
22
1507 1950 2110
23
962 1613 2038
24
554 1295 1501
25
488 784 1446
26
871 1935 1964
27
54 1475 1504
28
1579 1617 2074
29
1856 1967 2131
30
330 1582 2107
31
40 1056 1809
32
1310 1353 1410
33
232 554 1939
34
168 641 1099
35
333 437 1556
36
153 622 745
37
719 931 1188
38
237 638 1607
TABLE 12
In the above example, the length of the LDPC codeword is 16200, and the code rates are 5/15, 7/15, 9/15, 11/15, and 13/15. However, this is merely an example, and when the length of the LDPC codeword is 64800 or the code rate has different values, the position of 1 in the information word submatrix 210 may be defined differently.
In addition, even when the numerical order of sequences corresponding to the ith column group of the parity check matrix 200 as shown in tables 4 to 12 described above is changed, the changed parity check matrix is a parity check matrix for the same code. Thus, the inventive concept covers the following cases: the numerical order of the sequences corresponding to the ith column group in tables 4 to 12 is changed.
According to an exemplary embodiment, even when the arrangement order of the sequences corresponding to each column group is changed in tables 4 to 12, the cyclic characteristic and the algebraic characteristic (such as order distribution) on the graph of the code are not changed. Therefore, the concept of the present invention also covers the case where the arrangement order of the sequences shown in tables 4 to 12 is changed.
In addition, even at multiple Q' sldpcWhen the same is added to all sequences corresponding to a certain column group in tables 4 to 12, a cyclic characteristic or an algebraic characteristic (such as an order distribution) on a graph of the code does not change. Thus, the inventive concept also contemplates combining multiple QsldpcResults of equivalent additions to the sequences shown in tables 4 to 12. However, it should be noted that when multiple Qs are passed throughldpcThe resulting value obtained by addition to a given sequence is greater than or equal to (N)ldpc-Kldpc) Instead, the method should be applied by applying the result value for (N)ldpc-Kldpc) A modulo operation of (a).
Once the positions of the rows where 1 exists in the 0 th column of the ith column group of the information word submatrix 210 are defined as in tables 4 to 12, the positions of the rows where 1 exists in the other columns of each column group can be defined because the positions of the rows where 1 exists in the 0 th column are cyclically shifted by Q in the next columnldpc。
For example, in the case of table 4, in
In this case, Q is due toldpc=(Nldpc-Kldpc) Thus, the index of 1 row located in
In the above method, an index of 1 row located in all rows of each column group may be defined.
The sub-parity check matrix 220 of the parity check matrix 200 shown in fig. 20 may be defined as follows:
the parity submatrix 220 includes Nldpc-KldpcColumn (i.e., K th)ldpcColumn to NthlpdcColumn-1) and has a double diagonal or step configuration. Thus, parityExcept the last column (i.e., nth column) among the columns included in the syndrome matrix 220lpdc-1 column) is 2 and the order of the last column is 1.
Accordingly, the information word submatrix 210 of the parity check matrix 200 may be defined by tables 4 to 12, and the parity submatrix 220 of the parity check matrix 200 may have a dual diagonal configuration.
When the columns and rows of the parity check matrix 200 shown in fig. 20 are permuted based on equations 4 and 5, the parity check matrix shown in fig. 20 may become the parity check matrix 300 shown in fig. 21.
The method for permutation based on equations 4 and 5 will be described below. Since the same principle is applied to the row permutation and the column permutation, the row permutation is explained as an example.
In the case of line replacement, for the X-th line, the calculation satisfies X ═ QldpcI and j of X i + j, and the X-th row is replaced by assigning the calculated i and j to M X j + i. For example, for row 7, i and j satisfying 7 ═ 2 × i + j are 3 and 1, respectively. Thus, row 7 is permuted to row 13 (10 × 1+3 — 13).
When the row permutation and the column permutation are performed as described above, the parity check matrix of fig. 20 may be converted into the parity check matrix of fig. 21.
Referring to fig. 21, the parity check matrix 300 is divided into a plurality of partial blocks, and an M × M quasi-cyclic matrix corresponds to each partial block.
Accordingly, the parity check matrix 300 having the configuration of fig. 21 is formed of M × M matrix cells. That is, M × M submatrices are arranged into a plurality of partial blocks constituting the parity check matrix 300.
Since the parity check matrix 300 is formed of an M × M quasi-cyclic matrix, M columns may be referred to as a column block and M rows may be referred to as a column blockReferred to as row blocks. Accordingly, the parity check matrix 300 having the configuration of fig. 21 is represented by Nqc_column=Nldpca/M number of column blocks and Nqc_row=Nparityand/M line blocks.
The M × M sub-matrix will be described below.
Nth of first, 0 th row blockqc_columnColumn-1 block a (330) has the form shown in equation 6 below.
As described above, A330 is an M matrix, the values in both the 0 th row and the M-1 th column are "0", and for 0. ltoreq. i.ltoreq.M-2, the i +1 th row of the i-th column is "1" and the other values are "0".
Second, for 0 ≦ i ≦ (N) in the parity-check submatrix 320ldpc-Kldpc) (ii)/M-1, KldpcIth row block of/M + I column block is
Third, the
For example, the format of block P350 may be expressed by equation 7 presented below, where in
The circulant matrix P is a rectangular matrix having a size of M by M, and is a weight of 1 for each of M rows and M columnsThe weight of each column is a matrix of 1. When a isijWhen 0, the circulant matrix P (i.e., P)0) Representing a matrix of cells IM×M. In addition, for convenience of illustration, when aijIs ∞ time, P∞Is defined as a zero matrix.
The submatrix existing where the ith row block and the jth column block are crossed in the parity check matrix 300 of fig. 21 may be
Thus, i and j indicate the number of row blocks and the number of column blocks in the partial block corresponding to the information word. Thus, in the parity check matrix 300, the total number of columns is Nldpc=M×Nqc_columnAnd the total number of rows is Nparity=M×Nqc_row. That is, the parity check matrix 300 is composed of Nqc_columnA column block and Nqc_rowA "row block" is formed.A method of performing LDPC encoding based on the parity check matrix 200 shown in fig. 20 will be described below. For convenience of explanation, the parity check matrix 200 is defined as an LDPC encoding process as shown in table 4 as an example.
First, when having a length of KldpcThe information word isAnd has a length Nldpc-KldpcIs a parity bit of
LDPC encoding is performed by the following procedure.Step 1) initializes the parity bit to '0'. That is to say that the first and second electrodes,
step 2) the 0 th information word bit i0The parity bit having the address of the parity bit defined in the first row of table 4 (i.e., the row where i ═ 0) as the index of the parity bit is accumulated. This can be expressed by the following equation 8:
Here, i0Is the 0 th information word bit, piIs the ith parity bit, and
is a binary operation. According to the binary operation, the operation is carried out,is equal to 0 and is equal to 0,equal to 1, and is,equal to 1, and is,equal to 0.Step 3) other 359 information word bits im(m-1, 2, …,359) is accumulated in the parity bits. Other information word bits may belong to the same as0In the same column group. In this case, the address of the parity bit may be determined based on the following equation 9.
(x+(mmod360)×Qldpc)mod(Nldpc-Kldpc)…(9)
Where x is the bit i corresponding to the information word0The address of the parity bit accumulator, and QldpcIs the size of the cyclic shift of each column in the information word sub-matrix and may be 108 in the case of table 4. Further, (m mod360) in equation 9 can be regarded as m since m is 1,2, …, 359.
Thus, the information word bit im(m-1, 2, … 359) is accumulated in the parity bit having the address of the parity bit calculated based on equation 9 as an index. E.g. for information word bit i1The operation as shown in the following equation 10 may be performed:
here, i1Is the 1 st information word bit, piIs the ith parity bit, and
is a binary operation. According to the binary operation, the operation is carried out,is equal to 0 and is equal to 0,equal to 1, and is,equal to 1, and is,equal to 0.Step 4) converting the 360 th information word bit i360The parity bit having the address of the parity bit defined in the 2 nd row (i.e., the row where i is 1) of table 4 as an index thereof is accumulated.
Step 5) will belong to and information word bit i360The other 359 information word bits of the same group are accumulated in the parity bits. In this case, the address of the parity bit may be determined based on equation 9. However, in this case, x is the bit i corresponding to the information word360The address of the parity bit accumulator.
Step 6) the above steps 4 and 5 are repeated for all column groups of table 4.
Step 7) accordingly, the parity bit p is calculated based on the following equation 11i. In this case, i is initialized to 1.
In equation 11, piIs the ith parity bit, NldpcIs the length of the LDPC codeword, KldpcIs the length of an information word of an LDPC codeword, and
is a binary operation.Accordingly, the
In another example, the parity check matrix according to an exemplary embodiment may have a configuration as shown in fig. 22.
Referring to fig. 22, the parity check matrix 400 may be formed of 5 matrices A, B, C, Z and D. The configuration of each matrix will be explained below to explain the configuration of the parity check matrix 400.
First, a parameter value M associated with a parity check matrix 400 as shown in fig. 22 according to the length and code rate of an LDPC codeword1、M2、Q1And Q2Can be defined as the following list 13.
Watch 13
Matrix A is formed of K columns and g rows, and matrix C is formed of K + g columns and N-K-g rows. Here, K is the length of the information word bits, and N is the length of the LDPC codeword.
According to the length and code rate of the LDPC codeword, an index of 1 row located in the 0 th column of the ith column group in the matrix a and the matrix C may be defined based on the table 14. In this case, the interval at which the pattern of columns repeats in each of the matrix a and the matrix C (i.e., the number of columns belonging to the same group) may be 360.
For example, when the length N of the LDPC codeword is 16200 and the code rate is 5/15, the index of a row of 1 located in the 0 th column of the ith column group in the matrix a and the matrix C is defined as the following list 14:
i
1 index of a row located in
0
69 244 706 5145 5994 6066 6763 6815 8509
1
257 541 618 3933 6188 7048 7484 8424 9104
2
69 500 536 1494 1669 7075 7553 8202 10305
3
11 189 340 2103 3199 6775 7471 7918 10530
4
333 400 434 1806 3264 5693 8534 9274 10344
5
111 129 260 3562 3676 3680 3809 5169 7308 8280
6
100 303 342 3133 3952 4226 4713 5053 5717 9931
7
83 87 374 828 2460 4943 6311 8657 9272 9571
8
114 166 325 2680 4698 7703 7886 8791 9978 10684
9
281 542 549 1671 3178 3955 7153 7432 9052 10219
10
202 271 608 3860 4173 4203 5169 6871 8113 9757
11
16 359 419 3333 4198 4737 6170 7987 9573 10095
12
235 244 584 4640 5007 5563 6029 6816 7678 9968
13
123 449 646 2460 3845 4161 6610 7245 7686 8651
14
136 231 468 835 2622 3292 5158 5294 6584 9926
15
3085 4683 8191 9027 9922 9928 10550
16
2462 3185 3976 4091 8089 8772 9342
TABLE 14
In the above example, the length of the LDPC codeword is 16200 and the code rate is 5/15. However, this is merely an example, and when the length of the LDPC codeword is 64800 or the code rate has different values, the index of a row whose 1 is located in the 0 th column of the ith column group in the matrix a and the matrix C may be defined differently.
The positions of rows where 1 exists in matrix a and matrix C will be explained below by way of example with reference to table 14.
Due to the fact thatIn table 14, the length of the LDPC codeword is 16200 and the code rate is 5/15, and thus, referring to table 13, in the parity check matrix 400 defined by table 14, M1=720、M2=10080、Q12 and Q2=28。
In this context, Q1Is the size of a cyclic shift of columns of the same column group in matrix A, and Q2Is the size of the cyclic shift of the columns of the same column group in the matrix C.
Further, Q1=M1/L、Q2=M2/L、M1G and M2N-K-g, and L is the interval at which the pattern of columns repeats in matrix a and matrix C, which may be 360, for example
The index of 1 row in matrix A and matrix C may be based on M1And (4) determining the value.
For example, since in the case of Table 14, M1Accordingly, the position of a row of 1 existing in the 0 th column of the ith column group in the matrix a may be determined based on a value smaller than 720 among the index values of the table 14, and the position of a row of 1 existing in the 0 th column of the ith column group in the matrix C may be determined based on a value greater than or equal to 720 among the index values of the table 14.
Specifically, in table 14, the sequences corresponding to the 0 th column group are "69, 244, 706, 5145, 5994, 6066, 6763, 6815, and 8509". Thus, in the case of the 0 th column group in the matrix a, 1 may be located at the 69 th row, the 244 th row and the 706 th row, and in the case of the 0 th column group in the matrix C, 1 may be located at the 5145 th row, the 5994 th row, the 6066 th row, the 6763 th row, the 6815 th row and the 8509 th row.
Once the position of 1 in the 0 th column of each column group in matrix A is defined, Q is cyclically shifted from the previous column1The position of a row having 1 in the other column of each of the column groups may be defined. Once the position of 1 in the 0 th column of each column group in the matrix C is defined, Q is cyclically shifted from the previous column2The position of a row having 1 in the other column of each of the column groups may be defined.
In the above example, in the 0 th column of the 0 th column group of the
In the case of
In this method, the positions of rows where 1 exists in all column groups of matrix a and matrix C are defined.
Matrix B may have a dual diagonal configuration, matrix D may have a diagonal configuration (i.e., matrix D is an identity matrix), and matrix Z may be a zero matrix.
Accordingly, the parity check matrix 400 shown in fig. 22 may be defined by the matrices A, B, C, D and Z having the above-described configuration.
A method of performing LDPC encoding based on the parity check matrix 400 shown in fig. 22 will be described below. For convenience of explanation, the LDPC encoding process when the parity check matrix 400 is defined as in table 14 is explained as an example.
For example, when the information block S ═ S (S)0,s1,…,SK-1) When LDPC coded, parity bits may be generated
LDPC code wordM1And M2Respectively represent havingThe size of the matrix B in a dual diagonal arrangement and the size of the matrix C with a diagonal arrangement, and M1=g、M2=N-K-g。
The process of calculating the parity bits is as follows. In the following description, for convenience of explanation, the parity check matrix 400 is defined as table 14 as an example.
Step 1) initializing λ and p to λi=si(i=0,1,…,K-1)、pj=0(j=0,1,…,M1+M2-1)。
Step 2) the 0 th information word position lambda0Accumulated in the address of the parity bit defined in the first row (i.e., the row where i ═ 0) of the table 14. This can be represented by the following equation 12:
step 3) for the next L-1 number of information word bits lambdam(m-1, 2, …, L-1), converting λ into a linear formmAccumulated in the parity bit address calculated based on the following equation 13:
(χ+m×Q1)modM1(if χ < M)1)
M1+{(χ-M1+m×Q2)modM2(if χ ≧ M)1)…(13)
Here, x is the word position λ corresponding to the 0 th information word0The address of the parity bit accumulator.
Further, Q1=M1L and Q2=M2And L. Further, since the length N of the LDPC codeword is 16200 and the code rate is 5/15 in table 14, referring to table 13, M1=720,M2=10080,Q1=2,Q228 and L360.
Thus, for the 1 st information word bit λ1The operation shown in the following equation 14 may be performed:
step 4) because of the L-th information word bit lambdaLThe address of the same parity bit as in the second row (i.e., the row where i ═ 1) of table 14 is given in a similar manner to the above-described method, and therefore, the address is calculated based on equation 13 for the next L-1 information word bits λm(m ═ L +1, L +2, …,2L-1) parity bit address. In this case, x is the number corresponding to the information word bit λLAnd may be obtained based on the second row of table 14.
Step 5) the above process is repeated for the L new information word bits of each bit group by treating the new row of the table 14 as the address of the parity bit accumulator.
Step 6) aiming at code word position lambda0To lambdaK-1After repeating the above process, values with respect to the following equation 15 are sequentially calculated from i ═ 1:
step 7) calculates a parity bit λ corresponding to the matrix B having a dual diagonal configuration based on the following equation 16KTo
Step 8) calculate L new codeword bits λ for each group based on Table 14 and equation 13KToThe address of the parity bit accumulator.
Step 9) in calculating code word bit lambdaKTo
Thereafter, parity bits corresponding to the matrix C having the diagonal line configuration are calculated based on the following equation 17To
Thus, the parity bits may be calculated according to the above-described method.
Referring back to fig. 19, the
In this case, the
In addition, the
In this case, the
The
Specifically, the
To this end, as shown in fig. 23, the
The parity interleaver 121 interleaves the parity bits constituting the LDPC codeword.
Specifically, when the LDPC codeword is generated based on the parity check matrix 200 having the configuration of fig. 20, the
ui=ci for 0≤i<Kldpcand an
Where M is an interval at which the pattern of column groups is repeated in the information word submatrix 210, that is, the number of columns included in the column groups (for example, M-360), and QldpcIs the size of the cyclic shift of each column in the information word sub-matrix 210. That is, the
The LDPC codeword subjected to parity interleaving in the above-described method may be configured such that a predetermined number of consecutive bits of the LDPC codeword have similar decoding characteristics (a cyclic characteristic or a distribution of columns, etc.).
For example, the LDPC codeword may have the same characteristics based on M consecutive bits. Here, M is an interval at which the pattern of column groups is repeated in the information word submatrix 210, and may be 360, for example.
Specifically, the product of the LDPC codeword bits and the parity check matrix should be "0". This means that the ith LDPC codeword bit ci(i=0,1,…,Nldpc-1) the sum of the products with the ith column of the parity check matrix should be a "0" vector. Therefore, the ith LDPC codeword bit can be regarded as corresponding to the ith column of the parity check matrix.
In the case of the parity check matrix 200 of fig. 20, M columns in the information word submatrix 210 belong to the same group, and the information word submatrix 210 has the same characteristic based on column groups (e.g., columns belonging to the same column group have the same order distribution and the same cyclic characteristic).
In this case, since M consecutive bits of the information word bits correspond to the same column group of the information word submatrix 210, the information word bits may be formed of M consecutive bits having the same codeword characteristics. When the parity bits of the LDPC codeword are interleaved by the
However, parity bit interleaving may not be performed for LDPC codewords encoded based on the parity check matrix 300 of fig. 21 and the parity check matrix 400 of fig. 22. In this case, the
The group interleaver 122 may divide the parity-check-bit-interleaved LDPC codeword into a plurality of bit groups and rearrange the order of the plurality of bit groups by bit group (or in units of bit groups). That is, the
To this end, the
Xj={uk|360×j≤k<360×(j+1),0≤k<Nldpc}for0≤j<Ngroup…(20)
Wherein N isgroupIs the total number of bit groups, XjIs the jth bit group, and ukIs the k-th LDPC codeword bit input to the
Since 360 in these equations represents an example of the spacing M at which the pattern of column groups is repeated in the information word submatrix, 360 in these equations may be changed to M.
The LDPC codeword divided into a plurality of bit groups may be as shown in fig. 24.
Referring to fig. 24, an LDPC codeword is divided into a plurality of bit groups, and each bit group is formed of M consecutive bits. When M is 360, each bit group of the plurality of bit groups may be formed of 360 bits. Thus, the bit group may be formed of bits corresponding to a column group of the parity check matrix.
In particular, since the LDPC codeword is divided by M consecutive bits, KldpcAn information word bit is divided into Kldpca/M bit groups and Nldpc-KldpcThe parity check bits are divided into (N)ldpc-Kldpc) the/M bit groups. Accordingly, the LDPC codeword may be divided into N in totalldpcthe/M bit groups.
For example, when M is 360 and the length N of the LDPC codewordldpc16200 hours, the number of groups N constituting the LDPC codewordgroupsIs 45(═ 16200/360), and when M is 360 and the length N of the LDPC codeword is Nldpc64800, the number of groups N constituting the LDPC codewordgroupsIs 180(═ 64800/360).
As described above, the
In the above example, the number of bits constituting each bit group is M. However, this is merely an example, and the number of bits constituting each bit group is variable.
For example, the number of bits making up each bit group may be an integer division of M. That is, the number of bits constituting each bit group may be an integer division of the number of columns of a column group of an information word submatrix constituting the parity check matrix. In this case, each bit group may be formed of an integer division of M bits. For example, when the number of columns of a column group constituting the information word submatrix is 360, i.e., M is 360, the
In the following description, for convenience of explanation, the number of bits constituting a bit group is M as an example.
Thereafter, the
Here, the
In this case, the
To this end, the
Yj=Xπ(j)(0≤j<Ngroup)…(21),
wherein XjIs the jth bit group before group interleaving, and YjIs the jth bit group after group interleaving. Also, pi (j) is a parameter representing an interleaving order, and is determined based on at least one of a length of the LDPC codeword, a modulation method, and a code rate. That is, pi (j) indicates the permutation order of interleaving by group.
Thus, Xπ(j)Is the pi (j) -th bit group (or block) before the group interleaving, and equation 21 means thatThe pi (j) th bit group before the group interleaving is interleaved into the j th bit group.
According to an exemplary embodiment, examples of π (j) may be defined as the following tables 15 through 27.
In this case, pi (j) is defined according to the length and code rate of the LPDC codeword, and the parity check matrix is also defined according to the length and code rate of the LPDC codeword. Accordingly, when LDPC encoding is performed based on a specific parity check matrix according to the length and code rate of an LDPC codeword, the LDPC codeword may be bit group-wise interleaved based on pi (j) satisfying the corresponding length and code rate of the LDPC codeword.
For example, when the
For example, when the length of the LDPC codeword is 16200, the code rate is 5/15, and the modulation method (or modulation format) is 16 Quadrature Amplitude Modulation (QAM), pi (j) may be defined as the following list 15. Specifically, when LDPC encoding is performed based on the parity check matrix defined by table 14, table 15 may be applied.
Watch 15
In the case of table 15, equation 21 may be expressed as Y0=Xπ(0)=X3、Y1=Xπ(1)=X33、Y2=Xπ(2)=X39、…、Y43=Xπ(43)=X35、Y44=Xπ(44)=X27. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 7/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 16. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 5, table 16 may be applied.
TABLE 16
In the case of table 16, equation 21 may be expressed as Y0=Xπ(0)=X20、Y1=Xπ(1)=X13、Y2=Xπ(2)=X11、…、Y43=Xπ(43)=X1、Y44=Xπ(44)=X38. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 9/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 17. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 7, table 17 may be applied.
TABLE 17
In the case of table 17, equation 21 may be expressed as Y0=Xπ(0)=X17、Y1=Xπ(1)=X8、Y2=Xπ(2)=X7、…、Y43=Xπ(43)=X1And Y44=Xπ(44)=X21. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 11/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 18. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 9, table 18 may be applied.
Watch 18
In the case of table 18, equation 21 may be expressed as Y0=Xπ(0)=X21、Y1=Xπ(1)=X23、Y2=Xπ(2)=X5、…、Y43=Xπ(43)=X16、Y44=Xπ(44)=X30. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 13/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 19. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 11, table 19 may be applied.
Watch 19
In the case of table 19, equation 21 may be expressed as Y0=Xπ(0)=X4、Y1=Xπ(1)=X13、Y2=Xπ(2)=X8、…、Y43=Xπ(43)=X24、Y44=Xπ(44)=X38. Thus, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 5/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 20. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 4, table 20 may be applied.
Watch 20
In the case of table 20, equation 21 may be expressed as Y0=Xπ(0)=X5、Y1=Xπ(1)=X20、Y2=Xπ(2)=X9、…、Y43=Xπ(43)=X39、Y44=Xπ(44)=X29. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 7/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 21. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 6, table 21 may be applied.
TABLE 21
In the case of table 21, equation 21 may be expressed as Y0=Xπ(0)=X18、Y1=Xπ(1)=X16、Y2=Xπ(2)=X13、…、Y43=Xπ(43)=X34、Y44=Xπ(44)=X38. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 9/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 22. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 8, table 22 may be applied.
TABLE 22
In the case of table 22, equation 21 may be expressed as Y0=Xπ(0)=X20、Y1=Xπ(1)=X14、Y2=Xπ(2)=X13、…、Y43=Xπ(43)=X43、Y44=Xπ(44)=X44. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 11/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 23. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 10, table 23 may be applied.
TABLE 23
In the case of table 23, equation 21 may be expressed as Y0=Xπ(0)=X15、Y1=Xπ(1)=X10、Y2=Xπ(2)=X5、…、Y43=Xπ(43)=X30、Y44=Xπ(44)=X31. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 13/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 24. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 12, table 24 may be applied.
Watch 24
In the case of table 24, equation 21 may be expressed as Y0=Xπ(0)=X4、Y1=Xπ(1)=X11、Y2=Xπ(2)=X1、…、Y43=Xπ(43)=X28、Y44=Xπ(44)=X29. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 7/15, and the modulation method is 256-QAM, pi (j) may be defined as the following list 25. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 6, table 25 may be applied.
TABLE 25
In the case of table 25, equation 21 may be expressed as Y0=Xπ(0)=X39、Y1=Xπ(1)=X18、Y2=Xπ(2)=X33、…、Y43=Xπ(43)=X34、Y44=Xπ(44)=X44. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 9/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 26. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 7, table 26 may be applied.
Watch 26
In the case of table 26, equation 21 may be expressed as Y0=Xπ(0)=X17、Y1=Xπ(1)=X8、Y2=Xπ(2)=X7、…、Y43=Xπ(43)=X1、Y44=Xπ(44)=X21. Accordingly, the
In another example, when the length of the LDPC codeword is 16200, the code rate is 9/15, and the modulation method is 16-QAM, pi (j) may be defined as the following list 27. Specifically, when LDPC encoding is performed based on the parity check matrix defined in table 8, table 27 may be applied.
Watch 27
In the case of table 27, equation 21 may be expressed as Y0=Xπ(0)=X4、Y1=Xπ(1)=X14、Y2=Xπ(2)=X13、…、Y43=Xπ(43)=X43、Y44=Xπ(44)=X3. Accordingly, the
In the above example, the length of the LDPC codeword is 16200, and the code rates are 5/15, 7/15, 9/15, 11/15, and 13/15. However, they are merely examples, and when the length of the LDPC codeword is 64800 or the code rate has different values, the interleaving pattern may be defined differently.
As described above, the
The "jth block of packet interleaver output" in tables 15 to 27 represents the jth bit group output from the
Further, since the order of the bit groups constituting the LDPC codeword is rearranged by the
The LDPC codeword subjected to the group interleaving in the above method is shown in fig. 25. Comparing the LDPC codeword of fig. 25 with the LDPC codeword of fig. 24 before the group interleaving, it can be seen that the order of the plurality of bit groups constituting the LDPC codeword is rearranged.
That is, as shown in fig. 24 and 25, groups of LDPC codewords are arranged in groups of bits X before group interleaving0Group of bits X1… bit set XNgroup-1And according to the bit group Y after the group interleaving0Group of bits Y1… bit set YNgroup-1Are arranged in the order of (a). In this case, the order of arranging the bit groups by group interleaving may be determined based on tables 15 to 27.
The
In this case, the
For example, as shown in FIG. 26,
In addition, the
For example,
However, the above-described set of
Further, in the above example, the
The
In this case, the
Specifically, the
Here, the number of bit groups interleaved per bit group may be determined by at least one of the number of rows and columns constituting the
In addition, interleaving the bit groups by bit groups means that bits included in the same bit group are written in the same column. In other words, if the bit groups are interleaved in bit groups, the
Therefore, the number of rows constituting the first part is a multiple of the number of bits included in one bit group (for example, 360), and the number of rows constituting the second part may be smaller than the number of bits included in one bit group.
Further, in all the bit groups interleaved by the first section, bits included in the same bit group are written in the same column of the first section for interleaving, and in at least one group interleaved by the second section, bits are separated and written in at least two columns of the second section.
A specific interleaving method will be described below.
In addition, by interleaving, the
As described above, the
In this case, the
In this case, the
If the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns constituting the
Specifically, the
In this case, the
Hereinafter, the bit group located at the j-th position after being interleaved by the
For example, assume that the
In this case, when N of LDPC codeword is formed bygroupThe quotient of a bit group divided by the C columns forming the
For example, as shown in FIG. 27, a
Thus, the
However, when the number of bit groups of the LDPC codeword is not an integer multiple of the number of columns of the
Specifically, the
In this case, the
Here, each bit group of the plurality of bit groups may be formed of 360 bits. Further, the number of bit groups of the LDPC codeword is determined based on the length of the LDPC codeword and the number of bits included in the bit groups. For example, when an LDPC codeword having a length of 16200 is divided such that each bit group has 360 bits, the LDPC codeword is divided into 45 bit groups. Alternatively, when the LDPC codeword having a length of 64800 is divided such that each bit group has 360 bits, the LDPC codeword may be divided into 180 bit groups. In addition, the number of columns constituting the
Accordingly, the number of rows constituting each of the first part and the second part may be determined based on the number of columns constituting the
Specifically, in each of the plurality of columns, the first part may be formed of as many rows as the number of bits included in at least one bit group that may be written in each column in terms of bit groups among the plurality of bit groups of the LDPC codeword, according to the number of columns constituting the
In each of the plurality of columns, the second part may be formed of rows other than as many rows as the number of bits included in at least some of the bit groups that may be written in each of the plurality of columns in bit groups. Specifically, the number of rows of the second part may be the same value as a quotient obtained when the number of bits included in all bit groups except the bit group corresponding to the first part is divided by the number of columns constituting the
That is, the
Thus, the first part may be formed of as many rows as the number of bits included in the bit group (i.e., as many rows as an integer multiple of M). However, as described above, since the number of codeword bits constituting each bit group may be an integer division part of M, the first part may be formed of as many rows as an integer multiple of the number of bits constituting each bit group.
In this case, the
Specifically, the
That is, the
In this case, the
Specifically, the
That is, the
In this case, the
Specifically, the
That is, the
For example, assume that the
In this case, as shown in fig. 28 and 29, the
That is, in the above-described example, the number of bit groups that can be written in each column in bit groups is a, and the first part of each column may be formed of as many rows as the number of bits included in the a bit group, that is, may be formed of as many rows as the a × M number.
In this case, the
That is, as shown in FIGS. 28 and 29, the
As described above, the
In other words, in the above exemplary embodiment, the bit group (Y)0) Group of bits (Y)1) …, positionGroup (Y)A-1) May not be divided and all bits may be written to the first column, the bit group (Y)A) Group of bits (Y)A+1) …, group of bits (Y)2A-1) May not be divided and all bits may be written to a second column, …, and a group of bits (Y)CA-A) Group of bits (Y)CA-A+1) …, group of bits (Y)CA-1) The bits included in each bit group in (a) may not be separated and all bits may be written in column C. Thus, all the groups of bits interleaved using the first part are written in the same column of the first part.
Thereafter, the
In the above example, since a × C +1 ═ NgroupTherefore, when the bit groups constituting the LDPC codeword are successively written into the first part, the last bit group Y of the LDPC codewordNgroup-1Not written to the first portion and remains. Thus, the
The bits separated based on the number of columns may be referred to as a sub-bit group. In this case, each of the sub-bit groups may be written to each column of the second portion. That is, bits included in the bit group may be separated and may form a sub-bit group.
That is, the
That is, in the second part, the bits constituting the bit group may not be written in the same column, but may be written in a plurality of columns. In other words, in the above example, the last bit group (Y)Ngroup-1) Formed of M bits, and thus, the last bit group (Y)Ngroup-1) The included bits may be divided by M/C and written to each column. I.e. the last bit group (Y)Ngroup-1) The included bits are divided by M/C to form M/C sub-bit groups, and each of the sub-bit groups may be written in each column of the second part.
Therefore, in the at least one bit group interleaved by the second part, bits included in the at least one bit group are separated and written in at least two columns constituting the second part.
In the above example, the
Specifically, referring to fig. 29, the
On the other hand, the
Accordingly, the
As described above, the
Specifically, in the case of fig. 28, the bits included in the group of bits that do not belong to the first part are written in the second part in the column direction and the bits are read in the row direction. In view of this, the order of the bits included in the group of bits not belonging to the first part is rearranged. Since the bits included in the group of bits not belonging to the first part are interleaved as described above, Bit Error Rate (BER)/Frame Error Rate (FER) performance can be improved compared to the case where such bits are not interleaved.
However, the bit groups not belonging to the first part may not be interleaved, as shown in fig. 29. That is, since the
In fig. 28 and 29, the last single bit group of the plurality of bit groups is written in the second part. However, this is merely an example. The number of bit groups written in the second part may vary according to the total number of bit groups of the LDPC codeword, the number of columns and rows, the number of transmission antennas, and the like.
The
watch 28
Watch 29
Here, C (or N)C) Is the number of columns of the
Referring to table 28 and table 29, according to the modulation method, the number of columns has the same value as the modulation order, and each of the plurality of columns is formed of a number of rows corresponding to the number of bits constituting the LDPC codeword divided by the number of the plurality of columns.
For example, when the length N of an LDPC codewordldpcIs 16200 and the modulation method is 16-QAM, the
In addition, referring to table 28 and table 29, when the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns, the
When the number of columns of the
For example, when N isldpcWhen 16200 and the modulation method is 16-QAM, the
Referring to tables 28 and 29, the total number of rows (i.e., R) of the
In addition, the number of rows R of the first part1Is an integer multiple M (e.g., M-360) of the number of bits included in each group, and may be represented as
And the number of rows R of the second part2May be Nldpc/C-R1. In this context, it is intended that,is not more than NgroupThe largest integer of/C. Due to R1Is an integer multiple M of the number of bits included in each group, and thus, bits can be written into R by groups of bits1Next, the process is carried out.Further, table 28 and table 29 indicate that when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, the
Specifically, the length of the LDPC codeword divided by the number of columns is the total number of rows included in each column. In this case, when the number of bit groups of the LDPC codeword is a multiple of the number of columns, each column is not divided into two parts. However, when the number of bit groups of the LDPC codeword is not a multiple of the number of columns, each column is divided into two parts.
For example, it is assumed that the number of columns of the
When the modulation method is 16-QAM, the
In this case, since the number of bit groups divided by the number of columns of the LDPC codeword is 180/4(═ 45), bits can be written in each column in bit groups without dividing each column into two parts. That is, bits (i.e., 45 × 360(═ 16200) bits) included in 45 bit groups (i.e., the number of bit groups constituting the LDPC codeword divided by the number of columns) may be written in each column.
However, when the modulation method is 256-QAM, the
In this case, since the number of bit groups of the LDPC codeword divided by the number of columns is 22.5, 180/8, the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns. Thus, the
In this case, since bits should be written in the first part of each column by bit group, the number of bit groups that can be written in the first part of each column by bit group is 22, i.e., a quotient obtained when the number of bit groups constituting the LDPC codeword is divided by the number of columns, and thus, the first part of each column has 22 × 360(═ 7920) rows. Thus, 7920 bits included in the 22 bit groups may be written in the first portion of each column.
The second portion of each column has as many rows as a value obtained by subtracting the number of rows of the first portion from the total number of rows of each column. Thus, the second portion of each column includes 8100-7920 (180) rows.
In this case, the bits included in the other bit groups that are not written in the first part are separated and written in the second part of each column.
Specifically, since 22 × 8(═ 176) bit groups are written in the first part, the number of bit groups to be written in the second part is 180-0Group of bits Y1Group of bits Y2… bit group Y176Group of bits Y177And bit group Y179)。
Accordingly, the
That is, the
Thus, the bits included in the remaining bit groups are not written in the same column of the second portion but may be divided and written in a plurality of columns.
Hereinafter, the
LDPC codewords interleaved in groups
In, YjArranged consecutively likeThe LDPC codeword after the group interleaving may be interleaved by the
In particular, the input bit viWriting from the first portion to the second portion in succession in the column direction and subsequently reading from the first portion into the second portion in succession in the row direction. I.e. a data bit viThe data is written into the block interleaver successively in the column direction starting from the first section to the second section, and then read out successively in the row direction from the first section to the second section. Thus, bits included in the same group of bits of the first part may be mapped to a single bit of each modulation symbol. In other words, bits included in the same bit group of the first part may be mapped into a plurality of bits included in a plurality of modulation symbols, respectively.
In this case, the number of columns and the number of rows of the first and second parts of the
Watch 30
The operation of the
Specifically, as shown in fig. 30, the input bit vi(0≤i<NC×Nr1) C written to the first part of the block interleaver 124iR of columniIn the row. In this context, ciAnd riAre respectivelyAnd ri=(i mod Nr1)。
Furthermore, the input bit vi(NC×Nr1≤i<Nldpc) C written to the second part of the block interleaver 124iR of columniIn the row. In this context, ciAnd riRespectively satisfy
And ri=Nr1+{(i-NC×Nr1)modNr2}。Output bit qj(0≤j<Nldpc) From rjC of a linejRead out in columns. In this context, rjAnd cjRespectively satisfy
And cj=(j mod NC)。For example, when the length N of an LDPC codewordldpcIs 64800 and the modulation method is 256-QAM, the order of the bits output from the
The interleaving operation of the
The
In this case, the number of columns constituting the
For example, when the modulation method is 16-QAM, the
A method for interleaving a plurality of bit groups by bit group by the
When the number of bit groups constituting the LDPC codeword is an integer multiple of the number of columns, the
For example, when the modulation method is 16-QAM and the length N of the LDPC codewordldpcAt 16200, the
As described above, when the number of bit groups constituting the LDPC codeword is not an integer multiple of the number of columns constituting the
Specifically, the
Here, a section (i.e., a first section) including as many rows as the number of bits included in the bit group that can be written in bit groups may be composed of as many rows as an integer multiple of M. That is, when the modulation method is 256-QAM, each column of the
In this case, after writing at least a part of the bit groups that can be written in bit groups among the plurality of bit groups in each of the plurality of columns in order, the
For example, when the modulation method is 16-QAM, as shown in fig. 31 and 32, the
In this case, the
That is, as shown in fig. 31 and 32, the
As described above, the
Thereafter, the
For example, as shown in FIG. 31, when the last group (i.e., bit group (Y)) of the LDPC codeword44) The
That is, the
In addition, it is described in the above example that the
Specifically, referring to fig. 32, the
In addition, the
As described above, the
First, the
A demultiplexer (not shown) demultiplexes the interleaved LDPC codeword. Specifically, a demultiplexer (not shown) performs serial-to-parallel conversion on the interleaved LDPC codeword, and demultiplexes the interleaved LDPC codeword into units (or data units) having predetermined bits.
For example, as shown in fig. 33, a demultiplexer (not shown) receives the LDPC codeword Q ═ (Q) output from the
In this case, it is preferable that the air conditioner,bits having the same index in each of the plurality of sub-streams may constitute the same unit. Thus, the cell can be configured to be similar to (y)0,0,y1,0,…,yηMOD-1,0)=(q0,q1,qηMOD-1)、(y0,1,y1,1,…,yηMOD-1,1)=(qηMOD,qηMOD+1,…,q2xηMOD-1)、…。
Here, the number N of substreamssubstreamsCan be equal to the number of bits η constituting a modulation symbolMOD. Therefore, the number of bits constituting each cell may be equal to the number of bits constituting a modulation symbol (i.e., modulation order).
For example, when the modulation method is 16-QAM, the number η of bits constituting a modulation symbolMODIs 8, and thus, the number of substreams NsubstreamsIs 4 and the cell can be configured similarly to (y)0,0,y1,0,y2,0,y3,0)=(q0,q1,q2,q3,q4),(y0,1,y1,1,y2,1,y3,1,1)=(q4,q5,q6,q7),(y0,2,y1,2,y2,2,y3,2)=(q8,q9,q10,q11),...….
Specifically, the
In this case, since each cell output from the demultiplexer (not shown) is formed of as many bits as the number of bits constituting a modulation symbol, the
However, the above-described demultiplexer (not shown) may be omitted according to circumstances. In this case, the
The
In the non-uniform constellation method, once the constellation point in the first quadrant is defined, the constellation points in the other three quadrants may be determined as follows. For example, when the set of constellation points defined for the first quadrant is X, the set becomes-conj (X) in the case of the second quadrant, conj (X) in the case of the third quadrant, and- (X) in the case of the fourth quadrant.
That is, once the first quadrant is defined, the other quadrants may be represented as follows:
1 st quarter (first quadrant) ═ X
Second quadrant-conj (x)
3 rd quarter (third quadrant) ═ conj (x)
Fourth quadrant (4 th) ═ X
In particular, when using non-uniform M-QAM, the M constellation points may be defined as z ═ z { (z)0,z1,…,zM-1}. In this case, the constellation point when present in the first quadrant is defined as { x }0,x1,x2,…,xM/4-1Z may be defined as follows:
from z0To zM/4-1From x0To xM/4
From zM/4To z2xM/4-1Is ═ conj (from x)0To xM/4)
From z2xM/4To z3xM/4-1Conj (from x)0To xM/4)
From z3xM/4To z4xM/4-1Is ═ from x0To xM/4)
Thus, by mapping the output bits to have indices in the non-uniform constellation method
Z of (a)LIn addition, the
x/shape
5/15
7/15
9/15
11/15
13/15
x0
0.3192+0.5011i
0.2592+0.4888i
0.2386+0.5296i
0.9342+0.9847i
0.9517+0.9511i
x1
0.5011+0.3192i
0.4888+0.2592i
0.5296+0.2386i
0.9866+0.2903i
0.9524+0.3061i
x2
0.5575+1.1559i
0.5072+1.1980i
0.4882+1.1934i
0.2716+0.9325i
0.3067+0.9524i
x3
1.1559+0.5575i
1.1980+0.5072i
1.1934+0.4882i
0.2901+0.2695i
0.3061+0.3067i
x4
-0.3192+0.5011i
-0.2592+0.4888i
-0.2386+0.5296i
-0.9342+0.9847i
-0.9517+0.9511i
x5
-0.5011+0.3192i
-0.4888+0.2592i
-0.5296+0.2386i
-0.9866+0.2903i
-0.9524+0.3061i
x6
-0.5575+1.1559i
-0.5072+1.1980i
-0.4882+1.1934i
-0.2716+0.9325i
-0.3067+0.9524i
x7
-1.1559+0.5575i
-1.1980+0.5072i
-1.1934+0.4882i
-0.2901+0.2695i
-0.3061+0.3067i
x8
0.3192-0.5011i
0.2592-0.4888i
0.2386-0.5296i
0.9342-0.9847i
0.9517-0.9511i
x9
0.5011-0.3192i
0.4888-0.2592i
0.5296-0.2386i
0.9866-0.2903i
0.9524-0.3061i
x10
0.5575-1.1559i
0.5072-1.1980i
0.4882-1.1934i
0.2716-0.9325i
0.3067-0.9524i
x11
1.1559-0.5575i
1.1980-0.5072i
1.1934-0.4882i
0.2901-0.2695i
0.3061-0.3067i
x12
-0.3192-0.5011i
-0.2592-0.4888i
-0.2386-0.5296i
-0.9342-0.9847i
-0.9517-0.9511i
x13
-0.5011-0.3192i
-0.4888-0.2592i
-0.5296-0.2386i
-0.9866-0.2903i
-0.9524-0.3061i
x14
-0.5575-1.1559i
-0.5072-1.1980i
-0.4882-1.1934i
-0.2716-0.9325i
-0.3067-0.9524i
x15
-1.1559-0.5575i
-1.1980-0.5072i
-1.1934-0.4882i
-0.2901-0.2695i
-0.3061-0.3067i
Watch 31
Interleaving is performed in the above method for the following reasons.
In particular, when LDPC codeword bits are mapped onto modulation symbols, the bits may have different reliabilities (i.e., reception performance or reception probability) according to positions where the bits are mapped in the modulation symbols. LDPC codeword bits may have different codeword characteristics according to the configuration of the parity check matrix. That is, the LDPC codeword bits may have different codeword characteristics according to the number of 1's (i.e., column order) existing in the columns of the parity check matrix.
Thus, by considering codeword characteristics of LDPC codeword bits and reliabilities of bits constituting a modulation symbol, the
E.g. when the group X is composed of bits0To X44When the formed LDPC codeword is group-interleaved based on equation 12 and table 15, the
In this case, the number of columns of the
Therefore, among the 45 groups constituting the LDPC codeword, 11 bit groups (X)3、X33、X39、X2、X38、X29、X0、X10、X25、X17、X7) The first part of the first column, 11 bits, which can be input to the block interleaver 124Group (X)21、X44、X37、X8、X34、X20、X1、X4、X31、X11、X42) The first part of the second column, 11 bit groups (X), which may be input to the block interleaver 12422、X13、X12、X28、X26、X43、X30、X14、X16、X23、X24) The first part of the third column, 11 bit groups (X), which may be input to the block interleaver 12415、X5、X18、X9、X36、X6、X19、X32、X40、X41、X35) May be input to the first portion of the fourth column of the
Bit group X27To the second part of the
Also, the
As described above, since specific bits are mapped to specific bits in modulation symbols through interleaving, a receiver side can achieve high reception performance and high decoding performance.
Hereinafter, a method for determining pi (j), which is a parameter for group interleaving, according to various embodiments will be explained. The criteria to be considered are as follows:
criterion 1) determines different interleaving orders based on the modulation method and the code rate.
Criterion 2) considers both the functional characteristics of each group of bits of the LDPC codeword and the functional characteristics of the bits constituting the modulation symbol.
For example, in the LDPC codeword, the performance characteristics vary from group to group depending on the order of variable nodes corresponding to bits constituting each group (i.e., the number of edges connected to the variable nodes, and the characteristics of the graph connected to the variable nodes). Generally, the larger the order of the variable node, the better the performance.
In addition, the bits making up the modulation symbols may have different performance characteristics. For example, when the non-uniform 16-QAM (hereinafter, referred to as 16-NUQ) constellation shown in Table 31 is used, the signal reception performance of each bit (P (yi)) is represented by P (y0) ≧ P (y1) ≧ P (y2) ≧ P (y3) with respect to four (4) bits y0, y1, y2, y3 constituting a 16-NUQ symbol.
Therefore, when using the LDPC code and 16-NUQ of length 16200, it is necessary to consider the characteristics and modulation method of the LDPC code, and to select which bit among four (4) bits constituting a 16-NUQ symbol each of 45 bit groups is mapped to.
In this case, y having the highest performance among the first column of the
Accordingly, when using LDPC codeword and 16-NUQ of length 16200, eleven (11) bit groups need to be selected to map to y, from among four (4) bits constituting a 16-NUQ symbol0Above, eleven (11) bit groups need to be selected to map to y1Above, eleven (11) bit groups need to be selected to map to y2Above, eleven (11) bit groups need to be selected to map to y3And need to selectOne (1) bit group to map to y0、y1、y2、y3。
In addition, in order to predict decoding performance with respect to the LDPC code and the modulation method, a density evolution method may be used. The density evolution method is performed by receiving a Probability Density Function (PDF) of a log-likelihood ratio (LLR) for each bit group of an LDPC codeword and calculating a minimum signal-to-noise ratio (SNR) that satisfies a quasi-error free code (QEF). Herein, the SNR is referred to as a noise threshold.
The 16-NUQ is formed from four (4) bit levels. Here, the PDF of the LLR value corresponding to each bit level is g0(x)、g1(x)、g2(x)、g3(x) In that respect That is, when i is an integer between 0 and 3, from among four (4) bits constituting a 16-NUQ symbol, and yiThe PDF of LLR values for the corresponding channel output values is gi(x)。
In addition, among 45-bit groups constituting the LDPC codeword having the length of 16200, the PDF of the channel LLR of eleven (11) bit groups corresponding to the first part is f1(x) The PDF of the channel LLR for the eleven (11) bit groups corresponding to the second part is f2(x) The PDF of the channel LLR for the eleven (11) bit groups corresponding to the third part is f3(x) The PDF of the channel LLR of eleven (11) bit groups corresponding to the fourth section is f4(x) In that respect Further, the PDF of the channel LLRs for the one (1) bit groups corresponding to the first, second, third, and 4 th columns of the second portion is f5(x) In that respect In this case, a relational formula shown in the following equation 22 may be considered.
[ equation 22]
f1(x)=g0(x),f2(x)=g1(x),f3(x)=g2(x),f4(x)=g3(x),
f5(x)=(g0(x)+g1(x)+g2(x)+g3(x))/4
In various exemplary embodiments, in designing a group interleaver by determining a parameter π (j) for group interleaving, the first step is from f1(x) To f5(x) One of them is selected as the LDPC having the constituent length of 16200Each of the PDFs of LLR values for 45 bit groups of a codeword.
At step 1-1, which is the first step in the design of the group interleaver, the PDFs of the LLR values for all the bit groups are not selected. Therefore, when using the density evolution method, the PDF on the LLR values of all bit groups uses f according to equation 23remain(x) The value is obtained. This is a weighted average of the PDFs that have not been selected.
[ equation 23]
fremain(x)=(11×f1(x)+11×f2(x)+11×f3(x)+11×f4(x)+f5(x))/45
At step 1-2 of the first step of the group interleaver design, the PDF of the LLR values for each group of bits is from f1(x) To f5(x) Is selected from among. There are a total of 45 bit groups, and a total of five (5) PDFs may be selected for the respective bit groups. For example, it can be assumed that f1(x) The PDF selected as the first bit group, and the PDF of the remaining bit groups are not selected. In this case, the PDF for the remaining bit group, fremain(x) Is used as shown in equation 24 below. This is the weighted average of the PDFs that have not been selected.
[ equation 24]
fremain(x)=(10×f1(x)+11×f2(x)+11×f3(x)+11×f4(x)+f5(x))/44
According to an exemplary embodiment, in the above step, for f1(x) The PDF selected as the first bit group, one of cases where the value at which the noise threshold is obtained by the density evolution method is minimum, may be arbitrarily selected. The noise threshold is different according to the channel, and the channel and noise threshold considered in the present invention will be described in more detail below.
At step 1-3 of the group interleaver design, the next group of bits (for which the PDF is selected) and its PDF are selected based on step 1-2. For example, if it is assumed that in steps 1-2, f1(x) Selected as the PDF of the first group of bits (since the noise threshold average is smallest in this case), f3(x) The PDF selected as the second bit group. In this case, the PDF of the remaining bit group uses f as shown in the following equation 25remain(x) In that respect This is a weighted average of the PDFs that have not been selected.
[ equation 25]
fremain(x)=(10×f1(x)+11×f2(x)+10×f3(x)+11×f4(x)+f5(x))/43
After steps 1-46 of the first step of the group interleaver design are performed in the same manner as described above, f1(x) To f5(x) One PDF of is selected or assigned to each of the 45 bit groups. That is, when the first step of the group interleaver design is completed, the PDF of the LLR values for the respective ones of the 45 bit groups is from f1(x) To f5(x) To select among them.
In the above-described procedure, after calculating the noise threshold by using the density evolution, the position of each bit group corresponding to each column of the first part of the
For example, in general, a good interleaving pattern in AWGN channel is not good in Rayleigh channel in most cases. In this case, if the channel environment using a given system is closer to the Rayleigh channel, it may be better to select a good interleaving pattern in Rayleigh than in AWGN channel.
In summary, in order to determine the interleaving pattern, not only a predetermined channel environment but also various channel environments to be considered in the system should be considered to calculate a good interleaving pattern.
It should be understood that there is a channel C to be considered in the present invention1、C2、...、CkThe noise threshold for the final determination is as follows, after each noise threshold calculated in step 1-i is calculated, and its noise threshold is denoted as TH1[i]、TH2[i]、…、THk[i]。
TH[i]=W1*TH1[i]+W2*TH2[i]+…+Wk*THk[i],
Here, W1+W2+…+Wk=1,W1,W2,…,Wk>0.
W1、W2、…、WkAdjusted according to the degree of importance of the channel, i.e. in the important channel, W1、W2、…、WkIs adjusted to be large, and in less important channels, W1、W2、…、WkIs adjusted to be small (e.g., when considering two different channels such as AWGN and Rayleigh, if the degree of importance of any channel appears to be higher, then the weight value W corresponding to each channel1、W2In other words, a device such as W is provided1=0.25、W2Asymmetric value of 0.75. ).
The second step of the group interleaver design is to generate a plurality of pi (j) satisfying the conditions determined in the first step, observe the actual Bit Error Rate (BER) and Frame Error Rate (FER) performance for a predetermined SNR value, and select pi (j) with the best performance. Thus, the reason why the step of measuring the actual performance is added to the density evolution is: because the density evolution calculates the theoretical noise threshold under the assumption that the length of the LDPC codeword is infinite, the density evolution may not estimate the correct performance of an LDPC code with a finite length.
In general, pi (j) satisfying the condition predetermined in the first step is generated by 50, and then in each channel, at FER 10-3Zone test performance. Based on this, the selective SNR gain is estimated to be at the target FER (e.g., FER 10)-6) The largest 5 interleaver patterns in the set, test the performance of the final target FER, and then finally select the interleaver with the best performance. Here, a method of selecting an interleaver in which SNR gain seems to be the largest is: estimation of FER performance by extrapolation (by FER 10)-3Actual calculation of experimental results for the zone by the FER performance required by the system), and then comparing the estimated performance in the target FER required in the system, and the one that will have better performanceThe interleaver is determined to be a good interleaver. In the present invention, for convenience of explanation, the method of extrapolation is applied based on a linear function, but various extrapolation methods may be applied.
In addition, fig. 34 is a view showing an example of performance extrapolation estimated from calculation experiment results.
However, if the finally selected interleaver shows an error-floor (error-floor) at the target FER, then pi (j) satisfying the predetermined condition in the first step is further generated by 50, and the above process is repeated.
According to the method described above, pi (j) of tables 15-17 for group interleaving can be determined.
In the following, step 2 of the group interleaver design will be described in more detail.
In addition, as described above, since each of the bit groups constituting the LDPC codeword corresponds to each of the column groups of the parity check matrix, the order of each column group has an influence on the decoding performance of the LDPC codeword.
For example, a relatively high order of a column group indicates that the number of parity check equations related to the bit groups corresponding to the column group is relatively large, and a bit group corresponding to a column group having a relatively high order within a parity check matrix formed of a plurality of column groups may have a greater influence on decoding performance of the LDPC codeword than a bit group corresponding to a column group having a relatively low order. In other words, if column groups having a relatively high order are not properly mapped, the performance of the LDPC codeword is greatly reduced.
Accordingly, the group interleaver may be designed such that a bit group having the highest order among bit groups constituting the LDPC codeword is interleaved according to pi (j) and mapped to a specific bit of a modulation symbol (or a transmission symbol), and other bit groups having no highest order are randomly mapped to the modulation symbol. In this case, by observing the actual BER/FER performance, the case where the performance of the LDPC codeword is greatly reduced can be avoided.
Hereinafter, the following will be described in more detail: the
In this case, the
Therefore, the parity check matrix is formed of 45 column groups, and among the 45 column groups, 10 column groups have an order of 10, 7 column groups have an order of 9, and 28 column groups have an order of 1.
Accordingly, for only 10 order 10 column groups among 45 column groups, several π (j) for 10 column groups may be generated to satisfy the predetermined condition in the first step of the group interleaver design, and π (j) for the other column groups may be left blank. The bit groups corresponding to the other column groups may be arranged to be randomly mapped to the bits constituting the modulation symbol. Then, by observing the actual BER/FER performance with respect to a certain SNR value, pi (j) for 10 column groups with the best performance is selected. By fixing a portion of pi (j), i.e., pi (j) for 10 column groups selected as described above, a significant degradation of the performance of the LDPC codeword can be avoided.
Alternatively, table 32 may be represented as the following table 32-1.
TABLE 32-1
In the case of table 32, equation 21 may be expressed as Y7=Xπ(7)=X10、Y10=Xπ(10)=X7、Y14=Xπ(14)=X8、Y20=Xπ(20)=X11、Y23=Xπ(23)=X13、Y24=Xπ(24)=X12、Y29=Xπ(29)=X14、Y34=Xπ(34)=X5、Y36=Xπ(36)=X9、Y38=Xπ(38)=X6.
That is, the
In case some bit groups are already fixed, the above features are applied in the same way. In other words, a bit group corresponding to a column group having a relatively high order among other bit groups that are not fixed may have a greater influence on decoding performance of the LDPC codeword than a bit group corresponding to a column group having a relatively low order. That is, even in the case where the performance of the LDPC codeword is prevented from being degraded by fixing the bit group having the highest order, the performance of the LDPC codeword may be changed according to a method of mapping other bit groups. Therefore, a method of mapping the bit groups having the second highest order needs to be properly selected to avoid a case where the performance is relatively poor.
Accordingly, in the case where the bit group having the highest order has been fixed, the bit group having the second highest order among the bit groups constituting the LDPC codeword may be interleaved according to pi (j) and mapped to a specific bit of the modulation symbol, and the other bit groups may be randomly mapped. In this case, by observing the actual BER/FER performance, the case where the performance of the LDPC codeword is greatly reduced can be avoided.
Hereinafter, the following will be described in more detail: the
In this case, the
Therefore, the parity check matrix is formed of 45 column groups, and among the 45 column groups, 10 column groups have an order of 10, 7 column groups have an order of 9, and 28 column groups have an order of 1.
Accordingly, in the case where 10 column groups of order 10 have been fixed as in table 32, therefore, for only 7 column groups of order 9 among the other 35 column groups, several π (j) for the 7 column groups may be generated to satisfy the predetermined condition in the first step of the group interleaver design, and π (j) for the other column groups may be left blank. The bit groups corresponding to the other column groups may be arranged to be randomly mapped to the bits constituting the modulation symbol. Then, by observing the actual BER/FER performance with respect to a certain SNR value, pi (j) for the 7 column groups with the best performance is selected. By fixing a portion of pi (j), i.e., pi (j) for 7 column groups selected as described above, a significant degradation of the performance of the LDPC codeword can be avoided.
Watch 33
Watch 34
Alternatively, table 34 may be represented as the following table 34-1.
TABLE 34-1
In the case of table 34, equation 21 may be expressed as Y0=Xπ(0)=X3、Y3=Xπ(3)=X2、Y6=Xπ(6)=X0,…、Y34=Xπ(34)=X5、Y36=Xπ(36)=X9、Y38=Xπ(38)=X6。
That is, the
In the above exemplary embodiment, the following case is described: LDPC encoding is performed based on a code rate of 5/15 and a parity check matrix formed of an information word sub-matrix and a parity check sub-matrix having a diagonal configuration as defined in table 14, but this is merely exemplary, and pi (j) may be determined based on the above-described method even in the case where an LDPC codeword is performed based on a different code rate and a different parity check matrix.
The transmitting
Fig. 35 is a block diagram showing a configuration of a reception apparatus according to an exemplary embodiment. Referring to fig. 35, the receiving
The
The value corresponding to the LDPC codeword may be represented as a channel value for the received signal. There are various methods for determining the channel value, for example, a method for determining a Log Likelihood Ratio (LLR) value may be a method for determining the channel value.
The LLR value is a logarithmic value of a ratio of a probability that a bit transmitted from the
The
Specifically, the
The information on whether to perform the demultiplexing operation may be provided by the
The
Specifically, the
To this end, the
The
Specifically, the
That is, the
In this case, when the
Further, when the
Hereinafter, the
Input LLR vi (0 ≦ i)<Nldpc) is written into ri rows and ci columns of the
on the other hand, the output LLRs qi (0 ≦ i) are read from the ci columns and ri rows of the first portion of the
furthermore, the output LLRqi is read from ci columns and ri rows of the second part (Nc × Nr1 ≦ i<Nldpc). In this context, it is intended that,
ri=Nr1+{(i-Nc×Nr1)mode Nr2}。the
Specifically, the
That is, the
The group deinterleaver 1233 (or the packet deinterleaver) deinterleaves the output values of the
Specifically, the
That is, the
The parity deinterleaver 1234 performs parity deinterleaving on the output value of the
Specifically, the
However, the
Although the
For example, when the code rate is 5/15 and the modulation method is 16-QAM, the
In this case, each belongs to a group of bits X3、X21、X22、X15The bits of each bit group in (a) may constitute a single modulation symbol. Due to bit group X3、X21、X22、X15One bit of each bit group in (b) constitutes a single modulation symbol, and thus,
The
Specifically, the
For example, the
When performing LDPC decoding, the
Further, information on the parity check matrix and information on the code rate, etc. for LDPC decoding may be stored in the
Fig. 38 is a flowchart illustrating an interleaving method of a transmission apparatus according to an exemplary embodiment.
First, an LDPC codeword is generated by LDPC encoding based on a parity check matrix (S1410), and the LDPC codeword is interleaved (S1420).
Subsequently, the interleaved LDPC codeword is mapped onto a modulation symbol (S1430). In this case, bits included in a predetermined bit group among a plurality of bit groups constituting the LDPC codeword may be mapped onto predetermined bits in the modulation symbol.
In this case, each bit group of the plurality of bit groups may be formed of M number of bits, and M may be NldpcAnd KldpcAnd may be determined to satisfy Qldpc=(Nldpc-Kldpc) and/M. Here, QldpcIs a value of a cyclic shift parameter for a column of a column group of an information word sub-matrix of the parity check matrix, NldpcIs the length of the LDPC codeword, and KldpcIs the length of the information word bits of the LDPC codeword.
In addition, operation S1420 may include interleaving parity bits of the LDPC codeword; dividing the parity-check-bit-interleaved LDPC codeword into a plurality of bit groups and rearranging an order of the plurality of bit groups by bit group; and interleaving the plurality of bit groups, the order of which is rearranged.
Based on equation 21 above, the order of the plurality of bit groups may be rearranged by bit group.
In addition, pi (j) in equation 21 may be determined based on at least one of the length of the LDPC codeword, the modulation method, and the code rate.
For example, when the LDPC codeword has a length of 16200, the modulation method is 16-QAM, and the code rate is 5/15, pi (j) may be defined as in table 15.
In addition, at S1420, dividing the LDPC codeword into a plurality of bit groups, rearranging an order of the plurality of bit groups by bit group, and interleaving the rearranged plurality of bit groups is included.
However, this is merely exemplary, and pi (j) may be defined as the above tables 15 to 27.
Interleaving the plurality of bit groups may include: the method includes writing a plurality of bit groups in each of a plurality of columns in a column direction in terms of bit groups, and reading each row of the plurality of columns in a row direction in which the plurality of bit groups are written in terms of bit groups.
Further, interleaving the plurality of bit groups may include: at least some of the plurality of bit groups, which can be written in the plurality of columns by bit group, are successively written in the plurality of columns, and then the other bit groups are divided and written in an area remaining after the at least some of the bit groups are written in the plurality of columns by bit group.
Fig. 39 is a block diagram showing a configuration of a receiving apparatus according to an exemplary embodiment.
Referring to fig. 39, the receiving
The
The
The
Fig. 40 is a block diagram illustrating a demodulator according to an exemplary embodiment.
Referring to fig. 40, the
The
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The controller 3833 extracts an L1 signaling table from the L1 signaling bits, and controls the operations of the
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According to an exemplary embodiment, the
Fig. 41 is a flowchart for illustrating an operation of a reception apparatus from the time when a user selects a service until the selected service is reproduced according to an exemplary embodiment.
It is assumed that service information on all services available for user selection is acquired at initial scanning (S4010) before user' S service selection (S4020). The service information may include information on an RF channel and a PLP transmitting data required for reproducing a specific service in the current receiving apparatus. As an example of the service information, program specific information/service information (PSI/SI) in MPEG2-TS is available and can be generally implemented through L2 signaling and upper layer signaling.
In the initial scan (S4010), there is comprehensive information on the payload type of the PLP transmitted to the specific frequency band. As an example, there may be information on whether each PLP transmitted to the band includes a specific type of data.
When the user selects a service (S4020), the receiving apparatus converts the selected service to a transmission frequency (S4030) and performs RF signal detection (S4040). In the frequency transform operation (S4030), service information may be used.
When the RF signal is detected, the receiving apparatus performs an L1 signaling extraction operation from the detected RF signal (S4050). Subsequently, the receiving apparatus selects a PLP to transmit the selected service based on the extracted L1 signaling (S4060), and extracts a BBF from the selected PLP (S4070). In S4060, the service information may be used.
The operation of extracting the BBF (S4070) may include an operation of demapping the transmitted frame and selecting an OFDM unit included in the PLP, an operation of extracting LLR values for LDPC encoding/decoding from the OFDM unit, and an operation of decoding the LDPC codeword using the extracted LLR values.
The receiving apparatus extracts a BBP from the BBF using the extracted header information of the BBF (S4080). The receiving apparatus also extracts a user pack from the extracted BBP using the header information of the extracted BBP (S4090). The extracted user pack is used to reproduce the selected service (S4100). In the BBP extraction operation (S4080) and the user pack extraction operation (S4090), L1 signaling information extracted in the L1 signaling extraction operation may be used.
According to an exemplary embodiment, the L1 signaling information includes information about the type of user packets transmitted through the corresponding PLP, and information about the operation used to encapsulate the user packets in the BBF. The above information may be used in the user packet extraction operation (S4090). In particular, this information can be used in the operation of extracting the user package, which is the reverse operation of wrapping the user package in the BBF. In this case, the procedure for extracting the user packets (recovering null TS packets and inserting TS sync bytes) from the BBP is the same as described above.
A non-transitory computer readable medium may be provided which stores a program for sequentially performing the above-described encoding and/or interleaving methods according to various exemplary embodiments.
A non-transitory computer readable medium refers to a medium (such as registers, buffers, and memories) that stores data semi-permanently, rather than storing data for a short time, and is readable by a device. The various applications or programs described above may be stored in a non-transitory computer readable medium, such as a Compact Disc (CD), a Digital Versatile Disc (DVD), a hard disk, a blu-ray disc, a Universal Serial Bus (USB) flash memory, a memory card, and a Read Only Memory (ROM), and may be provided. Although a bus is not shown in the block diagrams of the transmitter device and the receiver device, communication may be performed between each element of each device via the bus. In addition, each device may also include a processor, such as a Central Processing Unit (CPU) or microprocessor, to perform the various operations described above.
According to exemplary embodiments, at least one of the components, elements or units represented by the blocks when the transmitting device and the receiving device are shown above may be embodied as various numbers of hardware, software and/or firmware structures performing the respective functions described above. For example, at least one of these components, elements or units may use a pass-through circuit structure, such as a memory, processing, logic, look-up table, or the like, that may perform a corresponding function under the control of one or more microprocessors or other control devices. Furthermore, at least one of these components, elements or units may be embodied by a module, program, or portion of code that contains one or more executable instructions for performing specific logical functions, and may be executed by one or more microprocessors or other control devices. Furthermore, at least one of these components, elements or units may further include a processor, such as a CPU, microprocessor, or the like, which performs the corresponding function. Two or more of these components, elements or units may be combined into a single component, element or unit that performs all the operations or functions of the two or more components, elements or units combined. Furthermore, at least part of the function of at least one of these components, elements or units may be performed by another one of these components, elements or units. In addition, although a bus is not shown in the above block diagrams, communication between the components, elements, or units may be performed through the bus. The functional aspects of the exemplary embodiments described above may be implemented in algorithms running on one or more processors. Further, the components, elements or units represented by the blocks or process steps may use any number of the related art techniques for electronic device configuration, signal processing and/or control, data processing, and so forth.
The foregoing exemplary embodiments and advantages are merely exemplary and are not to be construed as limiting the present inventive concept. The exemplary embodiments can be readily applied to other types of apparatuses. Furthermore, the description of the exemplary embodiments is intended to be illustrative, but not limiting, of the scope of the inventive concept, and many alternatives, modifications, and variations will be apparent to those skilled in the art.
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