阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 林相吾 于 2018-12-29 设计创作，主要内容包括：一种半导体装置包括：时钟控制电路,其响应于省电模式信号和时钟而产生周期性地转变的多个锁存控制时钟,并且将多个锁存控制时钟中的每个锁存控制时钟分别锁定到多个电平中的一个,而与时钟无关。所述半导体装置还包括锁存电路,其响应于多个锁存控制时钟而储存输入信号,并将所储存的信号作为输出信号输出。(A semiconductor device includes: a clock control circuit that generates a plurality of latch control clocks that periodically transition in response to the power saving mode signal and the clock, and locks each of the plurality of latch control clocks to one of a plurality of levels, respectively, regardless of the clock. The semiconductor device further includes a latch circuit that stores an input signal in response to a plurality of latch control clocks and outputs the stored signal as an output signal.)

1. A semiconductor device, comprising:

A clock control circuit configured to generate a plurality of latch control clocks that periodically transition in response to a power saving mode signal and a clock, and to lock each of the plurality of latch control clocks to one of a plurality of levels, respectively, regardless of the clock; and

A latch circuit configured to store an input signal in response to the plurality of latch control clocks and output the stored signal as an output signal.

2. The semiconductor device according to claim 1, wherein the clock control circuit comprises:

A plurality of control inverter circuits configured to generate the plurality of latch control clocks in response to the power saving mode signal and the clock; and

A plurality of level locking circuits configured to lock the plurality of latch control clocks in response to the power saving mode signal, wherein each of the plurality of latch control clocks is respectively locked to a low level or a high level of the plurality of levels.

3. The semiconductor device of claim 2, wherein each of the plurality of controlling inverter circuits is activated when the power saving mode signal is disabled and generates an associated one of the plurality of latch control clocks in response to the clock, and each of the plurality of controlling inverter circuits is deactivated when the power saving mode signal is enabled.

4. The semiconductor device according to claim 2, wherein the plurality of control inverter circuits are connected in series, and

Wherein at least one of the plurality of level-locking circuits is electrically connected to a node via which the plurality of control inverter circuits are connected in series.

5. The semiconductor device according to claim 4, wherein when the power saving mode signal is enabled, at least one of the plurality of control inverter circuits pulls up an output node in response to one of the plurality of level-lock circuits and locks one of the plurality of latch control clocks to the low level or the high level.

6. The semiconductor device according to claim 4, wherein at least one of the plurality of control inverter circuits allows an output node to float in response to one of the plurality of level-locking circuits when the power saving mode signal is enabled.

7. The semiconductor device according to claim 1, wherein the latch circuit stores the input signal and outputs the stored signal as the output signal when the plurality of latch control clocks are periodically transitioned, and

Wherein the latch circuit outputs only the stored signal as an output signal regardless of the input signal when each of the plurality of latch control clocks is locked to a specific level.

Technical Field

various embodiments relate generally to a semiconductor integrated circuit, and more particularly, to a semiconductor device.

Background

The semiconductor device is configured to operate in synchronization with a clock when it operates at high speed. Further, in order to achieve low power consumption, the semiconductor apparatus is configured to enter a power saving mode, for example, a power-off mode, a self-refresh mode, or a power gating mode.

When the semiconductor apparatus enters the power saving mode, only some of many internal circuits included in the semiconductor apparatus are activated, and the other circuits are deactivated.

Among internal circuits that operate in synchronization with a clock, particularly in a latch circuit that stores an input signal in response to a clock (e.g., in a flip-flop), the level of the stored signal may be changed when a floating input signal or clock is input in a power saving mode.

Disclosure of Invention

In one embodiment, a semiconductor apparatus includes a clock control circuit that generates a plurality of latch control clocks that periodically transition in response to a power saving mode signal and a clock, and locks each of the plurality of latch control clocks to one of a plurality of levels, respectively, regardless of the clock. The semiconductor device further includes a latch circuit that stores an input signal in response to the plurality of latch control clocks and outputs the stored signal as an output signal.

Drawings

Fig. 1 shows a configuration diagram of a semiconductor device according to an embodiment.

Fig. 2 shows a configuration diagram of the clock control circuit in fig. 1.

Fig. 3 shows a configuration diagram of the latch circuit of fig. 1.

Detailed Description

Hereinafter, a semiconductor device is described below by various example embodiments with reference to the drawings.

A semiconductor device is described herein in which a level of a previously stored signal does not change even if a clock or an input signal is input in a power saving mode.

According to the semiconductor device of one embodiment, in the power saving mode, since the level of the previously stored signal is not changed, when the power saving mode is switched to the normal mode, the abnormal operation of the semiconductor device can be removed.

A semiconductor apparatus according to one embodiment may substantially maintain a previously stored signal in a power saving mode, store an input signal in response to a clock when the power saving mode is switched to a normal mode, and output the stored signal as an output signal.

Fig. 1 shows a configuration diagram of a semiconductor device 300 according to an embodiment, wherein the semiconductor device 300 may include: a power transistor TR, a clock driver 50, a clock control circuit 100, and a latch circuit 200.

The power transistor TR may transmit a voltage (e.g., a low voltage: V _ L) to the clock driver 50 in response to the power saving mode signal PG _ EN. For example, when the power saving mode signal PG _ EN is disabled, the power transistor TR may transmit the low voltage V _ L to the clock driver 50. When the power saving mode signal PG _ EN is enabled, the power transistor TR may block the low voltage V _ L from being transferred to the clock driver 50.

When receiving the low voltage V _ L from the power transistor TR, the clock driver 50 may drive the driving clock CLK _ dr (also simply referred to as a clock) and transfer the driving clock CLK _ dr to the clock control circuit 100. When the low voltage V _ L is not received from the power transistor TR, the power transistor TR may form a node in a floating state from which the driving clock CLK _ dr is output, i.e., through which the clock driver 50 and the clock control circuit 100 are electrically connected to each other. As shown, the clock driver receives an input clock CLK from an external component or another component inside the semiconductor device.

The clock control circuit 100 may generate the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb in response to the power saving mode signal PG _ EN and the driving clock CLK _ dr, respectively. For example, when the power saving mode signal PG _ EN is disabled, the clock control circuit 100 may generate the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb in response to the driving clock CLK _ dr. When the power saving mode signal PG _ EN is enabled, the clock control circuit 100 may lock each of the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb to a specific level regardless of the driving clock CLK _ dr. For the various embodiments, the clock CLK, the driving clock CLK _ dr, and the latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb represent signals sent or received by the clock driver 50, the clock control circuitry, and/or the latch circuitry.

the latch circuit 200 may store the input signal IN _ s IN response to the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb and output the stored signal as the output signal OUT _ s. Further, the latch circuit 200 may output the stored signal as the output signal OUT _ s regardless of the input signal IN _ s IN response to the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb. For example, when the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb (which change voltage levels IN response to the driving clock CLK _ dr) are received from the clock control circuit 100, the latch circuit 200 may store the input signal IN _ s IN response to the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb and output the stored signal as the output signal OUT _ s. When the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb, which have been locked to a certain level regardless of the driving clock CLK _ dr, are received from the clock control circuit 100, the latch circuit 200 may output only the stored signal (regardless of the input signal IN _ s) as the output signal OUT _ s.

Fig. 2 shows a diagram illustrating the configuration of the clock control circuit 100 shown in fig. 1.

The clock control circuit 100 may include: a first controlled inverter circuit 111, a second controlled inverter circuit 112, a third controlled inverter circuit 113, and a fourth controlled inverter circuit 114, and a first level-locking circuit 121, a second level-locking circuit 122, a third level-locking circuit 123, and a fourth level-locking circuit 124.

When the power saving mode signal PG _ EN is disabled to the high level, the first control inverter circuit 111 may be activated and may invert the driving clock CLK _ dr to output the second latch control clock CLK _ Ab. When the power saving mode signal PG _ EN is enabled to a low level, the first control inverter circuit 111 may be deactivated.

The first control inverter circuit 111 may include a first transistor P1, a second transistor N1, and a third transistor N2. For the first transistor P1, the driving clock CLK _ dr is input to its gate, and the high voltage V _ H is applied to its source. For the second transistor N1, the driving clock CLK _ dr is input to its gate, and the drain of the first transistor P1 is electrically connected to the drain of the second transistor N1. For the third transistor N2, the power saving mode signal PG _ EN is input to its gate, the source of the second transistor N1 is electrically connected to the drain of the third transistor N2, and the low voltage V _ L is applied to the source of the third transistor N2. The voltage level of the high voltage V _ H may be higher than that of the low voltage V _ L. The second latch control clock CLK _ Ab is output from a node via which the first transistor P1 and the second transistor N1 are electrically connected to each other.

When the power saving mode signal PG _ EN is disabled to a high level, the second control inverter circuit 112 may be activated and invert the second latch control clock CLK _ Ab to output the first latch control clock CLK _ a. When the power saving mode signal PG _ EN is enabled to a low level, the second control inverter circuit 112 may be deactivated.

The second control inverter circuit 112 may include a fourth transistor P2, a fifth transistor N3, and a sixth transistor N4. For the fourth transistor P2, the second latch control clock CLK _ Ab is input to its gate, and the high voltage V _ H is applied to its source. For the fifth transistor N3, the second latch control clock CLK _ Ab is input to its gate, and the drain of the fourth transistor P2 is electrically connected to the drain of the fifth transistor N3. For the sixth transistor N4, the power saving mode signal PG _ EN is input to the gate thereof, the source of the fifth transistor N3 is electrically connected to the drain of the fifth transistor N3, and the low voltage V _ L is applied to the source of the fifth transistor N3. The first latch control clock CLK _ a is output from a node via which the fourth transistor P2 and the fifth transistor N3 are electrically connected to each other.

When the power saving mode signal PG _ EN is disabled to a high level, the third control inverter circuit 113 may be activated and inverts the driving clock CLK _ dr to output the fourth latch control clock CLK _ Bb. When the power saving mode signal PG _ EN is enabled to a low level, the third control inverter circuit 113 may be deactivated.

The third control inverter circuit 113 may include a seventh transistor P3, an eighth transistor N5, and a ninth transistor N6. For the seventh transistor P3, the driving clock CLK _ dr is input to its gate, and the high voltage V _ H is applied to its source. For the eighth transistor N5, the driving clock CLK _ dr is input to the gate thereof, and the drain of the seventh transistor P3 is electrically connected to the drain of the eighth transistor N5. In the ninth transistor N6, the power saving mode signal PG _ EN is input to a gate thereof, a source of the eighth transistor N5 is electrically connected to a drain of the ninth transistor N6, and the low voltage V _ L is applied to a source of the ninth transistor N6. The fourth latch control clock CLK _ Bb is output from a node through which the seventh transistor P3 and the eighth transistor N5 are electrically connected to each other.

When the power saving mode signal PG _ EN is disabled to a high level, the fourth control inverter circuit 114 may be activated and invert the fourth latch control clock CLK _ Bb to output the third latch control clock CLK _ B. When the power saving mode signal PG _ EN is enabled to a low level, the fourth control inverter circuit 114 may be deactivated.

The fourth control inverter circuit 114 may include a tenth transistor P4, an eleventh transistor N7, and a twelfth transistor N8. For the tenth transistor P4, the fourth latch control clock CLK _ Bb is input to its gate, and the high voltage V _ H is applied to its source. With the eleventh transistor N7, the fourth latch control clock CLK _ Bb is input to its gate, and the drain of the tenth transistor P4 is electrically connected to the drain of the eleventh transistor N7. For the twelfth transistor N8, the power saving mode signal PG _ EN is input to a gate thereof, a source of the eleventh transistor N7 is electrically connected to a drain of the twelfth transistor N8, and the low voltage V _ L is applied to a source of the twelfth transistor N8. The third latch control clock CLK _ B is output from a node through which the tenth transistor P4 and the eleventh transistor N7 are electrically connected to each other.

A node through which the first and third controlling inverter circuits 111 and 113 receive the driving clock CLK _ dr is referred to as a first node N _ a, a node through which the first and second controlling inverter circuits 111 and 112 are electrically connected to each other is referred to as a second node N _ B, and a node through which the second controlling inverter circuit 112 outputs the first latch controlling clock CLK _ a is referred to as a third node N _ C. A node through which the third control inverter circuit 113 and the fourth control inverter circuit 114 are electrically connected to each other is referred to as a fourth node N _ D, and a node through which the fourth control inverter circuit 114 outputs the third latch control clock CLK _ B is referred to as a fifth node N _ E.

The first level-locking circuit 121 may lock the driving clock CLK _ dr to a high level in response to the power saving mode signal PG _ EN. For example, when the power saving mode signal PG _ EN is enabled to a low level, the first level locking circuit 121 may lock the first node N _ a to a high level by applying the high voltage V _ H to the first node N _ a regardless of the driving clock CLK _ dr. In this case, the first control inverter circuit 111 may allow its own output node to float.

The first level-locking circuit 121 may include a thirteenth transistor P5. For the thirteenth transistor P5, the power saving mode signal PG _ EN is input to its gate, the high voltage V _ H is applied to its source, and the first node N _ a is electrically connected to its drain.

The second level locking circuit 122 may lock the second node N _ B to a low level in response to the power saving mode signal PG _ EN. For example, when the power saving mode signal PG _ EN is enabled to a low level, the second level locking circuit 122 may lock the second latch control clock CLK _ Ab to a low level by applying the low voltage V _ L to the second node N _ B. In this case, the second control inverter circuit 112 may receive the second latch control clock CLK _ Ab that transitions to the low level, and the transistor P2 of the second control inverter circuit 112 may pull up its own output node to latch the first latch control clock CLK _ a to the high level.

The second level-locking circuit 122 may include a fourteenth transistor N9. With the fourteenth transistor N9, the inverted signal PG _ ENb of the power saving mode signal PG _ EN is input to the gate thereof, the second node N _ B is electrically connected to the drain thereof, and the low voltage V _ L is applied to the source thereof.

The third level-locking circuit 123 may lock the fourth node N _ D to a high level in response to the power saving mode signal PG _ EN. For example, when the power saving mode signal PG _ EN is enabled to a low level, the third level locking circuit 123 may lock the fourth latch control clock CLK _ Bb to a high level by applying the high voltage V _ H to the fourth node N _ D.

The third level-locking circuit 123 may include a fifteenth transistor P6. For the fifteenth transistor P6, the power saving mode signal PG _ EN is input to its gate, the high voltage V _ H is applied to its source, and the fourth node N _ D is electrically connected to its drain.

The fourth level locking circuit 124 may lock the fifth node N _ E to a low level in response to the power saving mode signal PG _ EN. For example, when the power saving mode signal PG _ EN is enabled to a low level, the fourth level locking circuit 124 may lock the third latch control clock CLK _ B to a low level by applying a low voltage V _ L to the fifth node N _ E.

The fourth level-locking circuit 124 may include a sixteenth transistor N10. With the sixteenth transistor N10, the inverted signal PG _ ENb of the power saving mode signal PG _ EN is input to the gate thereof, the fifth node N _ E is electrically connected to the drain thereof, and the low voltage V _ L is applied to the source thereof.

Fig. 3 shows a diagram illustrating the configuration of the latch circuit 200 shown in fig. 1.

The latch circuit 200 may include first and second transfer gates PG1 and PG2 and first and second latch units 210 and 220.

IN response to the first and second latch control clocks CLK _ a and CLK _ Ab, the first transfer gate PG1 may transfer the input signal IN _ s to the first latch unit 210 or may block the input signal IN _ s from being transferred to the first latch unit 210. For example, when the first latch control clock CLK _ a is at a low level and the second latch control clock CLK _ Ab is at a high level, the first transfer gate PG1 transfers the input signal IN _ s to the first latch unit 210. When the first latch control clock CLK _ a is at a high level and the second latch control clock CLK _ Ab is at a low level, the first transfer gate PG1 blocks the input signal IN _ s from being transferred to the first latch unit 210.

IN the first transmission gate PG1, the second latch control clock CLK _ Ab is input to the first control terminal, the first latch control clock CLK _ a is input to the second control terminal, the input signal IN _ s is input to the input terminal, and the first latch unit 210 is electrically connected to the output terminal.

the first latch unit 210 may store a signal transferred from the first transfer gate PG1 and transfer the stored signal to the second transfer gate PG 2.

The first latch unit 210 may include a first inverter IV1 and a second inverter IV 2. In the first inverter IV1, the first transmission gate PG1 is electrically connected to the input terminal, and the second transmission gate PG2 is electrically connected to the output terminal. In the second inverter IV2, the output terminal of the first inverter IV1 is electrically connected to the input terminal, and the input terminal of the first inverter IV1 is electrically connected to the output terminal.

In response to the third and fourth latch control clocks CLK _ B and CLK _ Bb, the second transfer gate PG2 may transfer an output signal of the first latch unit 210 to the second latch unit 220 or separate the first and second latch units 210 and 220 from each other. For example, when the third latch control clock CLK _ B is at a low level and the fourth latch control clock CLK _ Bb is at a high level, the second transfer gate PG2 separates the first latch unit 210 and the second latch unit 220 from each other. When the third latch control clock CLK _ B is at a high level and the fourth latch control clock CLK _ Bb is at a low level, the second transfer gate PG2 transfers the output signal of the first latch unit 210 to the second latch unit 220.

In the second transmission gate PG2, the third latch control clock CLK _ B is input to the first control terminal, the fourth latch control clock CLK _ Bb is input to the second control terminal, the first latch unit 210 is electrically connected to the input terminal, and the second latch unit 220 is electrically connected to the output terminal.

The second latch unit 220 may store the signal transferred from the second transfer gate PG2 and transfer the stored signal as the output signal OUT _ s.

The second latch unit 220 may include a third inverter IV3 and a fourth inverter IV 4. In the third inverter IV3, the second transmission gate PG2 is electrically connected to the input terminal, and the output signal OUT _ s is output from the output terminal. In the fourth inverter IV4, the output terminal of the third inverter IV3 is electrically connected to the input terminal, and the input terminal of the third inverter IV3 is electrically connected to the output terminal.

Hereinafter, the operation of the semiconductor apparatus 300 configured as described above is described.

The following description provides the operation of the semiconductor apparatus 300 when the current mode is not the power saving mode (i.e., when the current mode is the normal mode). The power saving mode may include a mode (e.g., a power-off mode, a power gating mode, a self-refresh mode, etc.) for reducing power consumed in the semiconductor apparatus 300.

hereinafter, an operation of the clock control circuit 100 in the normal mode is described with reference to fig. 2.

In the normal mode, the power saving mode signal PG _ EN is disabled to a high level.

the first to fourth control inverter circuits 111 to 114 are activated by receiving the power saving mode signal PG _ EN disabled to the high level.

The activated first control inverter circuit 111 inverts the driving clock CLK _ dr to output the second latch control clock CLK _ Ab.

The activated second control inverter circuit 112 inverts the second latch control clock CLK _ Ab to output the first latch control clock CLK _ a.

The activated third control inverter circuit 113 inverts the driving clock CLK _ dr to output the fourth latch control clock CLK _ Bb.

The activated fourth control inverter circuit 114 inverts the fourth latch control clock CLK _ Bb to output the third latch control clock CLK _ B.

In short, in the normal mode, the clock control circuit 100 according to one embodiment generates the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb, which periodically transition, in response to the driving clock CLK _ dr. As used herein, the phrase "periodic transition" means that one or more of the latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb are switched between voltage levels, e.g., between a high voltage level and a low voltage level, also referred to as levels at different times. In some cases, the levels are high and low with respect to each other. That is, the high level is greater than the low level.

Hereinafter, the operation of the latch circuit 200 is described with reference to fig. 3, and the latch circuit 200 receives the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb, which periodically transition.

The first and second transmission gates PG1 and PG2 may receive the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb, which are periodically transited, transfer the input signal IN _ s to the first latch unit 210, and transfer the signal stored IN the first latch unit 210 to the second latch unit 220. In this case, the first latch unit 210 receives and stores the signal transferred from the first transfer gate PG1, and transfers the stored signal to the second transfer gate PG 2. The second latch unit 220 receives and stores the signal transferred from the second transfer gate PG2, and outputs the stored signal as an output signal OUT _ s.

As a result, in the normal mode, the semiconductor apparatus 300 according to one embodiment may perform an operation for storing an input signal and outputting the stored signal as an output signal in response to a clock.

Hereinafter, the operation of the clock control circuit 100 in the power saving mode is described according to one embodiment.

The operation of the clock control circuit 100 in the power saving mode is described with reference to fig. 2.

in the power saving mode, the power saving mode signal PG _ EN is enabled to a low level.

The first to fourth control inverter circuits 111 to 114 are deactivated by receiving the power saving mode signal PG _ EN enabled to a low level.

The first level-locking circuit 121 receives the power saving mode signal PG _ EN enabled to a low level and locks the first node N _ a to a high level.

The second level locking circuit 122 receives the power saving mode signal PG _ EN enabled to a low level and locks the second node N _ B to a low level. That is, the second latch control clock CLK _ Ab is latched to a low level. When the second latch control clock CLK _ Ab is at a low level, the fourth transistor P2 of the second control inverter circuit 112 is turned on and locks the third node N _ C to a high level. Therefore, in the power saving mode, when the third node N _ C is locked to a high level, the first latch control clock CLK _ a is locked to a high level.

The third level locking circuit 123 receives the power saving mode signal PG _ EN enabled to a low level and locks the fourth node N _ D to a high level. When the fourth node N _ D is latched to a high level, the fourth latch control clock CLK _ Bb is latched to a high level.

The fourth level locking circuit 124 receives the power saving mode signal PG _ EN enabled to a low level and locks the fifth node N _ E to a low level. When the fifth node N _ E is latched to a low level, the third latch control clock CLK _ B is latched to a low level.

In brief, in the power saving mode, the clock control circuit 100 according to one embodiment locks the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb to a certain level regardless of the driving clock CLK _ dr.

Hereinafter, the operation of the latch circuit 200 is described with reference to fig. 3, and the latch circuit 200 receives the first to fourth latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb locked to a certain level.

The first transfer gate PG1 receives the first latch control clock CLK _ a latched to a high level and the second latch control clock CLK _ Ab latched to a low level, and blocks the input signal IN _ s from being transferred to the first latch unit 210. IN the case of the power saving mode, since the first latch unit 210 does not receive the input signal IN _ s through the first transfer gate PG1, the first latch unit 210 stores a signal stored before entering the power saving mode.

The second transfer gate PG2 receives the third latch control clock CLK _ B locked to a low level and the fourth latch control clock CLK _ Bb locked to a high level, and separates the first latch unit 210 and the second latch unit 220 from each other. In the case of the power saving mode, since the second latch unit 220 is separated from the first latch unit 210 by the second transfer gate PG2, the second latch unit 220 stores a signal stored before entering the power saving mode and outputs the stored signal as the output signal OUT _ s.

As a result, in the power saving mode, the semiconductor apparatus 300 according to one embodiment can perform an operation for storing a signal stored before entering the power saving mode and outputting the stored signal as an output signal.

The semiconductor apparatus 300 according to one embodiment may lock the first node N _ a to which the driving clock CLK _ dr is input to a high level in the power saving mode, thereby preventing the driving clock CLK _ dr from floating and a glitch component from occurring in the driving clock CLK _ dr. Further, in the power saving mode, the semiconductor apparatus 300 according to one embodiment may lock the plurality of latch control clocks CLK _ A, CLK _ Ab, CLK _ B, and CLK _ Bb input to the latch circuit to a certain level, thereby blocking the respective inputs of the plurality of latch units 210 and 220 and substantially maintaining the signals stored before the power saving mode.

While various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are by way of example only and represent a limited number of possible embodiments. Accordingly, the semiconductor device 300 described herein should not be limited based on the described embodiments.