阅读说明：本技术 半导体装置及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 林文新 曾富群 林鑫成 胡钰豪 吴政璁 于 2018-06-05 设计创作，主要内容包括：本发明提出一种半导体装置及其制造方法,该半导体装置包括一基底、阱、一第一掺杂区、一第二掺杂区、一漏极区、一源极区以及一栅极区。基底具有一第一导电型。阱设置于基底之中,并具有一第二导电型。第一掺杂区设置于阱之中,并具有第一导电型。第二掺杂区设置于阱之中,并具有第一导电型。第一掺杂区与第二掺杂区在空间上彼此分隔。漏极区设置于阱之中,并具有第二导电型。源极区设置于阱之中,并具有第二导电型。栅极区设置于阱之中,并位于源极区与漏极区之间。栅极区具有第一导电型并重叠第一掺杂区。采用本发明方案可以有效提升结型场效应晶体管JFET的空乏能力及驱动电流,并降低JFET的通道截止电压。(The invention provides a semiconductor device and a manufacturing method thereof. The substrate has a first conductivity type. The well is disposed in the substrate and has a second conductive type. The first doped region is disposed in the well and has a first conductivity type. The second doped region is disposed in the well and has the first conductivity type. The first doped region and the second doped region are spatially separated from each other. The drain region is disposed in the well and has a second conductivity type. The source region is disposed in the well and has a second conductivity type. The gate region is arranged in the well and is positioned between the source region and the drain region. The gate region has the first conductivity type and overlaps the first doped region. By adopting the scheme of the invention, the depletion capability and the driving current of the JFET can be effectively improved, and the channel cut-off voltage of the JFET is reduced.)

1. A semiconductor device, comprising:

A substrate having a first conductivity type;

A first well disposed in the substrate and having a second conductivity type;

A first doped region disposed in the first well and having the first conductivity type;

a second doped region disposed in the first well and having the first conductivity type, wherein the first doped region and the second doped region are spatially separated from each other;

a drain region disposed in the first well and having the second conductivity type;

A source region disposed in the first well and having the second conductivity type; and

And a gate region disposed in the first well and between the source region and the drain region, wherein the gate region has the first conductivity type and overlaps the first doped region.

2. the semiconductor device according to claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

3. The semiconductor device according to claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

4. The semiconductor device of claim 1, further comprising:

and a body region of the first conductivity type formed in a second well disposed outside the first well.

5. The semiconductor device of claim 4, wherein the second doped region extends into the second well.

6. The semiconductor device of claim 5, further comprising:

And the interconnection structure is used for electrically connecting the gate region and the substrate region, wherein the first doped region is electrically floated.

7. The semiconductor device of claim 1, wherein said second doped region extends into said substrate.

8. the semiconductor device of claim 7, wherein said first doped region is electrically floating.

9. the semiconductor device of claim 1, wherein said source region overlaps said second doped region.

10. the semiconductor device of claim 1, wherein the first doped region and the second doped region are ring structures.

11. A method for manufacturing a semiconductor device, comprising:

Providing a substrate having a first conductivity type;

Forming a first well in the substrate, the first well having a second conductivity type;

forming a first doped region in the first well, the first doped region having the first conductivity type;

Forming a second doped region in the first well, the second doped region having the first conductivity type, wherein the first doped region and the second doped region are spatially separated from each other;

Forming a drain region in the first well, the drain region having the second conductivity type;

forming a source region in the first well, the source region having the second conductivity type; and

Forming a gate region in the first well, the gate region being located between the source region and the drain region and having the first conductivity type, wherein the gate region overlaps the first doped region.

12. The method of claim 11, wherein the first conductivity type is P-type and the second conductivity type is N-type.

13. the method of claim 11, wherein the first conductivity type is N-type and the second conductivity type is P-type.

14. the method of manufacturing a semiconductor device according to claim 11, further comprising:

Forming a second well in the substrate, the second well having the first conductivity type and located outside the first well; and

And forming a body region in the second well, wherein the body region has the first conductive type.

15. the method of manufacturing a semiconductor device according to claim 14, further comprising:

Extending the second doped region into the second well.

16. The method of manufacturing a semiconductor device according to claim 15, further comprising:

Electrically connecting the gate region and the substrate region; and

Electrically floating the first doped region.

17. the method of manufacturing a semiconductor device according to claim 11, further comprising:

extending the second doped region into the substrate.

18. The method of manufacturing a semiconductor device according to claim 17, further comprising:

electrically floating the first doped region.

19. The method of claim 11, wherein said source region overlaps said second doped region.

20. the method of claim 11, wherein the first doped region and the second doped region are ring structures.

Technical Field

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device of a Junction Field Effect Transistor (JFET) and a method of manufacturing the same.

Background

In order to increase the driving current of the junction field effect transistor, it is known to adjust the depth of the gate. The lower the depth of the gate, the greater the drive current provided by the jfet. However, the conventional method increases the channel off voltage (Pinch off voltage) of the jfet.

disclosure of Invention

The invention provides a semiconductor device, which comprises a substrate, a well, a first doped region, a second doped region, a drain region, a source region and a gate region. The substrate has a first conductivity type. The well is disposed in the substrate and has a second conductive type. The first doped region is disposed in the well and has a first conductivity type. The second doped region is disposed in the well and has the first conductivity type. The first doped region and the second doped region are spatially separated from each other. The drain region is disposed in the well and has a second conductivity type. The source region is disposed in the well and has a second conductivity type. The gate region is arranged in the well and is positioned between the source region and the drain region. The gate region has the first conductivity type and overlaps the first doped region.

The present invention also provides a method for manufacturing a semiconductor device, comprising providing a substrate; forming a well in the substrate; forming a first doped region in the well; forming a second doped region in the well; forming a drain region in the well; forming a source region in the well; a gate region is formed in the well. The substrate, the first doped region, the second doped region and the gate region have a first conductivity type. The first well, the drain region and the source region have a second conductivity type. The first doped region and the second doped region are spatially separated from each other. The gate region is located between the source region and the drain region and overlaps the first doped region.

The drain region, the source region and the gate region form a junction field effect transistor, and the first doped region and the second doped region are separated from each other in space, so that when the first doped region is electrically floated and the second doped region receives a ground voltage, the depletion capability and the driving current of the JFET can be effectively improved, and the channel cut-off voltage of the JFET is reduced.

Drawings

fig. 1 is a schematic cross-sectional view of a semiconductor device according to the present invention.

Fig. 2 is a schematic top view of a doped region according to the present invention.

fig. 3 is a schematic cross-sectional view of another possible semiconductor device of the present invention.

fig. 4 is a schematic cross-sectional view of another possible semiconductor device of the present invention.

Fig. 5 to 7 show a method of manufacturing the semiconductor device shown in fig. 1.

fig. 8 shows a method of manufacturing the semiconductor device shown in fig. 3.

fig. 9A and 9B illustrate another method of fabricating the semiconductor device shown in fig. 3.

Reference numerals

100: a semiconductor device;

102: a substrate;

104. 128: a well;

106. 108: a doped region;

110: a drain region;

112: a gate region;

114: a source region;

116: an inner dielectric layer;

118. 120, 122, 126: an interconnecting structure;

124: a base region;

200: an area;

d1, D2: direction;

DH1, DH 2: depth.

Detailed Description

in order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of the elements in the embodiments is for illustration and not for limitation. In addition, the reference numerals in the embodiments are partially repeated to simplify the description, and do not indicate the relationship between the different embodiments.

fig. 1 is a schematic cross-sectional view of a semiconductor device according to the present invention. As shown, the semiconductor device 100 includes a substrate 102, a well 104, doped regions 106 and 108, a drain region 110, a gate region 112, and a source region 114. The substrate 102 has a first conductivity type. In one embodiment, the substrate 102 is a silicon substrate, a Silicon On Insulator (SOI) substrate, or other suitable semiconductor substrate.

The well 104 is disposed in the substrate 102 and has a second conductive type. In this embodiment, the second conductivity type is opposite to the first conductivity type. In one embodiment, when the first conductivity type is P-type, the second conductivity type is N-type. In another embodiment, when the first conductivity type is N type, the second conductivity type is P type.

The doped region 106 is disposed in the well 104 and has a first conductivity type. The doped region 108 is disposed in the well 104 and has a first conductivity type. Doped regions 106 and 108 are spatially separated from each other (spaced apart). In the present embodiment, the doped region 106 is electrically floating (floating), and the doped region 108 receives a ground voltage (ground). How the doped region 108 receives a ground voltage will be described later.

The doping concentration of the doped regions 106 and 108 is not limited by the present invention. In one possible embodiment, the doping concentration of the doped regions 106 and 108 may also be selectively specifically set to improve the surface field according to a reduced surface field (RESURF) technique. In some embodiments, the doping concentration of the doped regions 106 and 108 is higher than the doping concentration of the substrate 102.

The drain region 110 is disposed in the well 104 and has a second conductivity type. In one possible embodiment, the doping concentration of the drain region 110 is higher than the doping concentration of the well 104. The source region 114 is disposed in the well 104 and has a second conductivity type. In one possible embodiment, the doping concentration of the source region 114 is higher than the doping concentration of the well 104. The gate region 112 is disposed in the well 104 and between the source region 114 and the drain region 110. In the present embodiment, the gate region 112 overlaps the doped region 106 and has the first conductivity type. In one possible embodiment, the gate region 112 has a higher doping concentration than the doped region 106.

In the present embodiment, the drain region 110, the gate region 112 and the source region 114 form a Junction Field Effect Transistor (JFET). Since the doped regions 106 and 108 are spatially separated from each other, when the doped region 106 is electrically floating and the doped region 108 receives a ground voltage, the depletion capability and the driving current of the JFET can be effectively increased, and the channel cut-off voltage of the JFET can be reduced.

in one embodiment, the semiconductor device 100 further includes an interlayer dielectric (ILD)116 and interconnect structures 118, 120, and 122. The interconnect structure 118 is electrically connected to the drain region 110 and serves as a drain electrode. In one embodiment, the drain electrode is configured to receive a drain voltage (not shown). The interconnect structure 120 is electrically connected to the gate region 112 to serve as a gate electrode. The gate electrode is for receiving a gate voltage (not shown). In one embodiment, the gate voltage is a ground voltage. The interconnect structure 122 is electrically connected to the source region 114 and serves as a source electrode. In one embodiment, the source voltage is used to receive a source voltage (not shown).

in some embodiments, the semiconductor device 100 further includes a body region 124. The body region 124 is disposed in the substrate 102 and has a first conductive type. In one possible embodiment, the doping concentration of the body region 124 is higher than the doping concentration of the doped region 106. In other embodiments, the doping concentration of the base region 124 is similar to the doping concentration of the gate region 112.

In the present embodiment, the ild layer 116 further has an interconnect structure 126. Interconnect structure 126 is electrically connected to substrate region 124 for serving as a substrate electrode. The substrate electrode is used for receiving a substrate voltage (not shown). In one embodiment, the bulk voltage is a ground voltage. In other embodiments, the interconnect structure 120 (or gate electrode) also receives a ground voltage. In this example, an interconnect structure (not shown) electrically connects interconnect structure 120 (or gate electrode) and interconnect structure 126 (or base electrode).

in the present embodiment, the doped regions 106 and 108 are ring-shaped structures. Fig. 2 is a possible top view of the doped regions 106 and 108. As shown, doped region 108 surrounds doped region 106. In the region 200, the doped region 108 extends in a direction D1. In the region 202, the doped region 108 extends in a direction D2. The angle between directions D1 and D2 is not limiting to the invention. In fig. 2, the angle between directions D1 and D2 is 180 degrees.

The doped regions 106 and 108 shown in fig. 1 are a cross-sectional view of the semiconductor structure of fig. 2 along the dashed line AA'. In addition, the doped regions 106 and 108 shown in fig. 3 are a cross-sectional view of the semiconductor structure of fig. 2 along the dashed line BB'. As shown in fig. 3, the doped region 108 extends into the substrate 102. Since the doped region 108 contacts the substrate 102, the voltage of the doped region 108 is approximately equal to the ground voltage when the body region 124 receives a ground voltage through the interconnect structure 126. When the interconnect structures 120 and 126 receive a ground voltage and the doped region 106 is electrically floating, the depletion capability and driving current of the JFET formed by the drain region 118, the gate region 112 and the source region 114 can be increased, and the off-voltage of the JFET can be reduced. In addition, since the doped region 106 is electrically floating, the surface electric field of the doped region 106 can be improved. In the present embodiment, the source region 114 overlaps the doped region 108.

Fig. 4 is another possible cross-sectional view of the semiconductor structure of fig. 2 along a dashed line BB'. Fig. 4 is similar to fig. 3, except that the semiconductor device 100 of fig. 4 further includes a well 128. The well 128 is disposed in the substrate 102 and has a first conductive type. In the present embodiment, the well 128 is disposed outside the well 104 and contacts the well 104, but the present invention is not limited thereto. In other embodiments, well 128 and well 104 are spatially separated from each other.

The present invention does not limit the doping concentration of the well 128. In one possible embodiment, the doping concentration of the well 128 is higher than the doping concentration of the substrate 102 and lower than the doping concentration of the body region 124. In the present embodiment, doped region 108 extends from well 104 into well 128. Since the doped region 108 contacts the well 128, the voltage of the doped region 108 is approximately equal to the ground voltage when the body region 124 receives a ground voltage through the interconnect structure 126.

Fig. 5 to 7 show a method of manufacturing the semiconductor device 100 shown in fig. 1. Referring to fig. 5, a substrate 102, such as a silicon substrate or a Silicon On Insulator (SOI) substrate or other suitable semiconductor substrate, having a first conductivity type is provided. A well 104 is then formed in a predetermined region of the substrate 102 by doping (e.g., ion implantation) and thermal diffusion. In the present embodiment, the well 104 has a second conductivity type different from the first conductivity type. The first conductivity type is opposite to the second conductivity type.

Referring to fig. 6, doped regions 106 and 108 are formed in the well 104 by doping (e.g., ion implantation) and thermal diffusion. In one embodiment, the doped regions 106 and 108 are ring-shaped structures. Doped regions 106 and 108 are spatially separated from each other. In the present embodiment, the doped regions 106 and 108 have the first conductivity type. In one embodiment, the doping concentration of the doped regions 106 and 108 is higher than the doping concentration of the substrate 102.

Referring to fig. 7, a drain region 110, a gate region 112, a source region 114 and a body region 124 are formed by doping (e.g., ion implantation) and thermal diffusion. In the present embodiment, the drain region 110, the gate region 112 and the source region 114 are formed in the well 104, and the body region 124 is formed in the substrate 102. The gate region 112 is located between the source region 114 and the drain region 110 and overlaps the doped region 106. The source region 114 is located between the gate region 112 and the body region 124. The drain region 110 and the source region 114 have a second conductivity type. The gate regions 112 and the body regions 124 have a first conductivity type. In one possible embodiment, the doping concentration of the drain region 110 and the source region 114 is higher than the doping concentration of the well 104. In addition, the gate region 112 and the body region 124 have a higher doping concentration than the doping concentrations of the doped regions 106 and 108. In the present embodiment, the drain region 110, the gate region 112, the source region 114 and the body region 124 form a JFET.

Referring to fig. 1, an inter-layer dielectric (ILD)116 and a plurality of interconnect structures 118, 120, 122 and 126 therein may be formed on the well 104 by conventional metallization processes. The interconnect structure 118 is electrically connected to the drain region 110 to serve as a drain electrode. The interconnect structure 120 is electrically connected to the gate region 112 to serve as a gate electrode. The interconnect structure 122 is electrically connected to the source region 114 to serve as a source electrode. Interconnect structure 126 is electrically connected to substrate region 124 to serve as a substrate electrode. In this way, the semiconductor device 100 is completed.

Fig. 8 is a method of fabricating doped region 108 of region 200 of fig. 2. Since the formation of the substrate 102 and the well 104 of fig. 8 has been described above, further description is omitted. Doped regions 106 and 108 are formed in the well 104 by doping and thermal diffusion processes in sequence. As shown, the doped region 108 extends into the substrate 102 in a direction D1.

in one embodiment, a drain region, a gate region, a source region, a body region, an interlayer dielectric layer and a plurality of interconnect structures may be formed in fig. 8 by doping, thermal diffusion and metallization processes. Since the formation and characteristics of the drain region, the gate region, the source region and the body region have been described above, they are not described again. In the present embodiment, the source region (114 in fig. 7) overlaps the doped region 108.

In addition, the interlayer dielectric layer and the interconnect structure are also described above, and thus are not described again. In the present embodiment, since the doped region 108 contacts the substrate 102, when the substrate 102 is coupled to a ground voltage through a body region (e.g., 124 of fig. 7), the voltage of the doped region 108 is approximately equal to the ground voltage. In this example, the doped region 106 is electrically floating. In other embodiments, the gate region and the body region are electrically connected together and receive a ground voltage.

Fig. 9A and 9B illustrate another method for fabricating the doped region 108 of the region 200 of fig. 2. Referring to fig. 9A, wells 104 and 128 are formed in the substrate 102 by a doping process and a thermal diffusion process. In the present embodiment, well 104 has the second conductivity type and well 128 has the first conductivity type. Well 128 is located outside of well 104. Well 128 may be directly connected to well 104 or may be spatially separated from well 104. In one embodiment, the doping concentration of the well 128 is lower than the doping concentration of the substrate 102. In the present embodiment, the depth DH1 of the well 104 is greater than the depth DH2 of the well 128, but the present invention is not limited thereto. Since the formation of the substrate 102 in fig. 9A is described above, it is not repeated herein.

referring to fig. 9B, doped regions 106 and 108 are formed in the well 104 by a doping process and a thermal diffusion process. In the present embodiment, doped region 108 extends into well 128 in direction D1. Next, a drain region, a gate region, a source region, a body region, an interlayer dielectric layer and a plurality of interconnect structures may be formed in fig. 9B by using a doping process, a thermal diffusion process and a metallization process. In other embodiments, the gate region and the body region are electrically connected together and receive a ground voltage. In this example, the doped region 106 is electrically floating.

Since the formation and characteristics of the drain region, the gate region, the source region and the body region have been described above, they are not described again. In this embodiment, the source region (114 of fig. 7) will overlap the doped region 108. In addition, the interlayer dielectric layer and the interconnect structure are also described above, and thus are not described again.

When the voltage of the doped region 108 is approximately equal to a ground voltage and the doped region 106 is floating, the depletion capability and the driving current of the JFET can be increased, and the off-voltage of the JFET can be reduced. Therefore, the performance of the JFET is greatly improved.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.

Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the system, apparatus or method described in the embodiments of the present invention can be realized in hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention is subject to the claims.