阅读说明：本技术 三相三电平anpc消除共模电流逆变系统 (Three-phase three-level ANPC common-mode current elimination inversion system ) 是由 王佳宁 刘晓晖 彭强 于 2019-08-21 设计创作，主要内容包括：本发明公开了一种三相三电平ANPC消除共模电流逆变系统。所述系统包括直流电源,直流侧电路,三相三电平ANPC逆变电路,滤波电路,负载。直流电源包括直流电源对地共模寄生电容,直流侧电路包括一个共模电感,三相三电平ANPC逆变电路包括逆变主电路和两个相同的支撑电容,滤波电路包括三个相同的滤波电感,三个相同的滤波电容和一个拉回直流母线中点的电感,负载包括三条交流母线。本发明提供的逆变系统,添加的辅助元器件成本低,占用体积小,可以在高频条件下,消除不确定的直流电源寄生电容参数的影响,实现有效的共模电流消除。(The invention discloses a three-phase three-level ANPC common-mode current elimination inversion system. The system comprises a direct-current power supply, a direct-current side circuit, a three-phase three-level ANPC inverter circuit, a filter circuit and a load. The direct-current power supply comprises a direct-current power supply ground common-mode parasitic capacitor, the direct-current side circuit comprises a common-mode inductor, the three-phase three-level ANPC inverter circuit comprises an inverter main circuit and two same supporting capacitors, the filter circuit comprises three same filter inductors, three same filter capacitors and an inductor which is pulled back to the midpoint of a direct-current bus, and the load comprises three alternating-current buses. The inverter system provided by the invention has the advantages that the added auxiliary components are low in cost and small in occupied size, the influence of uncertain direct-current power supply parasitic capacitance parameters can be eliminated under the high-frequency condition, and effective common-mode current elimination is realized.)

1. The three-phase three-level ANPC common-mode current elimination inverter system comprises a direct-current power supply (10), a direct-current side circuit (20), a three-phase three-level ANPC inverter circuit (30), a filter circuit (40) and a load (50);

The three-phase three-level ANPC inverter circuit (30) comprises two same supporting capacitors, a direct-current positive bus P, a direct-current negative bus N, a direct-current bus midpoint O and an inverter main circuit (31), wherein the inverter main circuit (31) comprises an A-phase bridge arm (311), a B-phase bridge arm (312) and a C-phase bridge arm (313), each phase of bridge arm comprises 6 switching tubes with anti-parallel diodes, namely the inverter main circuit (31) comprises 18 switching tubes with anti-parallel diodes; the two supporting capacitors are respectively marked as the supporting capacitor C₁And a support capacitor C₂18 switching tubes with antiparallel diodes are respectively denoted as switching tubes S_ij18 antiparallel diodes are respectively marked as diode D_ijWhere i denotes three phases, i ═ a, b, c, j denote serial numbers of switching tubes and diodes, and j ═ 1,2,3,4,5, 6; support capacitor C₁And a support capacitor C₂After being connected in series, the capacitor C is connected in parallel with the inverter main circuit (31) and supports the capacitor C₁connected between the positive DC bus P and the midpoint O of the DC bus, and supporting a capacitor C₂The three-phase bridge arm A, B, C of the inversion main circuit (31) is connected between the direct current bus midpoint O and the direct current negative bus N in parallel; in each of the three-phase arms, a switching tube S_i1Switch tube S_i2switch tube S_i3Switch tube S_i4are sequentially connected in series, and switch tube S_i1The input end of the switch tube is connected with a direct current positive bus P and a switch tube S_i1The output end of the switch tube S_i2Of the input terminal, switching tube S_i2The output end of the switch tube S_i3Of the input terminal, switching tube S_i3The output end of the switch tube S_i4Of the input terminal, switching tube S_i4The output end of the switch tube is connected with a direct current negative bus N and a switch tube S_i5Is connected with the switch tube S_i1Of the output terminal, switching tube S_i5The output end of the switch tube S is connected with a DC bus midpoint O and a switching tube S_i6The input end of the switch tube S is connected with a DC bus midpoint O and a switching tube S_i6The output end of the switch tube S_i3An output terminal of (a); switch tube S_a2And a switching tube S_a3Is marked as point a, switch tube S_b2And a switching tube S_b3Is marked as point b, switch tube S_c2And a switching tube S_c3The common node of (a) is marked as point c;

The load (50) comprises a U-shaped alternating current bus (51), a V-shaped alternating current bus (52) and a W-shaped alternating current bus (53), wherein the end point of the U-shaped alternating current bus (51) is marked as a point U, the end point of the V-shaped alternating current bus (52) is marked as a point V, and the end point of the W-shaped alternating current bus (53) is marked as a point W; the DC power supply common mode parasitic capacitance of the DC power supply (10) is marked as C₀；

it is characterized in that the preparation method is characterized in that,

The DC-side circuit (20) comprises a common-mode inductor L_cmCommon mode inductor L_cmThe circuit comprises four terminals which are respectively marked as a terminal 1, a terminal 2, a terminal 3 and a terminal 4, wherein the side of the terminal 1 and the terminal 2 is a common-mode inductor L_cmThe same name end of (2) is located;

the filtering circuit (40) comprises the following two topologies:

Firstly, the filter circuit (40) comprises a first group of three same filter inductors, three same filter capacitors and an inductor for pulling back a midpoint O of a direct current bus, wherein the first group of three filter inductors are respectively marked as filter inductors L₁Filter inductor L₂And a filter inductance L₃The three filter capacitors are respectively marked as filter capacitor C₃filter capacitor C₄And a filter capacitor C₅And the inductance of the pull-back DC bus midpoint O is recorded as a balance inductance L₀(ii) a Filter inductance L₁Is connected with the point a, and the other end is connected with the filter capacitor C₅Series, filter inductance L₂Is connected with point b, and the other end is connected with a filter capacitor C₄Series, filter inductance L₃Is connected to point C, and the other end is connected to the filter capacitor C₃Series, filter inductance L₁And a filter capacitor C₅the common node of the series connection is marked as point d, and the filter inductance L₂And a filter capacitor C₄The common node in series is marked as point e, and the filter inductance L₃And a filter capacitor C₃The common node of the series connection is marked as point f, and the filter capacitor C₅Filter capacitor C₄Filter capacitor C₃Are connected together at the other end and are marked as a neutral point Q, balancing an inductance L₀One end of the neutral point Q is connected with the neutral point Q, and the other end of the neutral point Q is connected with the midpoint O of the direct current bus, namely the balance inductor L₀The neutral point Q is connected with the midpoint O of the direct current bus;

Secondly, the filter circuit (40) comprises a first group of three same filter inductors, a second group of three same filter inductors, three same filter capacitors and an inductor for pulling back a midpoint O of the direct current bus, wherein the first group of three filter inductors are respectively marked as filter inductors L₁filter inductor L₂Filter inductor L₃The second group of three filter inductors are respectively marked as filter inductors L₄Filter inductor L₅Filter inductor L₆The three filter capacitors are respectively marked as filter capacitor C₃Filter capacitor C₄Filter capacitor C₅And the inductance of the pull-back DC bus midpoint O is recorded as a balance inductance L₀(ii) a Filter inductance L₁Is connected to the point a, a filter inductor L₁The other end is connected with the filter capacitor C₅In series with the filter inductance L₄Series, filter inductance L₄Is marked as point d, filter inductance L₂Is connected to point b, a filter inductance L₂The other end is connected with the filter capacitor C₄In series with the filter inductance L₅Series, filter inductance L₅Is marked as point e, filter inductance L₃Is connected to point c, a filter inductance L₃The other end is connected with the filter capacitor C₃In series with the filter inductance L₆Series, filter inductance L₆Is marked as point f, filter capacitor C₅Filter capacitor C₄Filter capacitor C₃Are connected together at the other end and are marked as a neutral point Q, balancing an inductance L₀One end of the neutral point Q is connected with the neutral point Q, and the other end of the neutral point Q is connected with the midpoint O of the direct current bus, namely the balance inductor L₀The neutral point Q is connected with the midpoint O of the direct current bus;

The above-mentionedCommon mode inductor L_cmConnected in parallel between a DC power supply (10) and a three-phase three-level ANPC inverter circuit (30), wherein a common mode inductor L_cmTerminal 1 of the transformer is connected with the positive electrode of a direct current power supply (10), and a common mode inductor L_cmTerminal 2 of the common mode inductor L is connected with the negative electrode of a direct current power supply (10)_cmTerminal 3 of the transformer is connected with a direct current positive bus P and a common mode inductor L_cmThe terminal 4 of the direct current negative bus is connected with a direct current negative bus N;

An end point U of a U alternating current bus (51) of the load (50) is connected with a point d of the filter circuit (40), an end point V of a V alternating current bus (52) is connected with a point e of the filter circuit (40), and an end point W of a W alternating current bus (53) is connected with a point f of the filter circuit (40).

2. The three-phase three-level ANPC cancellation common-mode current inversion system of claim 1, wherein the common-mode inductor L is_cmIs determined by the following equation:

L_cm≥0.4L_cmstd

In the formula (I), the compound is shown in the specification,

L_cmstdIs a common mode inductor L_cmThe reference inductance value of (a);

f_corThe turning frequency of the three-phase three-level ANPC common mode current eliminating inversion system is taken as f_cor＝150kHz；

C_ph1Is the sum of the capacitances 1, C_ph1＝C_p1+C_p2Wherein, C_p1Is a switch tube S_a2Output terminal of (1), switch tube S_b2Output terminal of (1), switch tube S_c2Output terminal of (1), diode D_a2Anode of (2), diode D_b2Anode of (2), diode D_c2The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p1，C_p2Is a switch tube S_a3Input terminal of (1), switch tube S_b3Input terminal of (1), switch tube S_c3Input terminal of, diode D_a3Cathode of (2), diode D_b3Cathode, diodePipe D_c3The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p2；

C_ph2Is a capacitive sum of 2, C_ph2＝C_p3+C_p4+C_p5+C_p6+C_p7+C_p8+C_p9+C_p10+C_p11+C_p12Wherein, C_p3Is a switch tube S_a1Input terminal of (1), switch tube S_b1Input terminal of (1), switch tube S_c1Input terminal of, diode D_a1Cathode of (2), diode D_b1Cathode of (2), diode D_c1The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p3；C_p4Is a switch tube S_a1output terminal of (1), switch tube S_b1Output terminal of (1), switch tube S_c1Output terminal of (1), diode D_b1anode of (2), diode D_c1Anode of (2), diode D_a1The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p4；C_p5Is a switch tube S_a2Input terminal of (1), switch tube S_b2Input terminal of (1), switch tube S_c2Input terminal of, diode D_a2cathode of (2), diode D_b2Cathode of (2), diode D_c2the sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p5；C_p6Is a switch tube S_a5Input terminal of (1), switch tube S_b5Input terminal of (1), switch tube S_c5Input terminal of, diode D_a5Cathode of (2), diode D_b5Cathode of (2), diode D_c5The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p6；C_p7Is a switch tube S_a3Output terminal of (1), switch tube S_b3Output terminal of (1), switch tube S_c3Output terminal of (1), diode D_a3Anode of (2), diode D_b3Anode of (2), diode D_c3The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p7；C_p8Is a switch tube S_a4input terminal of (1), switch tube S_b4Input terminal of (1), switch tube S_c4Input terminal of, diode D_a4Cathode of (2), diode D_b4Of a cathodeDiode D_c4The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p8；C_p9Is a switch tube S_a6Output terminal of (1), switch tube S_b6Output terminal of (1), switch tube S_c6Output terminal of (1), diode D_a6Anode of (2), diode D_b6Anode of (2), diode D_c6The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p9；C_p10Is a switch tube S_a4Output terminal of (1), switch tube S_b4Output terminal of (1), switch tube S_c4Output terminal of (1), diode D_a4Anode of (2), diode D_b4Anode of (2), diode D_c4The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p10；C_p11Is a switch tube S_a5Output terminal of (1), switch tube S_b5Output terminal of (1), switch tube S_c5Output terminal of (1), diode D_a5Anode of (2), diode D_b5Anode of (2), diode D_c5The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p11；C_p12Is a switch tube S_a6Input terminal of (1), switch tube S_b6Input terminal of (1), switch tube S_c6Input terminal of, diode D_a6Cathode of (2), diode D_b6Cathode of (2), diode D_c6The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p12。

3. The three-phase three-level ANPC cancellation common-mode current inversion system of claim 1, wherein the balance inductor L₀Is determined by the following equation:

L₀＝(0.7～1.3)L_0std

In the formula (I), the compound is shown in the specification,

L_0stdIs a balanced inductance L₀Standard inductance value of L₁Is a filter inductance L₁；

C_ph1Is the sum of the capacitances 1, C_ph1＝C_p1+C_p2Wherein, C_p1Is a switch tube S_a2Output terminal of (1), switch tube S_b2Output terminal of (1), switch tube S_c2Output terminal of (1), diode D_a2Anode of (2), diode D_b2Anode of (2), diode D_c2The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p1，C_p2Is a switch tube S_a3Input terminal of (1), switch tube S_b3Input terminal of (1), switch tube S_c3Input terminal of, diode D_a3Cathode of (2), diode D_b3Cathode of (2), diode D_c3The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p2；

C_ph2Is a capacitive sum of 2, C_ph2＝C_p3+C_p4+C_p5+C_p6+C_p7+C_p8+C_p9+C_p10+C_p11+C_p12Wherein, C_p3is a switch tube S_a1input terminal of (1), switch tube S_b1Input terminal of (1), switch tube S_c1Input terminal of, diode D_a1Cathode of (2), diode D_b1Cathode of (2), diode D_c1The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p3；C_p4Is a switch tube S_a1Output terminal of (1), switch tube S_b1Output terminal of (1), switch tube S_c1Output terminal of (1), diode D_b1Anode of (2), diode D_c1Anode of (2), diode D_a1The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p4；C_p5Is a switch tube S_a2Input terminal of (1), switch tube S_b2Input terminal of (1), switch tube S_c2Input terminal of, diode D_a2Cathode of (2), diode D_b2Cathode of (2), diode D_c2The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p5；C_p6Is a switch tube S_a5Input terminal of (1), switch tube S_b5Input terminal of (1), switch tube S_c5Input terminal of, diode D_a5Cathode of (2), diode D_b5A cathode of,Diode D_c5The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p6；C_p7Is a switch tube S_a3Output terminal of (1), switch tube S_b3Output terminal of (1), switch tube S_c3Output terminal of (1), diode D_a3Anode of (2), diode D_b3Anode of (2), diode D_c3The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p7；C_p8Is a switch tube S_a4Input terminal of (1), switch tube S_b4Input terminal of (1), switch tube S_c4Input terminal of, diode D_a4Cathode of (2), diode D_b4Cathode of (2), diode D_c4The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p8；C_p9Is a switch tube S_a6Output terminal of (1), switch tube S_b6Output terminal of (1), switch tube S_c6Output terminal of (1), diode D_a6Anode of (2), diode D_b6Anode of (2), diode D_c6The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p9；C_p10Is a switch tube S_a4Output terminal of (1), switch tube S_b4Output terminal of (1), switch tube S_c4Output terminal of (1), diode D_a4Anode of (2), diode D_b4Anode of (2), diode D_c4The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p10；C_p11Is a switch tube S_a5Output terminal of (1), switch tube S_b5Output terminal of (1), switch tube S_c5Output terminal of (1), diode D_a5Anode of (2), diode D_b5Anode of (2), diode D_c5The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p11；C_p12Is a switch tube S_a6Input terminal of (1), switch tube S_b6Input terminal of (1), switch tube S_c6Input terminal of, diode D_a6Cathode of (2), diode D_b6Cathode of (2), diode D_c6The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p12。

Technical Field

The invention relates to the field of power electronic converters, in particular to a three-phase three-level ANPC common-mode current elimination inversion system.

Background

In an inverter system, a common-mode parasitic capacitance to the ground exists in a direct-current power supply. Uncertain common-mode parasitic capacitance to ground has a certain influence on the inversion performance, which is particularly serious in photovoltaic inversion. The non-isolated photovoltaic grid-connected power generation mode without the transformer quickly obtains attention of researchers in various countries and attention of the industry by virtue of absolute advantages of high change efficiency, small volume, light weight and low cost, and is applied to part of European countries at present. But because no transformer is used for isolation, the photovoltaic cell, the photovoltaic inverter and the power grid form a common-mode loop through the common-mode parasitic capacitance of the photovoltaic cell to the ground; in the common mode loop, the common mode voltage changes constantly, which causes the charging and discharging of the capacitor and the inductor in the common mode loop, thereby generating larger common mode current in the common mode loop. The high-frequency common-mode current can cause serious conduction and radiation interference to surrounding equipment, increase grid-connected current harmonic waves and system loss, and even endanger equipment and personal safety.

At present, the suppression of the common-mode current of the inverter under the high-frequency condition has become a hot problem of research, which has been deeply theoretically analyzed by academic papers, and has an engineering method for practical application, such as the invention patent application of "a common-mode voltage suppression system for a photovoltaic grid-connected inverter" (CN 104638891a) and "a photovoltaic grid-connected inverter common-mode current suppression circuit" (CN 207098967U).

In the "common mode voltage suppression system for photovoltaic grid-connected inverter" disclosed in chinese patent application publication CN104638891A on 20/5/2015, a second common mode filter inductor is connected in series to a differential mode filter inductor and a pull-back bus midpoint capacitor loop, so that the filter pressure of a first common mode filter inductor is reduced, and most common mode voltage is reduced to the second common mode inductor, thereby suppressing strong common mode voltage. However, the common mode voltage suppression system has the following disadvantages:

1) When the second common mode inductor uses a high permeability core, the inductor is easily saturated;

2) The influence of the uncertain common-mode stray capacitance to the ground of the direct-current power supply, namely the influence of the common-mode stray capacitance to the ground of the photovoltaic array on the common-mode current rejection is not considered;

3) In order to obtain a good common mode current suppression effect at low frequency, the required second common mode inductance parameter value is large and the size is large.

Chinese patent application publication CN207098967U public-service in 2018, 3 and 13 monthsA filter capacitor C₅、C₆And a DC bus capacitor C₁、C₂、C₃、C₄After the midpoint connection, the circuit has good effect on inhibiting the common mode current in the inverter circuit. However, the common mode current suppression circuit has the following disadvantages:

1) The circuit is not suitable for a high-frequency inverter circuit;

2) The inverter circuit is used for a two-level circuit and is difficult to be applied to a three-level circuit;

3) The influence of the uncertain common-mode stray capacitance to ground of the direct-current power supply, namely the influence of the common-mode stray capacitance to ground of the photovoltaic array on the common-mode current rejection is not considered.

Disclosure of Invention

The invention aims to solve the technical problem that the influence of the parasitic capacitance to the ground and the common mode of an uncertain direct-current power supply on the suppression of the common mode current is neglected in the prior art, and provides a three-phase three-level ANPC (analog to digital converter) common mode current eliminating inversion system which can eliminate the influence of the parasitic capacitance to the ground of the uncertain direct-current power supply under the high-frequency condition in the practical industrial application.

In order to achieve the above object, the present invention provides a three-phase three-level ANPC common mode current eliminating inverter system, which includes a dc power supply, a dc side circuit, a three-phase three-level ANPC inverter circuit, a filter circuit and a load;

The three-phase three-level ANPC inverter circuit comprises two identical supporting capacitors, a direct-current positive bus P, a direct-current negative bus N, a direct-current bus midpoint O and an inverter main circuit, wherein the inverter main circuit comprises an A-phase bridge arm, a B-phase bridge arm and a C-phase bridge arm, each phase of bridge arm comprises 6 switching tubes with anti-parallel diodes, and the inverter main circuit comprises 18 switching tubes with anti-parallel diodes in total; the two supporting capacitors are respectively marked as the supporting capacitor C₁And a support capacitor C₂18 switching tubes with antiparallel diodes are respectively denoted as switching tubes S_ij18 antiparallel diodes are respectively marked as diode D_ijWhere i denotes three phases, i ═ a, b, c, j denote serial numbers of switching tubes and diodes, and j ═ 1,2,3,4,5, 6; support capacitor C₁And a support capacitorC₂After being connected in series, the capacitor is connected in parallel with the inverter main circuit and supports the capacitor C₁Connected between the positive DC bus P and the midpoint O of the DC bus, and supporting a capacitor C₂The A, B, C three-phase bridge arms of the inversion main circuit are mutually connected in parallel between the direct current positive bus P and the direct current negative bus N; in each of the three-phase arms, a switching tube S_i1Switch tube S_i2Switch tube S_i3Switch tube S_i4Are sequentially connected in series, and switch tube S_i1The input end of the switch tube is connected with a direct current positive bus P and a switch tube S_i1The output end of the switch tube S_i2Of the input terminal, switching tube S_i2The output end of the switch tube S_i3Of the input terminal, switching tube S_i3The output end of the switch tube S_i4Of the input terminal, switching tube S_i4The output end of the switch tube is connected with a direct current negative bus N and a switch tube S_i5Is connected with the switch tube S_i1Of the output terminal, switching tube S_i5The output end of the switch tube S is connected with a DC bus midpoint O and a switching tube S_i6The input end of the switch tube S is connected with a DC bus midpoint O and a switching tube S_i6The output end of the switch tube S_i3An output terminal of (a); switch tube S_a2And a switching tube S_a3Is marked as point a, switch tube S_b2And a switching tube S_b3Is marked as point b, switch tube S_c2And a switching tube S_c3The common node of (a) is marked as point c;

The load comprises a U-shaped alternating current bus, a V-shaped alternating current bus and a W-shaped alternating current bus, wherein the end point of the U-shaped alternating current bus is marked as a point U, the end point of the V-shaped alternating current bus is marked as a point V, and the end point of the W-shaped alternating current bus is marked as a point W; the DC power supply common mode parasitic capacitance of the DC power supply is marked as C₀；

The DC side circuit comprises a common mode inductor L_cmCommon mode inductor L_cmThe circuit comprises four terminals which are respectively marked as a terminal 1, a terminal 2, a terminal 3 and a terminal 4, wherein the side of the terminal 1 and the terminal 2 is a common-mode inductor L_cmThe same name end of (2) is located;

the filter circuit comprises the following two topologies:

First, the filter circuitThe circuit comprises a first group of three same filter inductors, three same filter capacitors and an inductor for pulling back a midpoint O of the direct current bus, wherein the three filter inductors are respectively marked as filter inductors L₁Filter inductor L₂And a filter inductance L₃The three filter capacitors are respectively marked as filter capacitor C₃Filter capacitor C₄And a filter capacitor C₅And the inductance of the pull-back DC bus midpoint O is recorded as a balance inductance L₀(ii) a Filter inductance L₁Is connected with the point a, and the other end is connected with the filter capacitor C₅Series, filter inductance L₂Is connected with point b, and the other end is connected with a filter capacitor C₄Series, filter inductance L₃Is connected to point C, and the other end is connected to the filter capacitor C₃Series, filter inductance L₁And a filter capacitor C₅The common node of the series connection is marked as point d, and the filter inductance L₂And a filter capacitor C₄The common node in series is marked as point e, and the filter inductance L₃And a filter capacitor C₃The common node of the series connection is marked as point f, and the filter capacitor C₅Filter capacitor C₄Filter capacitor C₃Are connected together at the other end and are marked as a neutral point Q, balancing an inductance L₀One end of the neutral point Q is connected with the neutral point Q, and the other end of the neutral point Q is connected with the midpoint O of the direct current bus, namely the balance inductor L₀The neutral point Q is connected with the midpoint O of the direct current bus;

Secondly, the filter circuit comprises a first group of three same filter inductors, a second group of three same filter inductors, three same filter capacitors and an inductor for pulling back a midpoint O of the direct current bus, wherein the first group of three filter inductors are respectively marked as filter inductors L₁Filter inductor L₂Filter inductor L₃The second group of three filter inductors are respectively marked as filter inductors L₄Filter inductor L₅Filter inductor L₆The three filter capacitors are respectively marked as filter capacitor C₃Filter capacitor C₄Filter capacitor C₅And the inductance of the pull-back DC bus midpoint O is recorded as a balance inductance L₀(ii) a Filter inductance L₁Is connected to the point a, a filter inductor L₁The other end is connected with the filter capacitor C₅in series, also with filtrationWave inductor L₄Series, filter inductance L₄Is marked as point d, filter inductance L₂Is connected to point b, a filter inductance L₂The other end is connected with the filter capacitor C₄In series with the filter inductance L₅Series, filter inductance L₅Is marked as point e, filter inductance L₃Is connected to point c, a filter inductance L₃The other end is connected with the filter capacitor C₃In series with the filter inductance L₆Series, filter inductance L₆Is marked as point f, filter capacitor C₅Filter capacitor C₄Filter capacitor C₃Are connected together at the other end and are marked as a neutral point Q, balancing an inductance L₀One end of the neutral point Q is connected with the neutral point Q, and the other end of the neutral point Q is connected with the midpoint O of the direct current bus, namely the balance inductor L₀The neutral point Q is connected with the midpoint O of the direct current bus;

The common mode inductor L_cmConnected in parallel between a DC power supply and a three-phase three-level ANPC inverter circuit, wherein the common mode inductor L_cmTerminal 1 of the common mode inductor L is connected with the positive pole of the DC power supply_cmTerminal 2 of the common mode inductor L is connected with the negative pole of the DC power supply_cmterminal 3 of the transformer is connected with a direct current positive bus P and a common mode inductor L_cmthe terminal 4 of the direct current negative bus is connected with a direct current negative bus N;

And an end point U of a U alternating current bus of the load is connected with a point d of the filter circuit, an end point V of a V alternating current bus is connected with a point e of the filter circuit, and an end point W of a W alternating current bus is connected with a point f of the filter circuit.

Preferably, the common mode inductance L_cmIs determined by the following equation:

L_cm≥0.4L_cmstd

In the formula (I), the compound is shown in the specification,

L_cmstdIs a common mode inductor L_cmThe reference inductance value of (a);

f_corThe turning frequency of the three-phase three-level ANPC common mode current eliminating inversion system is taken as f_cor＝150kHz；

C_ph1Is the sum of the capacitances 1, C_ph1＝C_p1+C_p2Wherein, C_p1Is a switch tube S_a2Output terminal of (1), switch tube S_b2Output terminal of (1), switch tube S_c2Output terminal of (1), diode D_a2Anode of (2), diode D_b2Anode of (2), diode D_c2The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p1，C_p2Is a switch tube S_a3Input terminal of (1), switch tube S_b3Input terminal of (1), switch tube S_c3Input terminal of, diode D_a3Cathode of (2), diode D_b3Cathode of (2), diode D_c3The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p2；

C_ph2Is a capacitive sum of 2, C_ph2＝C_p3+C_p4+C_p5+C_p6+C_p7+C_p8+C_p9+C_p10+C_p11+C_p12Wherein, C_p3Is a switch tube S_a1Input terminal of (1), switch tube S_b1Input terminal of (1), switch tube S_c1Input terminal of, diode D_a1Cathode of (2), diode D_b1Cathode of (2), diode D_c1The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p3；C_p4Is a switch tube S_a1Output terminal of (1), switch tube S_b1Output terminal of (1), switch tube S_c1Output terminal of (1), diode D_b1Anode of (2), diode D_c1Anode of (2), diode D_a1The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p4；C_p5Is a switch tube S_a2Input terminal of (1), switch tube S_b2Input terminal of (1), switch tube S_c2Input terminal of, diode D_a2Cathode of (2), diode D_b2Cathode of (2), diode D_c2The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p5；C_p6Is a switch tube S_a5Input terminal of (1), switch tube S_b5input terminal of (1), switch tube S_c5The input end of,Diode D_a5Cathode of (2), diode D_b5Cathode of (2), diode D_c5the sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p6；C_p7Is a switch tube S_a3Output terminal of (1), switch tube S_b3Output terminal of (1), switch tube S_c3Output terminal of (1), diode D_a3Anode of (2), diode D_b3anode of (2), diode D_c3The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p7；C_p8Is a switch tube S_a4Input terminal of (1), switch tube S_b4Input terminal of (1), switch tube S_c4input terminal of, diode D_a4Cathode of (2), diode D_b4Cathode of (2), diode D_c4The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p8；C_p9Is a switch tube S_a6Output terminal of (1), switch tube S_b6Output terminal of (1), switch tube S_c6Output terminal of (1), diode D_a6Anode of (2), diode D_b6Anode of (2), diode D_c6The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p9；C_p10Is a switch tube S_a4Output terminal of (1), switch tube S_b4Output terminal of (1), switch tube S_c4Output terminal of (1), diode D_a4Anode of (2), diode D_b4Anode of (2), diode D_c4The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p10；C_p11Is a switch tube S_a5Output terminal of (1), switch tube S_b5Output terminal of (1), switch tube S_c5Output terminal of (1), diode D_a5Anode of (2), diode D_b5Anode of (2), diode D_c5The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p11；C_p12Is a switch tube S_a6Input terminal of (1), switch tube S_b6Input terminal of (1), switch tube S_c6Input terminal of, diode D_a6Cathode of (2), diode D_b6Cathode of (2), diode D_c6The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p12；

preferably, the balanced inductanceL₀Is determined by the following equation:

L₀＝(0.7～1.3)L_0std

In the formula (I), the compound is shown in the specification,

L_0stdIs a balanced inductance L₀Standard inductance value of L₁Is a filter inductance L₁；

C_ph1Is the sum of the capacitances 1, C_ph1＝C_p1+C_p2Wherein, C_p1Is a switch tube S_a2Output terminal of (1), switch tube S_b2Output terminal of (1), switch tube S_c2Output terminal of (1), diode D_a2Anode of (2), diode D_b2Anode of (2), diode D_c2the sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p1，C_p2Is a switch tube S_a3Input terminal of (1), switch tube S_b3Input terminal of (1), switch tube S_c3Input terminal of, diode D_a3Cathode of (2), diode D_b3Cathode of (2), diode D_c3The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p2；

C_ph2Is a capacitive sum of 2, C_ph2＝C_p3+C_p4+C_p5+C_p6+C_p7+C_p8+C_p9+C_p10+C_p11+C_p12Wherein, C_p3is a switch tube S_a1Input terminal of (1), switch tube S_b1Input terminal of (1), switch tube S_c1Input terminal of, diode D_a1Cathode of (2), diode D_b1Cathode of (2), diode D_c1The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p3；C_p4Is a switch tube S_a1Output terminal of (1), switch tube S_b1Output terminal of (1), switch tube S_c1Output terminal of (1), diode D_b1Anode of (2), diode D_c1Anode of (2), diode D_a1The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasiticCapacitor C_p4；C_p5Is a switch tube S_a2Input terminal of (1), switch tube S_b2Input terminal of (1), switch tube S_c2input terminal of, diode D_a2Cathode of (2), diode D_b2Cathode of (2), diode D_c2The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p5；C_p6Is a switch tube S_a5Input terminal of (1), switch tube S_b5Input terminal of (1), switch tube S_c5Input terminal of, diode D_a5Cathode of (2), diode D_b5Cathode of (2), diode D_c5The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p6；C_p7is a switch tube S_a3Output terminal of (1), switch tube S_b3Output terminal of (1), switch tube S_c3Output terminal of (1), diode D_a3Anode of (2), diode D_b3Anode of (2), diode D_c3the sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p7；C_p8Is a switch tube S_a4input terminal of (1), switch tube S_b4Input terminal of (1), switch tube S_c4Input terminal of, diode D_a4Cathode of (2), diode D_b4Cathode of (2), diode D_c4The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p8；C_p9Is a switch tube S_a6Output terminal of (1), switch tube S_b6Output terminal of (1), switch tube S_c6Output terminal of (1), diode D_a6Anode of (2), diode D_b6Anode of (2), diode D_c6The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p9；C_p10Is a switch tube S_a4Output terminal of (1), switch tube S_b4Output terminal of (1), switch tube S_c4Output terminal of (1), diode D_a4Anode of (2), diode D_b4Anode of (2), diode D_c4The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p10；C_p11Is a switch tube S_a5Output terminal of (1), switch tube S_b5Output terminal of (1), switch tube S_c5Output terminal of (1), diode D_a5Anode of (2), diode D_b5Anode of (2), diode D_c5The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p11；C_p12Is a switch tube S_a6Input terminal of (1), switch tube S_b6Input terminal of (1), switch tube S_c6Input terminal of, diode D_a6Cathode of (2), diode D_b6Cathode of (2), diode D_c6The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p12；

according to the technical scheme, compared with the prior art, the invention has the following advantages:

1) The three-phase three-level ANPC common mode current elimination inversion system provided by the invention has the advantages that the number of added auxiliary inductors is small, and the structure is simple;

2) The invention provides a common mode inductor L_cmThe connection mode and the parameter selection basis can effectively eliminate the negative influence on the common mode current suppression brought by the uncertain direct current power supply to the ground common mode parasitic capacitance in the prior art;

3) The inductor L provided by the invention₀The connection mode and the parameter selection basis can effectively restrain the common-mode current under the conditions of low cost and low volume occupation.

Drawings

FIG. 1 is a topology diagram of a three-phase three-level ANPC eliminating common mode current inversion system employing the present invention;

FIG. 2 is a topology diagram of a three-phase three-level ANPC cancellation common-mode current inversion system of the present invention when the filter circuit (40) is in case 1;

FIG. 3 is a topology diagram of a three-phase three-level ANPC cancellation common mode current inversion system according to the present invention when the filter inductor (40) is in case 2;

Fig. 4 is a circuit diagram of the inverter main circuit (31) of the present invention;

Fig. 5 is a distribution diagram of the common-mode parasitic capacitance to ground of the main inverter circuit (31) of the invention;

FIG. 6 shows that the filter circuit (40) is in case 1, without the common mode inductor L_cmAnd a balance inductance L₀A time common mode current simulation graph;

Figure 7 is a diagram of the case 1 filter circuit (40),C₀＝10nF，L_cm＝0.4mH，L₀A common mode current simulation result graph is obtained when the current is 6 mH;

FIG. 8 shows C when the filter circuit (40) is in case 1₀＝100nF，L_cm＝0.4mH，L₀The simulation result of the common mode current is shown in 6 mH.

Detailed Description

In order to make the purpose and technical solution of the present invention more clearly understood, the following detailed description of the embodiments of the present invention is made with reference to the accompanying drawings and examples.

Fig. 1 is a topology diagram of a three-phase three-level ANPC cancellation common mode current inverter system of the present invention, fig. 4 is a circuit diagram of an inverter main circuit 31 of the present invention, and as can be seen from fig. 1 and 4, the three-phase three-level ANPC cancellation common mode current inverter system of the present invention includes a dc power supply 10, a dc side circuit 20, a three-phase three-level ANPC inverter circuit 30, a filter circuit 40, and a load 50.

The three-phase three-level ANPC inverter circuit 30 comprises two same supporting capacitors, a direct-current positive bus P, a direct-current negative bus N, a direct-current bus midpoint O and an inverter main circuit 31. Fig. 4 is a circuit diagram of the inverter main circuit 31 of the present invention, and as can be seen from fig. 4, the inverter main circuit 31 includes an a-phase arm 311, a B-phase arm 312, and a C-phase arm 313. Each phase bridge arm comprises 6 switching tubes with anti-parallel diodes, namely the main inverter circuit 31 comprises 18 switching tubes with anti-parallel diodes. The two supporting capacitors are respectively marked as the supporting capacitor C₁And a support capacitor C₂18 switching tubes with antiparallel diodes are respectively denoted as switching tubes S_ij18 antiparallel diodes are respectively marked as diode D_ijWhere i denotes three phases, i is a, b, c, j denotes serial numbers of switching tubes and diodes, and j is 1,2,3,4,5, 6. Support capacitor C₁And a support capacitor C₂Connected in parallel with the main inverter circuit 31 after being connected in series, and supporting a capacitor C₁Connected between the positive DC bus P and the midpoint O of the DC bus, and supporting a capacitor C₂The three-phase bridge arm A, B, C of the main inverter circuit 31 is connected in parallel between the positive dc bus P and the negative dc bus N. In each of the three-phase armsSwitching tube S_i1Switch tube S_i2Switch tube S_i3Switch tube S_i4Are sequentially connected in series, and switch tube S_i1The input end of the switch tube is connected with a direct current positive bus P and a switch tube S_i1The output end of the switch tube S_i2Of the input terminal, switching tube S_i2The output end of the switch tube S_i3Of the input terminal, switching tube S_i3The output end of the switch tube S_i4Of the input terminal, switching tube S_i4The output end of the switch tube is connected with a direct current negative bus N and a switch tube S_i5Is connected with the switch tube S_i1Of the output terminal, switching tube S_i5The output end of the switch tube S is connected with a DC bus midpoint O and a switching tube S_i6The input end of the switch tube S is connected with a DC bus midpoint O and a switching tube S_i6The output end of the switch tube S_i3To the output terminal of (a). Switch tube S_a2And a switching tube S_a3Is marked as point a, switch tube S_b2And a switching tube S_b3Is marked as point b, switch tube S_c2And a switching tube S_c3Is denoted as point c.

The load 50 includes a U-phase ac bus 51, a V-phase ac bus 52, and a W-phase ac bus 53. The end point of the U-phase alternating current bus 51 is denoted as a point U, the end point of the V-phase alternating current bus 52 is denoted as a point V, and the end point of the W-phase alternating current bus 53 is denoted as a point W; the common mode parasitic capacitance of the dc power supply 10 to ground is marked as C₀。

The DC side circuit 20 includes a common mode inductor L_cmCommon mode inductor L_cmIncluding four terminals, denoted as terminal 1, terminal 2, terminal 3, and terminal 4, respectively. Wherein, the side of the terminal 1 and the terminal 2 is a common mode inductor L_cmThe same name end of (1) is located.

The filter circuit 40 includes the following two topologies.

The first one is shown in fig. 2, and comprises a first group of three identical filter inductors, three identical filter capacitors and an inductor which is pulled back to the midpoint O of the direct current bus. The three filter inductors are respectively marked as filter inductors L₁Filter inductor L₂And a filter inductance L₃The three filter capacitors are respectively marked as filter capacitor C₃Filter capacitor C₄And a filter circuitContainer C₅And the inductance of the pull-back DC bus midpoint O is recorded as a balance inductance L₀. Filter inductance L₁Is connected with the point a, and the other end is connected with the filter capacitor C₅Series, filter inductance L₂is connected with point b, and the other end is connected with a filter capacitor C₄Series, filter inductance L₃Is connected to point C, and the other end is connected to the filter capacitor C₃Are connected in series. Filter inductance L₁And a filter capacitor C₅The common node of the series connection is marked as point d, and the filter inductance L₂And a filter capacitor C₄The common node in series is marked as point e, and the filter inductance L₃And a filter capacitor C₃The common node in the series is denoted as point f. Filter capacitor C₅Filter capacitor C₄Filter capacitor C₃The other ends of which are connected together and are denoted as neutral point Q. Balance inductance L₀One end of the neutral point Q is connected with the neutral point Q, and the other end of the neutral point Q is connected with the midpoint O of the direct current bus, namely the balance inductor L₀A balance inductor L connected between the neutral point Q and the DC bus midpoint O₀Simultaneous and filter capacitor C₃Filter capacitor C₄Filter capacitor C₅Are connected in series.

The second type is shown in fig. 3, and comprises a first group of three identical filter inductors, a second group of three identical filter inductors, three identical filter capacitors, and an inductor which is pulled back to the midpoint O of the direct current bus. The first three filter inductors are respectively marked as filter inductors L₁Filter inductor L₂Filter inductor L₃The second group of three filter inductors are respectively marked as filter inductors L₄Filter inductor L₅Filter inductor L₆The three filter capacitors are respectively marked as filter capacitor C₃Filter capacitor C₄filter capacitor C₅And the inductance of the pull-back DC bus midpoint O is recorded as a balance inductance L₀. Filter inductance L₁Is connected to the point a, a filter inductor L₁The other end is connected with the filter capacitor C₅In series with the filter inductance L₄Series, filter inductance L₄Is marked as point d, filter inductance L₂Is connected to point b, a filter inductance L₂The other end is connected with the filter capacitor C₄In series, and also filteringInductor L₅Series, filter inductance L₅Is marked as point e, filter inductance L₃Is connected to point c, a filter inductance L₃The other end is connected with the filter capacitor C₃in series with the filter inductance L₆Series, filter inductance L₆Is marked as point f, filter capacitor C₅Filter capacitor C₄Filter capacitor C₃The other ends of which are connected together and are denoted as neutral point Q. Balance inductance L₀One end of the neutral point Q is connected with the neutral point Q, and the other end of the neutral point Q is connected with the midpoint O of the direct current bus, namely the balance inductor L₀Connected between neutral point Q and dc bus midpoint O.

The common mode inductor L_cmConnected in parallel between the dc power supply 10 and the three-phase three-level ANPC inverter circuit 30. Wherein, the positive pole of the DC power supply 10 is connected with a common mode inductor L_cmTerminal 1, the negative electrode of the dc power supply 10 is connected to the common mode inductor L_cmTerminal 2, common mode inductance L_cmTerminal 3 of the transformer is connected with a direct current positive bus P and a common mode inductor L_cmThe terminal 4 of the transformer is connected with a direct current negative bus N.

The terminal U of the U-phase ac bus 51 of the load is connected to the point d of the filter circuit 40, the terminal V of the V-phase ac bus 52 is connected to the point e of the filter circuit 40, and the terminal W of the W-phase ac bus 53 is connected to the point f of the filter circuit 40.

In the three-phase three-level ANPC elimination common-mode current inversion system, the common-mode inductor L_cmThe inductance value of (a) is determined by the equation (1):

L_cm≥0.4L_cmstd (1)

(2) In the formula (I), the compound is shown in the specification,

L_cmstdIs a common mode inductor L_cmThe reference inductance value of (a); f. of_corThe turning frequency of the three-phase three-level ANPC common mode current eliminating inversion system is taken as f_cor＝150kHz；C_ph1is the sum of the capacitances 1, C_ph2Is the capacitive sum of 2.

In the three-phase three-level ANP of the inventionIn the C eliminating common mode current inversion system, the balance inductor L₀The inductance value of (c) is determined by the equation (3):

L₀＝(0.7～1.3)L_0std (3)

(4) In the formula, L_0stdIs a balanced inductance L₀Standard inductance value of L₁Is a filter inductance L₁，C_ph1Is the sum of the capacitances 1, C_ph2Is the capacitive sum of 2.

In the formulas (2) and (4), the sum of the capacitances is 1C_ph1Capacitive sum 2C_ph2The formula of (1) is as follows:

C_ph1＝C_p1+C_p2

C_ph2＝C_p3+C_p4+C_p5+C_p6+C_p7+C_p8+C_p9+C_p10+C_p11+C_p12

Wherein: c_p1Is a switch tube S_a2Output terminal of (1), switch tube S_b2Output terminal of (1), switch tube S_c2Output terminal of (1), diode D_a2Anode of (2), diode D_b2Anode of (2), diode D_c2The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p1；C_p2Is a switch tube S_a3Input terminal of (1), switch tube S_b3Input terminal of (1), switch tube S_c3Input terminal of, diode D_a3Cathode of (2), diode D_b3Cathode of (2), diode D_c3The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p2；C_p3Is a switch tube S_a1Input terminal of (1), switch tube S_b1Input terminal of (1), switch tube S_c1Input terminal of, diode D_a1Cathode of (2), diode D_b1cathode of (2), diode D_c1The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p3；C_p4Is a switch tube S_a1Output terminal of (1), switch tube S_b1Output of (2)Terminal, switch tube S_c1Output terminal of (1), diode D_a1Anode of (2), diode D_b1Anode of (2), diode D_c1The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p4；C_p5Is a switch tube S_a2Input terminal of (1), switch tube S_b2Input terminal of (1), switch tube S_c2Input terminal of, diode D_a2Cathode of (2), diode D_b2Cathode of (2), diode D_c2The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p5；C_p6Is a switch tube S_a5input terminal of (1), switch tube S_b5Input terminal of (1), switch tube S_c5input terminal of, diode D_a5Cathode of (2), diode D_b5Cathode of (2), diode D_c5The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p6；C_p7Is a switch tube S_a3Output terminal of (1), switch tube S_b3Output terminal of (1), switch tube S_c3Output terminal of (1), diode D_a3Anode of (2), diode D_b3Anode of (2), diode D_c3The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p7；C_p8is a switch tube S_a4Input terminal of (1), switch tube S_b4Input terminal of (1), switch tube S_c4Input terminal of, diode D_a4Cathode of (2), diode D_b4Cathode of (2), diode D_c4The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p8；C_p9Is a switch tube S_a6Output terminal of (1), switch tube S_b6Output terminal of (1), switch tube S_c6output terminal of (1), diode D_a6Anode of (2), diode D_b6Anode of (2), diode D_c6the sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p9；C_p10Is a switch tube S_a4Output terminal of (1), switch tube S_b4Output terminal of (1), switch tube S_c4output terminal of (1), diode D_a4anode of (2), diode D_b4Anode of (2), diode D_c4The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p10；C_p11Is a switch tubeS_a5Output terminal of (1), switch tube S_b5Output terminal of (1), switch tube S_c5Output terminal of (1), diode D_a5Anode of (2), diode D_b5Anode of (2), diode D_c5The sum of the anode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p11；C_p12Is a switch tube S_a6Input terminal of (1), switch tube S_b6Input terminal of (1), switch tube S_c6Input terminal of, diode D_a6Cathode of (2), diode D_b6Cathode of (2), diode D_c6The sum of the cathode-to-ground common-mode parasitic capacitance is recorded as parasitic capacitance C_p12. Fig. 5 shows a distribution diagram of the common-mode parasitic capacitance to ground of the main inverter circuit 31 of the present invention.

In order to verify the effectiveness of the present invention, simulation verification was performed. The DC side voltage is 300V, the switch tube S_ijThe switching frequency of (2) is 40kHz, the modulation degree is 0.9, and the filter circuit used is case 1, in which the filter inductance L is₁Filter inductor L₂Filter inductor L₃All inductance values of (1) are 90uH, and the filter capacitor C₃Filter capacitor C₄Filter capacitor C₅All of the capacitance values of (1) are 10pF, the sum of the capacitances is 1C_ph110500pF, sum of capacitances 2C_ph22100pF, and taking L according to the formulas (1) and (3)_cm＝0.4mH，L₀6 mH. First, as shown in FIG. 6, no common mode inductor L is added to the inverter system_cmAnd a balance inductance L₀A simulated plot of the common mode current. Selecting C aiming at uncertain DC power supply to ground common mode parasitic capacitance by simulation₀10pF and C₀The verification was performed at 100 pF. FIG. 7 shows that when the DC side is C as the parameter of the common mode parasitic capacitance to ground₀At 10pF, a common mode inductor L is added_cmAnd a balance inductance L₀Then, the common mode current simulation diagram of the inverter system of the invention. FIG. 8 shows that when the DC side is C as the parameter of the common mode parasitic capacitance to ground₀At 100pF, a common mode inductor L is added_cmAnd a balance inductance L₀Then, the common mode current simulation diagram of the inverter system of the invention. As can be seen from FIGS. 7 and 8, the present invention can eliminate the parasitic capacitance of uncertain DC power supply to ground under high frequency conditionThe affected three-phase three-level ANPC eliminates the common mode current inversion system.