阅读说明：本技术 应用于集成磁隔离芯片的边沿转换方法及编解码电路 (edge conversion method and coding and decoding circuit applied to integrated magnetic isolation chip ) 是由 李威 袁思彤 文守甫 罗和平 王建斌 程瑜 于 2019-08-22 设计创作，主要内容包括：应用于集成磁隔离芯片的边沿转换方法及编解码电路,涉及集成电路技术。本发明的编码电路包括下述部分：外部信号输入端；第一与门,其一个输入端接外部信号输入端,另一个输入端接边沿检测电路的输出端,其输出端接变压器的原端绕组第一端；第二与门,其一个输入端接边沿检测电路的输出端,另一个输入端接反相器的输出端,其输出端接变压器的原端绕组第二端；边沿检测电路,其输入端接外部信号输入端；反相器,其输入端接外部信号输入端；变压器副端绕组的一端作为转换输出端,另一端接地。本发明能大大提高信号传输速率。同时,实施该方案只需要一个变压器,芯片面积小。(an edge conversion method and a coding and decoding circuit applied to an integrated magnetic isolation chip relate to the integrated circuit technology. The encoding circuit of the present invention includes the following parts: an external signal input terminal; one input end of the first AND gate is connected with an external signal input end, the other input end of the first AND gate is connected with the output end of the edge detection circuit, and the output end of the first AND gate is connected with the first end of the primary winding of the transformer; one input end of the second AND gate is connected with the output end of the edge detection circuit, the other input end of the second AND gate is connected with the output end of the inverter, and the output end of the second AND gate is connected with the second end of the primary winding of the transformer; the input end of the edge detection circuit is connected with the external signal input end; the input end of the inverter is connected with the external signal input end; one end of the secondary winding of the transformer is used as a conversion output end, and the other end of the secondary winding of the transformer is grounded. The invention can greatly improve the signal transmission rate. Meanwhile, only one transformer is needed for implementing the scheme, and the chip area is small.)

1. The edge conversion method applied to the integrated magnetic isolation chip is characterized by comprising the following steps of:

Detecting an input signal;

converting the rising edge into a positive pulse and the falling edge into a negative pulse; alternatively, the rising edge is converted to a negative pulse and the falling edge is converted to a positive pulse.

2. The edge transition coding circuit applied to the integrated magnetic isolation chip is characterized by comprising the following parts:

An external signal input terminal;

one input end of the first AND gate is connected with an external signal input end, the other input end of the first AND gate is connected with the output end of the edge detection circuit, and the output end of the first AND gate is connected with the first end of the primary winding of the transformer;

One input end of the second AND gate is connected with the output end of the edge detection circuit, the other input end of the second AND gate is connected with the output end of the inverter, and the output end of the second AND gate is connected with the second end of the primary winding of the transformer;

The input end of the edge detection circuit is connected with the external signal input end;

the input end of the inverter is connected with the external signal input end;

One end of the secondary winding of the transformer is used as a conversion output end, and the other end of the secondary winding of the transformer is grounded.

3. the edge-shifting encoder circuit applied to the integrated magnetic isolation chip of claim 2, wherein the output end of the first AND gate is connected to the transformer through a delay circuit, and the output end of the second AND gate is connected to the transformer through a delay circuit.

4. The edge conversion decoding circuit applied to the integrated magnetic isolation chip is characterized by comprising the following parts:

A decoding reference point connected with the coding signal input end through a first capacitor;

a first resistor (R1), a second capacitor (C2) connected in series between the decoded reference point and the reference voltage point;

A second resistor (R2) connecting the decoded reference point and the reference voltage point;

The positive input end of the first comparator is connected with the reference voltage point, the negative input end of the first comparator is connected with the decoding reference point, and the output end of the first comparator is connected with the first input end of the RS trigger;

the negative input end of the second comparator is connected with the reference voltage point, the positive input end of the second comparator is connected with the decoding reference point, and the output end of the second comparator is connected with the second input end of the RS trigger;

And the output end of the RS trigger is used as the output end of the decoding circuit.

Technical Field

the present invention relates to integrated circuit technology.

Background

the isolator is used for isolating circuit modules with independent functions in a circuit system in the occasions of medical treatment, communication, industrial bus control and the like, so that the mutual influence among the functional modules is avoided, and a sensitive circuit is protected from being damaged by dangerous voltage and current. In fig. 2, 3 and 4 it is shown that two grounds, gnd1 and gnd2, gnd1 and gnd2, may be at different potentials.

The circuit isolation device which is used in large quantity for a long time is an optical coupler device, but the optical coupler device has short service life, low data transmission rate, unstable performance and overlarge volume, and the defects are very obvious.

a new way of isolation that has emerged in the last decade is isolation using on-chip integrated transformers as the isolation devices, i.e. magnetic coupling isolation. The integrated transformer on the chip is processed on a silicon chip, and a layer of isolation material is arranged between a primary end coil and a secondary end coil of the transformer, so that the isolation effect is achieved. Magnetic coupling isolation data communication over the isolation layer is achieved by means of a varying magnetic field between the two coils using the law of electromagnetic induction. The magnetic coupling isolation has the advantages of long service life, high data transmission rate, stable performance, small volume and the like.

fig. 1(a) is a schematic diagram of such chip architecture, in which DIE1, DIE2, and DIE3 are an encoder chip, a decoder chip, and a silicon-based transformer chip, respectively, DIE1 and DIE2 are designed using conventional CMOS processes, and DIE3 is designed using a self-developed manufacturing process. The three dice, DIE1, DIE2, and DIE3, are integrated into a package and connected by package wires.

Because the integrated magnetic coupling isolation device is small in size and small in coil inductance, the coupling coefficient of the primary end coil and the secondary end coil in a high-frequency section is higher, and the integrated magnetic coupling isolation device is more beneficial to signal transmission, the input low-frequency square wave signal is generally coded, and the frequency of the coded low-frequency square wave signal is improved so as to be beneficial to transmission of the coded low-frequency square wave signal through a transformer. One commonly used method of increasing the frequency is to perform edge detection on the incoming square wave signal, convert the rising and falling edges of the square wave signal into short pulses of about two nanoseconds duration, and then restore them to the rising or falling edges of the square wave after the pulses have passed through the transformer. This method has a problem of how to distinguish between rising and falling edges. Fig. 1(b) is a flowchart of this codec process.

Document [ 1 ] describes a method of transmitting a rising-edge pulse and a falling-edge pulse separately using two transformers, as shown in fig. 2. In the scheme, the rising edge and the falling edge of an input square wave are respectively converted into a single pulse, then the two single pulses are respectively transmitted by two different transformers, and after passing through the transformers, the two single pulses are respectively restored into the rising edge and the falling edge. The disadvantage of this approach is that two transformers are required, wasting chip area.

document [ 2 ] and document [ 3 ] describe a double-single pulse coding scheme, as shown in fig. 3. In this scheme, the rising edge is represented by a double pulse and the falling edge is represented by a single pulse. The disadvantage of this solution is that the decoding circuit needs to recognize double pulses and single pulses, and a certain distance is needed between the double pulses and the single pulses, which affects the data transmission rate (i.e. a certain distance is needed between the rising edge and the falling edge of the input square wave signal, so that the frequency of the square wave signal cannot be too high). Meanwhile, the encoding and decoding circuits are relatively complex.

By search, the maximum transmission rate of the magnetic coupling isolation product on the market is 150Mbps (bps is bit per second, which is applied to non-return-to-zero signals, the same applies below), namely 75MHz square wave frequency (see literature [ 4 ]).

Reference documents:

[1]B.Chen,J.Wynne,and R.Lkiger,“High speed digital isolators using microscale on-chip transformers,”Elektronik Mag.,2003.

[2]B.Chen,“Fully integrated isolated DC-DC converter using microtransformers,”in Proc.23rd Annual IEEE Applied Power Electronics Conf.,Feb.2008,pp.335–338.[3]B.Chen,“Isolated half-bridge gate driver with integrated high-side supply,”in Proc.IEEE Power Electronics SpecialistsConf.,Jun.2008,pp.3615–3618.

[4]Digital-Isolator-Product-Selection-Guide.pdf，

http://www.analog.com/media/en/technical-documentation/product-selector-card/Digi tal-Isolator-Product-Selection-Guide.pdf

disclosure of Invention

The technical problem to be solved by the invention is to provide a simple and easy encoding and decoding scheme for distinguishing the rising edge and the falling edge of an input square wave signal aiming at the magnetic coupling isolation technology, so that the area of a chip is reduced and the transmission rate of data is improved.

The technical scheme adopted by the invention for solving the technical problems is that,

the edge conversion method applied to the integrated magnetic isolation chip is characterized by comprising the following steps of:

Detecting an input signal;

converting the rising edge into a positive pulse and the falling edge into a negative pulse; alternatively, the rising edge is converted to a negative pulse and the falling edge is converted to a positive pulse.

The invention also provides an edge conversion coding circuit applied to the integrated magnetic isolation chip, which is characterized by comprising the following parts:

An external signal input terminal;

One input end of the first AND gate is connected with an external signal input end, the other input end of the first AND gate is connected with the output end of the edge detection circuit, and the output end of the first AND gate is connected with the first end of the primary winding of the transformer;

One input end of the second AND gate is connected with the output end of the edge detection circuit, the other input end of the second AND gate is connected with the output end of the inverter, and the output end of the second AND gate is connected with the second end of the primary winding of the transformer;

The input end of the edge detection circuit is connected with the external signal input end;

the input end of the inverter is connected with the external signal input end;

One end of the secondary winding of the transformer is used as a conversion output end, and the other end of the secondary winding of the transformer is grounded.

the output end of the first AND gate is connected with the transformer through the delay circuit, and the output end of the second AND gate is connected with the transformer through the delay circuit.

the invention also provides an edge conversion decoding circuit applied to the integrated magnetic isolation chip, which is characterized by comprising the following parts:

A decoding reference point connected with the coding signal input end through a first capacitor;

a first resistor R1 and a second capacitor C2 connected in series between the decoding reference point and the reference voltage point;

a second resistor R2 connecting the decoding reference point and the reference voltage point;

the positive input end of the first comparator is connected with the reference voltage point, the negative input end of the first comparator is connected with the decoding reference point, and the output end of the first comparator is connected with the first input end of the RS trigger;

The negative input end of the second comparator is connected with the reference voltage point, the positive input end of the second comparator is connected with the decoding reference point, and the output end of the second comparator is connected with the second input end of the RS trigger;

And the output end of the RS trigger is used as the output end of the decoding circuit. One of the two outputs of the RS flip-flop can be selected.

the invention uses the positive and negative polarities of the pulse to distinguish the rising edge and the falling edge of the input square wave, the coding and decoding circuit is simple and easy to operate, and the signal transmission rate can be greatly improved. Meanwhile, only one transformer is needed for implementing the scheme, and the chip area is small. Simulation verification shows that the data transmission rate of the scheme can reach over 250 Mbps.

drawings

Fig. 1 is a schematic diagram of a chip architecture and a data transmission flow of a circuit isolator, where a is a schematic diagram of the chip architecture and b is a schematic diagram of the data transmission flow.

Fig. 2 is a schematic diagram of a forward single-pulse dual-transformer codec scheme.

FIG. 3 is a schematic diagram of a double-single pulse codec scheme.

Fig. 4 is a schematic diagram of a positive and negative pulse encoding and decoding scheme.

fig. 5 is a schematic diagram of an encoder.

Fig. 6 is an encoding timing diagram.

Fig. 7 is a schematic diagram of a decoder.

Fig. 8 is a decoding timing diagram.

Detailed Description

Referring to fig. 4, the rising edge and the falling edge of the input square wave respectively pour forward and reverse pulse currents into the primary end of the transformer. When the positive pulse current is poured, the secondary end of the transformer induces a positive voltage to generate a positive pulse; when reverse pulse current is poured, negative voltage is induced at the secondary end of the transformer, and a negative pulse appears. The positive and negative pulses are restored by the decoder to the rising and falling edges of the square wave, respectively.

fig. 5 and 6 are schematic diagrams of an encoding circuit and an encoding timing diagram thereof, respectively. Fig. 6 shows waveforms corresponding to the respective nodes (N1, N2, N3, N4, N5, and N6) in fig. 5. In fig. 5, after the input square wave signal passes through the edge detection circuit, its rising edge and falling edge each generate a positive pulse at N3. At N4, only positive going pulses generated by the rising edge can occur; at N5, only the positive going pulse generated by the falling edge can occur. When a positive pulse occurs at N4, the potential at N5 is zero, current flows from N4 to N5, and a positive pulse voltage is induced at N6; when a positive pulse occurs at N5, the potential at N4 is zero, current flows from N5 to N4, and a negative pulse voltage is induced at N6. The voltages of the nodes N1-N5 and their timing relationships are shown in FIG. six.

fig. 7 and 8 are schematic diagrams of a decoding circuit and a decoding timing diagram thereof, respectively. Fig. 8 shows waveforms corresponding to respective nodes (N1, N2, N3, N4, N5, and Q) in fig. 7. In fig. 7, the common-mode reference voltage VCM is set to half the supply voltage. The voltage induced by the secondary terminal of the transformer is at the position N1, the voltage at the position N2 is the voltage obtained by dividing the voltage of N1 by the capacitors C1 and C2, and the voltage is a pulse voltage taking VCM as reference. Considering the voltage dividing effect of the capacitors C1 and C2, the relationship between the peak voltage VN2 at N2 and the peak voltage VN1 at N1 is:

resistors R1 and R2 provide a discharge path for capacitor C2, and the voltage at N2 is equal to VCM when no pulse is coming. R1 and C2 also together form a buffer circuit that reduces voltage ringing at N2.

COMP1 and COMP2 are two hysteretic comparators, followed by an RS flip-flop, Q being the output of the decoding circuit. When the positive pulse arrives, the COMP2 outputs a positive pulse, N4 is 1 for a short time, N3 is kept to be 0, Q is set, and the rising edge of the input square wave is recovered; when a negative pulse arrives, the COMP1 outputs a positive pulse, N3 is 1 for a short time, N4 is kept to be 0, and the falling edge of the input square wave is recovered; when no pulse arrives, N3 and N4 are both 0, and the RS flip-flop remains in the current state. The voltages at the various nodes of N1 through Q and their timing relationships are shown in FIG. 8.

In practical applications, the width of the positive and negative pulses generated by the encoder in fig. 5 may be set to 1 to 2 ns, the distance between the positive and negative pulses is also set to 1 to 2 ns, and the actual transmission data rate is greater than 250 Mbps. The circuit proposed by this scheme can be implemented using a 0.5 micron integrated circuit fabrication process.